®

DAC80
FPO
FPO 41% DAC80P

Monolithic 12-Bit
DIGITAL-TO-ANALOG CONVERTERS

FEATURES resistors, as well as low integral and differential lin-

earity errors. Innovative circuit design enables the
● INDUSTRY STANDARD PINOUT DAC80 to operate at supply voltages as low as ±11.4V
● FULL ±10V SWING WITH VCC = ±12VDC with no loss in performance or accuracy over any
● DIGITAL INPUTS ARE TTL- AND range of output voltage. The lower power dissipation
CMOS-COMPATIBLE of this 118-mil by 121-mil chip results in higher
reliability and greater long term stability.
● GUARANTEED SPECIFICATIONS WITH
±12V AND ±15V SUPPLIES Burr-Brown has further enhanced the reliability of the
monolithic DAC80 by offering a hermetic, side-brazed,
● ±1/2LSB MAXIMUM NONLINEARITY:
ceramic package. In addition, ease of use has been
0°C to +70°C
enhanced by eliminating the need for a +5V logic
● SETTLING TIME: 4µs max to ±0.01% of power supply.
Full Scale
For applications requiring both reliability and low
● GUARANTEED MONOTONICITY: cost, the DAC80P in a molded plastic package offers
0°C to +70°C the same electrical performance over temperature as
● TWO PACKAGE OPTIONS: Hermetic side- the ceramic model. The DAC80P is available with
brazed ceramic and low-cost molded voltage output only.
plastic
For designs that require a wider temperature range, see
Burr-Brown models DAC85H and DAC87H.

DESCRIPTION Reference
This monolithic digital-to-analog converter is pin-for-
pin equivalent to the industry standard DAC80 first
introduced by Burr-Brown. Its single-chip design in- 12-Bit Reference
Resistor Gain
Digital Inputs

cludes the output amplifier and provides a highly Control

Ladder Adjustment
Circuit
stable reference capable of supplying up to 2.5mA to Network
Scaling
an external load without degradation of D/A perfor- and
Network
Current
mance. Switches
This converter uses proven circuit techniques to pro- Analog
vide accurate and reliable performance over tempera- Output
ture and power supply variations. The use of a buried
zener diode as the basis for the internal reference Offset
contributes to the high stability and low noise of the Adjustment
+ Supply
device. Advanced methods of laser trimming result in
– Supply
precision output current and output amplifier feedback

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©1986 Burr-Brown Corporation PDS-643F Printed in U.S.A. July, 1993

SPECIFICATIONS
ELECTRICAL
Typical at +25°C and ±VCC = 12V or 15V unless otherwise noted.

DAC80
PARAMETER MIN TYP MAX UNITS
DIGITAL INPUT
Resolution 12 Bits
Logic Levels (0°C to +70°C)(1):
VIH (Logic “1”) +2 +16.5 VDC
VIL (Logic “0”) 0 +0.8 VDC
IIH (VIN = +2.4V) +20 µA
IIL (VIN = +0.4V) –180 µA
ACCURACY (at +25°C)
Linearity Error ±1/4 ±1/2 LSB
Differential Linearity Error ±1/2 ±3/4 LSB
Gain Error(2) ±0.1 ±0.3 %
Offset Error(2) ±0.05 ±0.15 % of FSR(3)
DRIFT (0°C to +70°C)(4)
Total Bipolar Drift (includes gain, offset, and linearity drifts) ±10 ±25 ppm of FSR/°C
Total Error Over 0°C to +70°C(5)
Unipolar ±0.06 ±0.15 % of FSR
Bipolar ±0.06 ±0.12 % of FSR
Gain: Including Internal Reference ±10 ±30 ppm/°C
Excluding Internal Reference ±5 ±10 ppm/°C
Unipolar Offset ±1 ±3 ppm of FSR/°C
Bipolar Offset ±7 ±15 ppm of FSR/°C
Differential Linearity 0°C to +70°C ±1/2 ±3/4 LSB
Linearity Error 0°C to +70°C ±1/4 ±1/2 LSB
Monotonicity Guaranteed 0 +70 °C
CONVERSION SPEED, VOUT Models
Settling Time to ±0.01% of FSR
For FSR Change (2kΩ || 500pF Load)
with 10kΩ Feedback 3 4 µs
with 5kΩ Feedback 2 3 µs
For 1LSB Change 1 µs
Slew Rate 10 V/µs
CONVERSION SPEED, IOUT Models
Settling Time to ±0.01% of FSR
For FSR change: 10Ω to 100Ω Load 300 ns
1kΩ Load 1 µs
ANALOG OUTPUT, VOUT Models
Ranges ±2.5, ±5, ±10, +5, +10 V
Output Current(6) ±5 mA
Output Impedance (DC) 0.05 Ω
Short Circuit to Common, Duration(7) Indefinite
ANALOG OUTPUT, IOUT Models
Ranges: Bipolar ±0.96 ±1.0 ±1.04 mA
Unipolar –1.96 –2.0 –2.04 mA
Output Impendance: Bipolar 2.6 3.2 3.7 kΩ
Unipolar 4.6 6.6 8.6 kΩ
Compliance –2.5 +2.5 V
REFERENCE VOLTAGE OUTPUT +6.23 +6.30 +6.37 V
External Current (constant load) 2.5 mA
Drift vs Temperature ±10 ±20 ppm/°C
Output Impedance 1 Ω
POWER SUPPLY SENSITIVITY
VCC = ±12VDC or ±15VDC ±0.002 ±0.006 % FSR/ % VCC
POWER SUPPLY REQUIREMENTS
±VCC ±11.4 ±16.5 VDC
Supply Drain (no load): +VCC 8 12 mA
–VCC 15 20 mA
Power Dissipation (VCC = ±15VDC) 345 480 mW
TEMPERATURE RANGE
Specification 0 +70 °C
Operating –25 +85 °C
Storage: Plastic DIP –60 +100 °C
Ceramic DIP –65 +150 °C

NOTES: (1) Refer to “Logic Input Compatibility” section. (2) Adjustable to zero with external trim potentiometer. (3) FSR means full scale range and is 20V for ±10V range,
10V for ±5V range for VOUT models; 2mA for IOUT models. (4) To maintain drift spec, internal feedback resistors must be used. (5) Includes the effects of gain, offset
and linearity drift. Gain and offset errors externally adjusted to zero at +25°C. (6) For ±VCC less than ±12VDC, limit output current load to ±2.5mA to maintain ±10V full
scale output voltage swing. For output range of ±5V or less, the output current is ±5mA over entire ±VCC range. (7) Short circuit current is 40mA, max.

DAC80/80P 2
FUNCTIONAL DIAGRAM AND PIN ASSIGNMENTS

Voltage Models Current Models

(MSB) Bit 1 1 24 6.3V Ref Out (MSB) Bit 1 1 24 6.3V Ref Out
Reference Reference
Bit 2 2 Control 23 Gain Adjust Bit 2 2 Control 23 Gain Adjust
Circuit Circuit
Bit 3 3 22 +VCC Bit 3 3 22 +VCC

Bit 4 4 21 Common Bit 4 4 21 Common

12-Bit 12-Bit
Bit 5 5 20 Summing Junction Bit 5 5 20 Scaling Network
Resistor 5kΩ Resistor 2kΩ
Bit 6 6 Ladder 19 20V Range Bit 6 6 Ladder 19 Scaling Network
3kΩ
Network 5kΩ Network
Bit 7 7 and 18 10V Range Bit 7 7 and 18 Scaling Network
Current 6.3kΩ Current 5kΩ
Bit 8 8 Switches 17 Bipolar Offset Bit 8 8 Switches 17 Bipolar Offset
6.3kΩ
Bit 9 9 16 Ref Input Bit 9 9 16 Ref Input

Bit 10 10 15 VOUT Bit 10 10 15 IOUT

Bit 11 11 14 –VCC Bit 11 11 14 –VCC

(LSB) Bit 12 12 13 NC(1) (LSB) Bit 12 12 13 NC(1)

NOTE: (1) Logic supply applied to this pin has no effect.

ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION

+VCC to Common ...................................................................... 0V to +18V PACKAGE DRAWING
–VCC to Common ......................................................................... 0V to –18 MODEL PACKAGE NUMBER(1)
Digital Data Inputs to Common .............................................. –1V to +18V
DAC80P 24-Pin Plastic DIP 167
Reference Output to Common ............................................................ ±VCC
DAC80 24-Pin Ceramic DIP 125
Reference Input to Common ............................................................... ±VCC
Bipolar Offset to Common ................................................................... ±VCC
NOTE: (1) For detailed drawing and dimension table, please see end of data
10V Range R to Common ................................................................... ±VCC
sheet, or Appendix D of Burr-Brown IC Data Book.
20V Range R to Common ................................................................... ±VCC
External Voltage to DAC Output .............................................. –5V to +5V
Lead Temperature (soldering, 10s) ................................................ +300°C
Max Junction Temperature .............................................................. 165°C
BURN-IN SCREENING
Thermal Resistance, θJA: Plastic DIP ........................................... 100°C/W Burn-in screening is an option available for the models
Ceramic DIP ......................................... 65°C/W
indicated in the Ordering Information table. Burn-in dura-
Stresses above those listed under “Absolute Maximum Ratings” may
tion is 160 hours at the maximum specified grade operating
cause permanent damage to the device. Exposure to absolute maxi-
mum conditions for extended periods may affect device reliability. temperature (or equivalent combination of time and tem-
perature).
All units are tested after burn-in to ensure that grade speci-
fications are met. To order burn-in, add “–BI” to the base
model number.

ORDERING INFORMATION
MODEL PACKAGE OUTPUT
DAC80-CBI-I Ceramic DIP Current
DAC80Z-CBI-I Ceramic DIP Current
DAC80-CBI-V Ceramic DIP Voltage
DAC80Z-CBI-V Ceramic DIP Voltage
DAC80P-CBI-V Plastic DIP Voltage

BURN-IN SCREENING OPTION

BURN-IN TEMP.
MODEL PACKAGE (160h)(1)
DAC80-CBI-V-BI Ceramic DIP +125°C
DAC80P-CBI-V-BI Plastic DIP +125°C

NOTE: (1) Or equivalent combination. See text.

3 DAC80/80P
DICE INFORMATION

PAD FUNCTION PAD FUNCTION

1 Bit 1 (MSB) 15 –VCC
2 Bit 2 16 VOUT
3 Bit 3 17 Ref In
4 Bit 4 18 Bipolar Offset
5 Bit 5 19 Scale 10V FSR
6 Bit 6 20 Scale 20V FSR
7 Bit 7 21 NC
8 Bit 8 22 Sum Junct
9 Bit 9 23 COM
10 Bit 10 24 COM
11 Bit 11 25 +VCC
12 Bit 12 (LSB) 26 Gain Adjust
13 NC 27 6.3V Ref Out
14 NC

Substrate Bias: Isolated. NC: No Connection

MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 118 x 121 ± 5 3.0 x 3.07 ± 0.13
Die Thickness 20 ± 3 0.51 ± 0.08
Min. Pad Size 4x4 0.10 x 0.10
DAC80KD-V DIE TOPOGRAPHY
Metalization Aluminum

PAD FUNCTION PAD FUNCTION

1 Bit 1 (MSB) 15 –VCC
2 Bit 2 16 IOUT
3 Bit 3 17 Ref In
4 Bit 4 18 Bipolar Offset
5 Bit 5 19 Scale 10V FSR
6 Bit 6 20 Scale 20V FSR
7 Bit 7 21 Scale
8 Bit 8 22 NC
9 Bit 9 23 COM
10 Bit 10 24 COM
11 Bit 11 25 +VCC
12 Bit 12 (LSB) 26 Gain Adjust
13 NC 27 6.3V Ref Out
14 NC

Substrate Bias: Isolated. NC: No Connection

MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 118 x 121 ± 5 3.0 x 3.07 ± 0.13
Die Thickness 20 ± 3 0.51 ± 0.08
DAC80KD-I DIE TOPOGRAPHY Min. Pad Size 4x4 0.10 x 0.10
Metalization Aluminum

DAC80/80P 4
DISCUSSION OF SETTLING TIME
Settling time for each DAC80 model is the total time
SPECIFICATIONS (including slew time) required for the output to settle within
DIGITAL INPUT CODES an error band around its final value after a change in input
The DAC80 accepts complementary binary digital input (see Figure 1).
codes. The CBI model may be connected by the user for any
one of three complementary codes: CSB, COB, or CTC (see
1
Table I). V Models
10kΩ

Percent of Full-Scale Range (%)

0.3 Feedback
DIGITAL INPUT ANALOG OUTPUT I Models
5kΩ
0.1
CSB COB CTC(1) Feedback

Accuracy
Complementary Complementary Complementary
Straight Offset Two’s 0.03
MSB LSB Binary Binary Complement RL=
↓ ↓ 0.01 10Ω
to 100Ω
000000000000 +Full Scale +Full Scale –1LSB
RL=
011111111111 +1/2 Full Scale Zero –Full Scale 0.003
1000Ω
100000000000 1/2 Full Scale –1LSB –1LSB –Full Scale
to 1875Ω
111111111111 Zero –Full Scale Zero 0.001
0.1 1 10 100
NOTE: (1) Invert the MSB of the COB code with an external inverter to obtain
Settling Time (µs)
CTC code.

TABLE I. Digital Input Codes. FIGURE 1. Full Scale Range Settling Time vs Accuracy.

ACCURACY Voltage Output Models

Linearity of a D/A converter is the true measure of its Three settling times are specified to ±0.01% of full scale
performance. The linearity error of the DAC80 is specified range (FSR); two for maximum full scale range changes of
over its entire temperature range. This means that the analog 20V, 10V and one for a 1LSB change. The 1LSB change is
output will not vary by more than ±1/2LSB, maximum, from measured at the major carry (0111...11 to 1000...00), the
an ideal straight line drawn between the end points (inputs point at which the worst case settling time occurs.
all “1”s and all “0”s) over the specified temperature range of
0°C to +70°C. Current Output Models
Differential linearity error of a D/A converter is the devia- Two settling times are specified to ±0.01% of FSR. Each is
tion from an ideal 1LSB voltage change from one adjacent given for current models connected with two different resis-
output state to the next. A differential linearity error speci- tive loads: 10Ω to 100Ω and 1000Ω to 1875Ω. Internal
fication of ±1/2LSB means that the output voltage step sizes resistors are provided for connecting nominal load resis-
can range from 1/2LSB to 3/2LSB when the input changes tances of approximately 1000Ω to 1800Ω for output voltage
from one adjacent input state to the next. range of ±1V and 0 to –2V (see Figures 11 and 12).
Monotonicity over a 0°C to +70°C range is guaranteed in the
DAC80 to insure that the analog output will increase or COMPLIANCE
remain the same for increasing input digital codes. Compliance voltage is the maximum voltage swing allowed
on the current output node in order to maintain specified
DRIFT accuracy. The maximum compliance voltage of all current
output models is ±2.5V. Maximum safe voltage range of
Gain Drift is a measure of the change in the full scale range
±1V and 0 to –2V (see Figures 11 and 12).
output over temperature expressed in parts per million per
°C (ppm/°C). Gain drift is established by: 1) testing the end
point differences for each DAC80 model at 0°C, +25°C, and POWER SUPPLY SENSITIVITY
+70°C; 2) calculating the gain error with respect to the 25°C Power supply sensitivity is a measure of the effect of a
value, and; 3) dividing by the temperature change. This power supply change on the D/A converter output. It is
figure is expressed in ppm/°C and is given in the electrical defined as a percent of FSR per percent of change in either
specifications both with and without internal reference. the positive or negative supplies about the nominal power
Offset Drift is a measure of the actual change in output with supply voltages (see Figure 2).
all “1”s on the input over the specified temperature range.
The offset is measured at 0°C, +25°C, and 70°C. The REFERENCE SUPPLY
maximum change in Offset is referenced to the Offset at All DAC80 models are supplied with an internal 6.3V
25°C and is divided by the temperature range. This drift is reference voltage supply. This voltage (pin 24) has a toler-
expressed in parts per million of full scale range per °C (ppm ance of ±1% and must be connected to the Reference Input
of FSR/°C).
®

5 DAC80/80P
 % of FSR Error per % of Change in VCC
0.1 OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
–VCC Connect power supply voltages as shown in Figure 3. For
0.01
optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown. These
capacitors (1µF tantalum) should be located close to the
+VCC
0.001 DAC80.

±12V OPERATION
0.0001 All DAC80 models can operate over the entire power supply
1 10 100 1k 10k 100k range of ±11.4V to ±16.5V. Even with supply levels drop-
Power Supply Ripple Frequency (Hz) ping to ±11.4V, the DAC80 can swing a full ±10V range,
provided the load current is limited to ±2.5mA. With power
FIGURE 2. Power Supply Rejection vs Power Supply Ripple.
supplies greater than ±12V, the DAC80 output can be loaded
up to ±5mA. For output swing of ±5V or less, the output
(pin 16) for specified operation. This reference may be used current is ±5mA, minimum, over the entire VCC range.
externally also, but external current drain is limited to
No bleed resistor is needed from +VCC to pin 24, as was
2.5mA.
needed with prior hybrid Z versions of DAC80. Existing
If a varying load is to be driven, an external buffer amplifier ±12V applications that are being converted to the monolithic
is recommended to drive the load in order to isolate bipolar DAC80 must omit the resistor to pin 24 to insure proper
offset from load variations. Gain and bipolar offset adjust- operation.
ments should be made under constant load conditions.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
LOGIC INPUT COMPATIBILITY
Offset and gain may be trimmed by installing external Offset
DAC80 digital inputs are TTL, LSTTL and 4000B, and Gain potentiometers. Connect these potentiometers as
54/74HC CMOS compatible. The input switching threshold shown in Figure 3 and adjust as described below. TCR of the
remains at the TTL threshold over the entire supply range. potentiometers should be 100ppm/°C or less. The 3.9MΩ
Logic “0” input current over temperature is low enough to and 10MΩ resistors (20% carbon or better) should be lo-
permit driving DAC80 directly from outputs of 4000B and cated close to the DAC80 to prevent noise pickup. If it is not
54/74C CMOS devices. convenient to use these high value resistors, an equivalent
“T” network, as shown in Figure 4, may be substituted.

Voltage Output Models Current Output Models

+VCC +VCC
1 24 1 24
Reference 10MΩ 10kΩ Reference 10MΩ 10kΩ
2 Control 23 to 2 Control 23 to
Circuit 100kΩ Circuit 100kΩ
3 22 0.01µF 3 22 0.01µF
–VCC –VCC
4 21 4 21
3.9MΩ 10kΩ 10kΩ
12-Bit 12-Bit
5 20 to 5 20 to
Resistor 5kΩ Resistor 2kΩ
Ladder 100kΩ Ladder 100kΩ
6 19 6 3kΩ 19
Network 5kΩ Network
7 and 18 7 and 18
Current 6.3kΩ +VCC Current 5kΩ +VCC
1µF 1µF
8 Switches 17 8 Switches 17
6.3kΩ
9 16 9 16 3.9MΩ

10 15 10 15
–VCC –VCC
11 14 11 14
1µF 1µF
12 13 12 13

FIGURE 3. Power Supply and External Adjustment Connection Diagrams.

DAC80/80P 6
 Offset Adjustment
10MΩ 270kΩ 270kΩ For unipolar (CSB) configurations, apply the digital input
code that should produce zero potential output and adjust the
7.8kΩ to 10kΩ Offset potentiometer for zero output.
For bipolar (COB, CTC) configurations, apply the digital
3.9MΩ 180kΩ 180kΩ input code that should produce the maximum negative
output. Example: If the Full Scale Range is connected for
10kΩ 20V, the maximum negative output voltage is –10V. See
Table II for corresponding codes.

FIGURE 4. Equivalent Resistances. Gain Adjustment

For either unipolar or bipolar configurations, apply the
Existing applications that are converting to the monolithic digital input that should give the maximum positive output.
DAC80 must change the gain trim resistor on pin 23 from Adjust the Gain potentiometer for this positive full scale
33MΩ to 10MΩ to insure sufficient adjustment range. Pin output. See Table II for positive full scale voltages and
23 is a high impedance point and a 0.001µ1F to 0.01µF currents.
ceramic capacitor should be connected from this pin to
Common (pin 21) to prevent noise pickup. Refer to Figure ANALOG OUTPUT
5 for relationship of Offset and Gain adjustments to unipolar DIGITAL INPUT VOLTAGE(1) CURRENT
and bipolar D/A operation. MSB LSB 0 to +10V ±10V 0 to –2mA ±1mA
↓ ↓
000000000000 +9.9976V +9.9951V –1.9995mA –0.9995mA
Unipolar 011111111111 +5.0000V 0.0000V –1.0000mA 0.0000mA
100000000000 +4.9976V –0.0049V –0.9995mA +0.0005mA
111111111111 0.0000V –10.0000V 0.0000mA +1.000mA
Range of One LSB 2.44mV 4.88mV 0.488µA 0.488µA
+ Full Scale
Gain Adjust
NOTE: (1) To obtain values for other binary ranges:
1LSB 0 to +5V range divide 0 to +10V range values by 2.
±5V range: divide ±10V range values by 2.
±2.5V range: divide ±10V range values by 4.
Full Scale Range
Analog Output

Gain Adjust TABLE II. Digital Input/Analog Output.

Rotates the Line
VOLTAGE OUTPUT MODELS
Output Range Connections
All Bits
Range
Logic 1
Internal scaling resistors provided in the DAC80 may be
of Offset All Bits connected to produce bipolar output voltage ranges of ±10V,
Adjust Logic 0 ±5V, or ±2.5V; or unipolar output voltage ranges of 0 to
+5V or 0 to +10V. See Figure 6.
Digital Input
Offset Adjust Translates the Line To Reference Control Circuit
Reference Input 6.3kΩ(1)
Bipolar Bipolar
16 17
+ Full Scale Offset
Range of Summing 21 Common
Gain Adjust Junction

1LSB From Weighted 20 5kΩ(1) 18 5kΩ(1)

Resistor 19
All Bits Full Scale
Network
Analog Output

Logic 1 Range Gain Adjust

Rotates the Line
15 Output

All Bits NOTE: (1) Resistor Tolerances: ±2% max.

Bipolar MSB On, Logic 0
Offset All Others
Range of FIGURE 6. Output Amplifier Voltage Range Scaling Circuit.
Off
Offset Adjust
–Full Scale
Gain and offset drift are minimized because of the thermal
tracking of the scaling resistors with other internal device
Digital Input components. Connections for various output voltage ranges
Offset Adjust Translates the Line are shown in Table III. Settling time for a full-scale range
FIGURE 5. Relationship of Offset and Gain Adjustments for change is specified as 4µs for the 20V range and 3µs for the
a Unipolar and Bipolar D/A Converter. 10V range.
®

7 DAC80/80P
 Output Digital Connect Connect Connect Connect
Range Input Codes Pin 15 to Pin 17 to Pin 19 to Pin 16 to 19 20V Range

±10 COB or CTC 19 20 15 24 5kΩ 18

±5 COB or CTC 18 20 NC 24 10V Range
±2.5V COB or CTC 18 20 20 24
0 to +10V CSB 18 21 NC 24 5kΩ
15 A
0 to +5V CSB 18 21 20 24
OPA604(1)
IOUT
TABLE III. Output Voltage Range Connections for Voltage 0 to 6.6kΩ VOUT
Models. 2mA

CURRENT OUTPUT MODELS 21

NOTE: (1) For fast settling.
The resistive scaling network and equivalent output circuit
of the current model differ from the voltage model and are FIGURE 9. External Op-Amp—Using Internal Feedback
shown in Figures 7 and 8. Resistors.

To Reference Control Circuit the current output model DAC80 provides output voltage
ranges the same as the voltage model DAC80. To obtain the
Reference Input 6.3kΩ(1) desired output voltage range when connecting an external op
16 17
amp, refer to Table IV.
3kΩ(1) 2kΩ(1)
18 19
Output Digital Connect Connect Connect Connect
5kΩ(1) Range Input Codes A to Pin 17 to Pin 19 to Pin 16 to
±10V COB or CTC 19 15 A 24
15 20
±5V COB or CTC 18 15 NC 24
NOTE: (1) Resistor Tolerances: ±2% max. ±2.5V COB or CTC 18 15 15 24
0 to +10V CSB 18 21 NC 24
0 to +5V CSB 18 21 15 24
FIGURE 7. Internal Scaling Resistors.
TABLE IV. Voltage Range of Current Output.

24 Reference Out Output Larger Than 20V Range

To
Reference
17 Bipolar Offset For output voltage ranges larger than ±10V, a high voltage
Control 6.3kΩ op amp may be employed with an external feedback resistor.
+
Circuit
16 Reference Input Use IOUT value of ±1mA for bipolar voltage ranges and
6.3V 15 IOUT –2mA for unipolar voltage ranges. See Figure 10. Use
– protection diodes when a high voltage op amp is used.
0 to RO
I The feedback resistor, RF, should have a temperature coef-
2mA 6.6kΩ
ficient as low as possible. Using an external feedback
21 Common
resistor, overall drift of the circuit increases due to the lack
of temperature tracking between RF and the internal scaling
FIGURE 8. Current Output Model Equivalent Output Circuit. resistor network. This will typically add 50ppm/°C plus RF
drift to total drift.
Internal scaling resistors (Figure 7) are provided to scale an
external op amp or to configure load resistors for a voltage
output. These connections are described in the following
24
sections. RF
17
+
If the internal resistors are not used for voltage scaling,
6.3kΩ 6.3kΩ
external RL (or RF ) resistors should have a TCR of – 16
±25ppm/°C or less to minimize drift. This will typically add
±50ppm/°C plus the TCR of RL (or RF) to the total drift. 15 BB3582J(1)
I
0 to 6.6kΩ
VOUT
Driving An External Op Amp 2mA
The current output model DAC80 will drive the summing 21
junction of an op amp used as a current-to-voltage converter
NOTE: (1) For output voltage swings up to 290V p-p.
to produce an output voltage. See Figure 9.
VOUT = IOUT x RF
FIGURE 10. External Op-Amp—Using External Feedback
where IOUT is the DAC80 output current and RF is the Resistors.
feedback resistor. Using the internal feedback resistors of
®

DAC80/80P 8
Driving a Resistive Load Unipolar Driving a Resistive Load Bipolar
A load resistance, RL = RLI + RLS, connected as shown in The equivalent output circuit for a bipolar output voltage
Figure 11 will generate a voltage range, VOUT, determined range is shown in Figure 12, RL = RLI + RLS. VOUT is
by: determined by:
VOUT = –2mA [(RL x RO) ÷ (RL + RO)] VOUT = ±1mA [(RO x RL) ÷ (RO + RL)]

By connecting pin 17 to 15, the output current becomes

bipolar (±1mA) and the output impedance RO becomes
3.2kΩ (6.6kΩ in parallel with 6.3kΩ). RLI is 1200Ω (derived
by connecting pin 15 to 18 and pin 18 to 19). By choosing
Current Controlled
by Digital Input
RLS = 225Ω, RL = 1455Ω. RL in parallel with RO yields 1kΩ
15
+ total load. This gives an output range of ±1V. As indicated
RLI
18 above, trimming may be necessary.
0 to VOUT
RO
–2mA
RLS
–
21 Common

FIGURE 11. Current Output Model Equivalent Circuit Current Controlled

Connected for Unipolar Voltage Output with by Digital Input 15
+
Resistive Load. RLI
20
VOUT
+1mA RO
The unipolar output impedance RO equals 6.6kΩ (typ) and RLS
RLI is the internal load resistance of 968Ω (derived by
–
connecting pin 15 to 20 and pin 18 to 19). By choosing RLS 21 Common
= 210Ω, RL = 1178Ω. RL in parallel with RO yields 1kΩ total
load. This gives an output range of 0 to –2V. Since RO is not FIGURE 12. Current Output Model Connected for Bipolar
exact, initial trimming per Figure 3 may be necessary; also Output Voltage with Resistive Load.
RLS may be trimmed.

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no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

9 DAC80/80P
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