Ads 7816
Ads 7816
Ads 7816
AD ADS7816
OPSA7816
ADS
781
6
658
FEATURES DESCRIPTION
● 200kHz SAMPLING RATE The ADS7816 is a 12-bit, 200kHz sampling analog-
● MICRO POWER: to-digital converter. It features low power operation
1.9mW at 200kHz with automatic power down, a synchronous serial
150µW at 12.5kHz interface, and a differential input. The reference volt-
age can be varied from 100mV to 5V, with a corre-
● POWER DOWN: 3µA Max
sponding resolution from 24µV to 1.22mV.
● 8-PIN MINI-DIP, SOIC, AND MSOP
Low power, automatic power down, and small size
● DIFFERENTIAL INPUT make the ADS7816 ideal for battery operated systems
● SERIAL INTERFACE or for systems where a large number of signals must be
acquired simultaneously. It is also ideal for remote
APPLICATIONS and/or isolated data acquisition. The ADS7816 is
available in an 8-pin plastic mini-DIP, an 8-lead SOIC,
● BATTERY OPERATED SYSTEMS
or an 8-lead MSOP package.
● REMOTE DATA ACQUISITION
● ISOLATED DATA ACQUISITION
SAR Control
VREF
DOUT
+In
CDAC Serial
–In Interface DCLOCK
CS/SHDN
S/H Amp Comparator
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1996 Burr-Brown Corporation PDS-1355B Printed in U.S.A., March, 1997
SBAS061
SPECIFICATIONS
At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ANALOG INPUT
Full-Scale Input Span +In – (–In) 0 VREF ✻ ✻ ✻ ✻ V
Absolute Input Voltage +In –0.2 VCC +0.2 ✻ ✻ ✻ ✻ V
–In –0.2 +0.2 ✻ ✻ ✻ ✻ V
Capacitance 25 ✻ ✻ pF
Leakage Current ±1 ✻ ✻ µA
SYSTEM PERFORMANCE
Resolution 12 ✻ ✻ Bits
No Missing Codes 11 12 ✻ Bits
Integral Linearity Error ±0.5 ±2 ±0.5 ±2 ±0.5 ±1 LSB(1)
Differential Linearity Error ±0.5 ±2 ±0.5 ±1 ±0.25 ±0.75 LSB
Offset Error ±4 ✻ ✻ LSB
Gain Error ±4 ✻ ✻ LSB
Noise 33 ✻ ✻ µVrms
Power Supply Rejection 82 ✻ ✻ dB
SAMPLING DYNAMICS
Conversion Time 12 ✻ ✻ Clk Cycles
Acquisition Time 1.5 ✻ ✻ Clk Cycles
Throughput Rate 200 ✻ ✻ kHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –84 ✻ ✻ dB
VIN = 5.0Vp-p at 5kHz –82 ✻ ✻ dB
SINAD VIN = 5.0Vp-p at 1kHz 72 ✻ ✻ dB
Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 86 ✻ ✻ dB
REFERENCE INPUT
Voltage Range 0.1 5 ✻ ✻ ✻ ✻ V
Resistance CS = GND, fSAMPLE = 0Hz 5 ✻ ✻ GΩ
CS = VCC 5 ✻ ✻ GΩ
Current Drain At Code 710h 38 100 ✻ ✻ ✻ ✻ µA
fSAMPLE = 12.5kHz 2.4 20 ✻ ✻ ✻ ✻ µA
CS = VCC 0.001 3 ✻ ✻ ✻ ✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻ ✻
Logic Levels:
VIH IIH = +5µA 3 +VCC +0.3 ✻ ✻ ✻ ✻ V
VIL IIL = +5µA –0.3 0.8 ✻ ✻ ✻ ✻ V
VOH IOH = –250µA 3.5 ✻ ✻ V
VOL IOL = 250µA 0.4 ✻ ✻ V
Data Format Straight Binary ✻ ✻
POWER SUPPLY REQUIREMENTS
VCC Specified Performance 4.50 5.25 ✻ ✻ ✻ ✻ V
Quiescent Current 380 700 ✻ ✻ ✻ ✻ µA
fSAMPLE = 12.5kHz(2, 3) 30 ✻ ✻ µA
fSAMPLE = 12.5kHz(3) 280 400 ✻ ✻ µA
Power Down CS = VCC, fSAMPLE = 0Hz 3 ✻ ✻ µA
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ ✻ ✻ °C
ADS7816 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
+VCC ..................................................................................................... +6V
Analog Input ........................................................... –0.3V to (+VCC + 0.3V) DISCHARGE SENSITIVITY
Logic Input ............................................................. –0.3V to (+VCC + 0.3V)
Case Temperature ......................................................................... +100°C Electrostatic discharge can cause damage ranging from per-
Junction Temperature .................................................................... +150°C formance degradation to complete device failure. Burr-
Storage Temperature ..................................................................... +125°C Brown Corporation recommends that all integrated circuits
External Reference Voltage .............................................................. +5.5V
be handled and stored using appropriate ESD protection
NOTE: (1) Stresses above these ratings may permanently damage the device. methods.
ESD damage can range from subtle performance degrada-
PIN CONFIGURATION
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
VREF 1 8 +VCC parametric changes could cause the device not to meet
published specifications.
+In 2 7 DCLOCK
ADS7816
–In 3 6 DOUT
GND 4 5 CS/SHDN
8-Pin PDIP,
8-Lead SOIC,
8-Lead MSOP
PIN ASSIGNMENTS
PIN NAME DESCRIPTION
1 VREF Reference Input.
2 +In Non Inverting Input.
3 –In Inverting Input. Connect to ground or to remote ground sense point.
4 GND Ground.
5 CS/SHDN Chip Select when LOW, Shutdown Mode when HIGH.
6 DOUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.
8 +VCC Power Supply.
PACKAGE/ORDERING INFORMATION
MAXIMUM MAXIMUM
INTEGRAL DIFFERENTIAL PACKAGE
LINEARITY ERROR LINEARITY ERROR TEMPERATURE DRAWING
PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER(1)
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3 ADS7816
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
3.5
0.1
Delta from 25°C (LSB)
3
Change in Gain (LSB)
0.05
2.5
2 0
1.5
–0.05
1
–0.1
0.5
0 –0.15
1 2 3 4 5 –55 –40 –25 0 25 70 85
Reference Voltage (V) Temperature (°C)
11.75 9
Effective Number of Bits (rms)
8
11.5
7
11.25 6
11 5
10.75 4
3
10.5
2
10.25
1
10 0
0.1 1 10 0.1 1 10
Reference Voltage (V) Reference Voltage (V)
ADS7816 4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
FREQUENCY SPECTRUM
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY (2048 Point FFT; fIN = 9.9kHz, –0.5dB)
0 0
–10
–10
–20
Power Supply Rejection (dB)
–20 –30
–30 –40
Amplitude (dB)
–50
–40
–60
–50 –70
–60 –80
–90
–70
–100
–80 –110
–90 –120
1 10 100 1000 10000 0 25 50 75 100
Ripple Frequency (kHz) Frequency (kHz)
100 80
90
Signal-to-(Noise + Distortion) (dB)
70
80
60
70
60 50
50 40
40 30
30
20
20
10 10
0 0
1 10 100 –40 –35 –30 –25 –20 –15 –10 –5 0
Frequency (kHz) Input Level (dB)
5 ADS7816
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
0.75 0.75
0.50 0.50
0.25 0.25
0.00 0.00
–0.25 –0.25
–0.50 –0.50
–0.75 –0.75
–1.00 –1.00
0 2048 4095 0 2048 4095
Code Code
0.05
Leakage Current (nA)
Change in Differential
0.00 1
Linearity (LSB)
–0.05
–0.10 0.1
Change in Integral
–0.15 Linearity (LSB)
–0.20 0.01
1 2 3 4 5 –55 –40 –25 0 25 70 85
Reference Voltage (V) Temperature (°C)
350 2
300 1.5
fSAMPLE = 12.5kHz
250 1
200 0.5
150 0
–55 –40 –25 0 25 70 85 –55 –40 –25 0 25 70 85
Temperature (°C) Temperature (°C)
ADS7816 6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
35
50
30
45
25
40
20
15 35
10
30
5
25
0 –55 –40 –25 0 25 70 85
0 40 80 120 160 200
Temperature (°C)
Sample Rate (kHz)
0.5
0 Change in Differential
Linearity (LSB)
–0.5
0 100 200 300 400 500
Sample Rate (kHz)
7 ADS7816
THEORY OF OPERATION to a 12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
The ADS7816 is a classic successive approximation register down mode, the input impedance is greater than 1GΩ.
(SAR) analog-to-digital (A/D) converter. The architecture is
Care must be taken regarding the absolute analog input
based on capacitive redistribution which inherently includes
voltage. To maintain the linearity of the converter, the –In
a sample/hold function. The converter is fabricated on a 0.6µ
input should not exceed GND ±200mV. The +In input
CMOS process. The architecture and process allow the
should always remain within the range of GND –200mV to
ADS7816 to acquire and convert an analog signal at up to
VCC +200mV. Outside of these ranges, the converter’s lin-
200,000 conversions per second while consuming very little
earity may not meet specifications.
power.
The ADS7816 requires an external reference, an external
clock, and a single +5V power source. The external refer- REFERENCE INPUT
ence can be any voltage between 100mV and VCC. The value
of the reference voltage directly sets the range of the analog The external reference sets the analog input range. The
input. The reference input current depends on the conversion ADS7816 will operate with a reference in the range of 100mV
rate of the ADS7816. to VCC. There are several important implications of this.
The external clock can vary between 10kHz (625Hz through- As the reference voltage is reduced, the analog voltage
put) and 3.2MHz (200kHz throughput). The duty cycle of weight of each digital output code is reduced. This is often
the clock is essentially unimportant as long as the minimum referred to as the LSB (least significant bit) size and is equal
high and low times are at least 150ns. The minimum clock to the reference voltage divided by 4096. This means that
frequency is set by the leakage on the capacitors internal to any offset or gain error inherent in the A/D converter will
the ADS7816. appear to increase, in terms of LSB size, as the reference
voltage is reduced. The typical performance curves of
The analog input is provided to two input pins: +In and –In. “Change in Offset vs Reference Voltage” and “Change in
When a conversion is initiated, the differential input on these Gain vs Reference Voltage” provide more information.
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from The noise inherent in the converter will also appear to
any internal function. increase with lower LSB size. With a 5V reference, the
internal noise of the converter typically contributes only
The digital result of the conversion is clocked out by the 0.16 LSB peak-to-peak of potential error to the output code.
DCLOCK input and is provided serially, most significant bit When the external reference is 100mV, the potential error
first, on the DOUT pin. The digital data that is provided on the contribution from the internal noise will be 50 times larger—
DOUT pin is for the conversion currently in progress—there 8 LSBs. The errors due to the internal noise are gaussian in
is no pipeline delay. It is possible to continue to clock the nature and can be reduced by averaging consecutive conver-
ADS7816 after the conversion is complete and to obtain the sion results.
serial data least significant bit first. See the Digital Interface
section for more information. For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
ANALOG INPUT The effective number of bits (ENOB) figure is calculated
based on the converter’s signal-to-(noise + distortion) ratio
The +In and –In input pins allow for a differential input signal. with a 1kHz, 0dB input signal. SINAD is related to ENOB
Unlike some converters of this type, the –In input is not re- as follows: SINAD = 6.02 • ENOB +1.76.
sampled later in the conversion cycle. When the converter
With lower reference voltages, extra care should be taken to
goes into the hold mode, the voltage difference between +In
provide a clean layout including adequate bypassing, a clean
and –In is captured on the internal capacitor array.
power supply, a low-noise reference, and a low-noise input
The range of the –In input is limited to ±200mV. Because of signal. Because the LSB size is lower, the converter will also
this, the differential input can be used to reject only small be more sensitive to external sources of error such as nearby
signals that are common to both inputs. Thus, the –In input digital signals and electromagnetic interference.
is best used to sense a remote signal ground that may move
The current that must be provided by the external reference
slightly with respect to the local ground potential.
will depend on the conversion result. The current is lowest
The input current on the analog inputs depends on a number at full-scale (FFFh) and is typically 25µA at a 200kHz
of factors: sample rate, input voltage, source impedance, and conversion rate (25°C). For the same conditions, the current
power down mode. Essentially, the current into the ADS7816 will increase as the input approaches zero, reaching 50µA at
charges the internal capacitor array during the sample pe- an output result of 000h. The current does not increase
riod. After this capacitance has been fully charged, there is linearly, but depends, to some degree, on the bit pattern of
no further input current. The source of the analog input the digital output.
voltage must be able to charge the input capacitance (25pF)
ADS7816 8
The reference current diminishes directly with both conver- value for one clock period. For the next 12 DCLOCK
sion rate and reference voltage. As the current from the periods, DOUT will output the conversion result, most sig-
reference is drawn on each bit decision, clocking the con- nificant bit first. After the least significant bit (B0) has been
verter more quickly during a given conversion period will output, subsequent clocks will repeat the output data but in
not reduce the overall current drain from the reference. The a least significant bit first format.
reference current changes only slightly with temperature. After the most significant bit (B11) has been repeated, DOUT
See the curves, “Reference Current vs Sample Rate” and will tri-state. Subsequent clocks will have no effect on the
“Reference Current vs Temperature” in the Typical Perfor- converter. A new conversion is initiated only when CS has
mance Curves section for more information. been taken HIGH and returned LOW.
tCYC
CS/SHDN
tSUCS POWER
DOWN
DCLOCK
tCSD
NULL NULL
HI-Z BIT HI-Z BIT
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1) B11 B10 B9 B8
tSMPL (MSB)
tCONV tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
tCSD
NULL
HI-Z BIT HI-Z
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
tSMPL (MSB)
tCONV tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
9 ADS7816
1.4V
3kΩ VOH
DOUT
DOUT VOL
Test Point
tr tf
100pF
CLOAD
Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall TImes tr, and tf
Test Point
DCLOCK VIL
VCC
tdDO 3kΩ tdis Waveform 2, ten
DOUT
VOH
DOUT tdis Waveform 1
100pF
VOL CLOAD
thDO
Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden
DOUT
90% DCLOCK 1 2
Waveform 1(1)
tdis
DOUT VOL
10% DOUT B11
Waveform 2(2)
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that Voltage Waveforms for ten
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
ADS7816 10
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses 1000
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
SHORT CYCLING
1
Another way of saving power is to utilize the CS signal to 1 10 100 1000
short cycle the conversion. Because the ADS7816 places the Sample Rate (kHz)
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that FIGURE 4. Scaling fCLK Reduces Supply Current Only
the conversion can be terminated at any time. For example, Slightly with Sample Rate.
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
60
This technique can be used to lower the power dissipation TA = 25°C
(or to increase the conversion rate) in those applications 50 VCC = VREF = +5V
fCLK = 16 • fSAMPLE
where an analog signal is being monitored until some con-
Supply Current (µA)
CS LOW
dition becomes true. For example, if the signal is outside a 40 (GND)
predetermined range, the full 12-bit conversion result may
30
not be needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4. This 20
results in lower power dissipation in both the converter and
the rest of the system, as they spend more time in the power 10 CS = HIGH (VCC)
down mode.
0
1 10 100 1000
For optimum performance, care should be taken with the FIGURE 5. Shutdown Current is Considerably Lower with
physical layout of the ADS7816 circuitry. This is particularly CS HIGH than when CS is LOW.
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7816 makes a bit
decision every 312ns. That is, for each subsequent bit deci-
11 ADS7816
sion, the digital output must be updated with the results of the described in the previous paragraph, voltage variation due to
last bit decision, the capacitor array appropriately switched the line frequency (50Hz or 60Hz), can be difficult to
and charged, and the input to the comparator settled to a remove.
12-bit level all within one clock cycle. The GND pin on the ADS7816 should be placed on a clean
The basic SAR architecture is sensitive to spikes on the ground point. In many cases, this will be the “analog”
power supply, reference, and ground connections that occur ground. Avoid connecting the GND pin too close to the
just prior to latching the comparator output. Thus, during grounding point for a microprocessor, microcontroller, or
any single conversion for an n-bit SAR converter, there are digital signal processor. If needed, run a ground trace di-
n “windows” in which large external transient voltages can rectly from the converter to the power supply connection
easily affect the conversion result. Such spikes might origi- point. The ideal layout will include an analog ground plane
nate from switching power supplies, digital logic, and high for the converter and associated analog circuitry.
power devices, to name a few. This particular source of error The –In input pin should be connected directly to ground. In
can be very difficult to track down if the glitch is almost those cases where the ADS7816 is a large distance from the
synchronous to the converter’s DCLOCK signal—as the signal source and/or the circuit environment contains large
phase difference between the two changes with time and EMI or RFI sources, the –In input should be connected to the
temperature, causing sporadic misoperation. ground nearest the signal source. This should be done with
With this in mind, power to the ADS7816 should be clean a signal trace that is adjacent to the +In input trace. If
and well bypassed. A 0.1µF ceramic bypass capacitor should appropriate, coax cable or twisted-pair wire can be used.
be placed as close to the ADS7816 package as possible. In
addition, a 1 to 10µF capacitor and a 10Ω series resistor may
be used to lowpass filter a noisy supply. APPLICATION CIRCUITS
The reference should be similarly bypassed with a 0.1µF Figures 6, 7, and 8 show some typical application circuits for
capacitor. Again, a series resistor and large capacitor can be the ADS7816. Figure 6 uses an ADS7816 and a multiplexer
used to lowpass filter the reference voltage. If the reference to provide for a flexible data acquisition circuit. A resistor
voltage originates from an op amp, be careful that the op- string provides for various voltages at the multiplexer input.
amp can drive the bypass capacitor without oscillation (the The selected voltage is buffered and driven into VREF. As
series resistor can help in this case). Keep in mind that while shown in Figure 6, the input range of the ADS7816 is
the ADS7816 draws very little current from the reference on programmable to 100mV, 200mV, 300mV, or 400mV. The
average, there are higher instantaneous current demands 100mV range would be useful for sensors such as the
placed on the external reference circuitry. thermocouple shown.
Also, keep in mind that the ADS7816 offers no inherent Figure 7 is more complex variation of Figure 6 with in-
rejection of noise or voltage variation in regards to the creased flexibility. In this circuit, a digital signal processor
reference input. This is of particular concern when the designed for audio applications is put to use in running three
reference input is tied to the power supply. Any noise and ADS7816s and a DAC56. The DAC56 provides a variable
ripple from the supply will appear directly in the digital voltage for VREF —enabling the input range of the ADS7816s
results. While high frequency noise can be filtered out as to be programmed from 100mV to 3V.
+5V
+5V +5V
R8
46kΩ
0.4V
R7
R9
10Ω
R1 1kΩ
OPA237
D1 150kΩ C2 0.3V
R3 U2
0.1µF R10
500kΩ C1
MUX 1kΩ
R2 R6 VREF 10µF
59kΩ 1MΩ DCLOCK 0.2V
R11
C3 DOUT 1kΩ
TC1 ADS7816 A0
TC2 0.1µF
CS/SHDN 0.1V
Thermocouple A1
R12
TC3 C4 U1 1kΩ
R4 U3
10µF R5 C5
1kΩ
500Ω 0.1µF µP
ISO Thermal Block
3-Wire
Interface
U4
FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7816.
®
ADS7816 12
DSP56004
ADS7816
WST
VREF CS SDO0
+
10µF 0.1µF +In DOUT SDO1
–In DCLOCK SDO2
VREF CS SDI0
+
10µF 0.1µF +In DOUT SDI1
ADS7816 SCK/SCL
VREF CS MISO/SDA
+ Serial Host
10µF 0.1µF +In DOUT MOSI/HA0
Interface
–In DCLOCK HREQ
SS/HA2
10Ω 10Ω 10Ω DAC56
VOUT LE
CLK
DATA
+5V
5Ω to 10Ω
+ 1µF to
10µF
ADS7816
VREF VCC
+ 1µF to
0.1µF 10µF
+In CS Microcontroller
–In DOUT
GND DCLOCK
The ADS7816s and the DSP56004 can all be placed into a Figure 8 shows a basic data acquisition system. The ADS7816
power down mode. Or, the DSP56004 can run the ADS7816s input range is 0V to 5V, as the reference input is connected
at a full 3.2MHz clock rate while on-board software enables directly to the +5V supply. The 5Ω to 10Ω resistor and 1µF
the ADS7816s as needed. With additional glue logic, the to 10µF capacitor filter the microcontroller “noise” on the
DSP56004 could be used to run multiple DAC56s or provide supply, as well as any high-frequency noise from the supply
CS controls for each of the three ADS7816s. itself. The exact values should be picked such that the filter
provides adequate rejection of the noise.
13 ADS7816
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
ADS7816E/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816E/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816E/2K5G4 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816EB/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816EB/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816EB/2K5G4 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816EC/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816EC/2K5 ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 A16 Samples
ADS7816U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
ADS7816U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
ADS7816U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
ADS7816UB ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
B
ADS7816UB/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
B
ADS7816UC ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
C
ADS7816UC/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
C
ADS7816UC/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
C
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
ADS7816UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS Samples
7816U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
0.25
GAGE PLANE
1.1 MAX
0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.4) (R0.05) TYP
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
SEE DETAILS
(4.4)
4214862/A 04/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
(4.4)
4214862/A 04/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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