Application Note AN-1084: Power MOSFET Basics
Application Note AN-1084: Power MOSFET Basics
Application Note AN-1084: Power MOSFET Basics
Table of Contents
Page
Breakdown Voltage ..............................................................................5
On-resistance.......................................................................................6
Transconductance................................................................................6
Dynamic Characteristics.......................................................................8
Gate Charge.........................................................................................10
www.irf.com AN-1084 1
Power MOSFET Basics
Vrej Barkhordarian, International Rectifier, El Segundo, Ca.
However, at high breakdown voltages (>200V) the on-state voltage drop of the power MOSFET becomes
higher than that of a similar size bipolar device with similar voltage rating. This makes it more attractive
to use the bipolar power transistor at the expense of worse high frequency performance. Figure 2 shows
the present current-voltage limitations of power MOSFETs and BJTs. Over time, new materials,
structures and processing techniques are expected to raise these limits.
Source
Gate Polysilicon
Oxide Gate
Source
Metallization
n+ Substrate S
(100)
Drain
Metallization
Drain
Figure 3. Schematic Diagram for an n-Channel Power MOSFET and the Device.
Figure 3 shows schematic diagram and Figure 4 shows the physical origin of the parasitic components in
an n-channel power MOSFET. The parasitic JFET appearing between the two body implants restricts
current flow when the depletion widths of the two adjacent body diodes extend into the drift region with
increasing drain voltage. The parasitic BJT can make the device susceptible to unwanted device turn-on
and premature breakdown. The base resistance RB must be minimized through careful design of the
doping and distance under the source region. There are several parasitic capacitances associated with
the power MOSFET as shown in Figure 3.
CGS is the capacitance due to the overlap of the source and the channel regions by the polysilicon gate
and is independent of applied voltage. CGD consists of two parts, the first is the capacitance associated
with the overlap of the polysilicon gate and the silicon underneath in the JFET region. The second part is
the capacitance associated with the depletion region immediately under the gate. CGD is a nonlinear
function of voltage. Finally, CDS, the capacitance associated with the body-drift diode, varies inversely
with the square root of the drain-source bias. There are currently two designs of power MOSFETs, usually
referred to as the planar and the trench designs. The planar design has already been introduced in the
schematic of Figure 3. Two variations of the trench power MOSFET are shown Figure 5. The trench
technology has the advantage of higher cell density but is more difficult to manufacture than the planar
device.
Metal
Cgsm LTO
CGS2
CGD
n- CGS1
RCh n-
JFET
- RB
p BJT
CDS
REPI
n- Epi Layer
n- Substrate
The reach-through phenomenon occurs when the depletion region on the drift side of the body-drift p-n
junction reaches the epilayer-substrate interface before avalanching takes place in the epi. Once the
depletion edge enters the high carrier concentration substrate, a further increase in drain voltage will
cause the electric field to quickly reach the critical value of 2x105 V/cm where avalanching begins.
ON-RESISTANCE
The on-state resistance of a power MOSFET is made up of several components as shown in Figure 8:
where:
25
Rsource = Source diffusion resistance
Rch = Channel resistance 7
RA = Accumulation resistance
RJ = "JFET" component-resistance of the Gate
region between the two body regions Voltage
Linear Region
Wafers with substrate resistivities of up to
(Saturation
20mΩ-cm are used for high voltage
Region)
devices and less than 5mΩ-cm for low
15
voltage devices.
TRANSCONDUCTANCE
Transconductance, gfs, is a measure of the sensitivity of drain current to changes in gate-source bias.
This parameter is normally quoted for a Vgs that gives a drain current equal to about one half of the
maximum current rating value and for a VDS that ensures operation in the constant current region.
Transconductance is influenced by gate width, which increases in proportion to the active area as cell
density increases. Cell density has increased over the years from around half a million per square inch in
1980 to around eight million for planar MOSFETs and around 12 million for the trench technology. The
limiting factor for even higher cell densities is the photolithography process control and resolution that
allows contacts to be made to the source metallization in the center of the cells.
Channel length also affects transconductance. Reduced
channel length is beneficial to both gfs and on-resistance,
with punch-through as a tradeoff. The lower limit of this ID
length is set by the ability to control the double-diffusion
process and is around 1-2mm today. Finally the lower the
gate oxide thickness the higher gfs.
Soft
THRESHOLD VOLTAGE
Sharp
GATE
DIODE FORWARD VOLTAGE
N+
The diode forward voltage, VF, is the SOURCE
guaranteed maximum forward drop of
the body-drain diode at a specified
value of source current. Figure 10 RCH
RA
shows a typical I-V characteristics for RSOURCE P-BASE
RJ
this diode at two temperatures. P-
channel devices have a higher VF due
to the higher contact resistance
between metal and p-silicon
compared with n-type silicon.
Maximum values of 1.6V for high RD
voltage devices (>100V) and 1.0V for
low voltage devices (<100V) are
common.
Pd = T j m ax- 25 (2)
R thJC
Tjmax = Maximum allowable temperature of the p-n junction in the device (normally 1500C or 1750C) RthJC
= Junction-to-case thermal impedance of the device.
DYNAMIC CHARACTERISTICS
When the MOSFET is used as a switch, its basic function is to control the drain current by the gate
voltage. Figure 11(a) shows the transfer characteristics and Figure 11(b) is an equivalent circuit model
often used for the analysis of MOSFET switching performance.
Packaging
Rwcml
Metallization
Source
RCH Channel
JFET
Region
REPI
Expitaxial
Layer
Substrate
The switching performance of a device is determined by the time required to establish voltage changes
across capacitances. RG is the distributed resistance of the gate and is approximately inversely
proportional to active area. LS and LD are source and drain lead inductances and are around a few tens of
nH. Typical values of input (Ciss), output (Coss) and reverse transfer (Crss) capacitances given in the data
sheets are used by circuit designers as a starting point in determining circuit component values. The data
sheet capacitances are defined in terms of the equivalent circuit capacitances as:
Ciss = CGS + CGD, CDS shorted 100
Crss = CGD
ID
LD
CGD
D'
G RG
C ID Body-drain
Slope = gfs
CDS Diode
S'
CGS
LS
VGS
S
(a) (b)
Figure 11. Power MOSFET (a) Transfer characteristics, (b) Equivalent Circuit Showing Components That
Have Greatest Effect on Switching
GATE CHARGE
RD
Although input capacitance VDS
values are useful, they do not
provide accurate results when
comparing the switching D.U.T.
VGS
performances of two devices
from different manufacturers. -
Effects of device size and RG
VDD
transconductance make such +
comparisons more difficult. A
more useful parameter from the
circuit design point of view is
-10V
the gate charge rather than
Pulse Width < 1µµs
capacitance. Most Duty Factor < 0.1%
manufacturers include both
parameters on their data sheets.
(a)
Figure 13 shows a typical gate
charge waveform and the test td(on) tr td(off) tf
circuit. When the gate is
connected to the supply voltage, VGS
VGS starts to increase until it 100%
reaches Vth, at which point the
drain current starts to flow and
the CGS starts to charge. During
the period t1 to t2, CGS
continues to charge, the gate
voltage continues to rise and
drain current rises
90%
proportionally. At time t2, CGS
is completely charged and the
VDS
drain current reaches the
predetermined current ID and (b)
stays constant while the drain Figure 12. Switching Time Test (a) Circuit, (b) VGS and VDS
voltage starts to fall. With Waveforms
reference to the equivalent
circuit model of the MOSFET shown in Figure 13, it can be seen that with CGS fully charged at t2, VGS
becomes constant and the drive current starts to charge the Miller capacitance, CDG. This continues
until time t3.
Charge time for the Miller capacitance is
VDD
larger than that for the gate to source
capacitance CGS due to the rapidly changing
drain voltage between t2 and t3 (current = C
dv/dt). Once both of the capacitances CGS ID D
dv
VGS = I1 R G = R G C GD (3)
dt
When the gate voltage VGS exceeds the threshold voltage of the device Vth, the device is forced into
conduction. The dv/dt capability for this mechanism is thus set by:
dv V
= th
dt R G C GD (4)
dv VBE
= (5)
dt R BC DB
SOURCE
GATE
"HEXFET Power MOSFET Designer's Manual - Application Notes and Reliability Data," International
Rectifier
"Modern Power Devices," B. Jayant Baliga
"Physics of Semiconductor Devices," S. M. Sze
"Power FETs and Their Applications," Edwin S. Oxner
"Power MOSFETs - Theory and Applications," Duncan A. Grant and John Gower