International Journal of Electrical, Electronics and Data Communication, ISSN(p): 2320-2084, ISSN(e): 2321-2950

Volume-6, Issue-6, Jun.-2018, http://iraj.in

DESIGN OF CMOS MULTISTAGE HIGH GAIN DIFFERENTIAL
AMPLIFIER USING CADENCE
1
SHIVANI M ADERAO, 2SUSHMAKEJGIR
1
PG Student, 2Associate Professor, Electronics Engineering, Shri Guru Gobind Singhji Institute of Engineering and
Technology
E-mail: 2016mec012@sggs.ac.in

Abstract - In this paper behavior of multiple energy storage elements of Op-amp is observed. Initially a two stage Op-amp
is designed using CMOS technology in VLSI. Designed Op-Amp consists of differential amplifier & gain amplifier. The
initial stage of differential amplifier removes the noise and only amplifies the actual signal. Since the amplified signal does
not meet Op-amp requirements a gain amplifier is used for amplification. 2nd stage is a common source amplifier which is
used to increase the gain.

Keywords - Cadence gpdk090, gpdk180, Differential Amplifier, Common Source Amplifier, Current Mirror circuit.

I. INTRODUCTION III. RESEARCH WORK

In VLSI design of Op-amp is classified under the MOSFET

category of analog-integrated circuits. Op-amp is The behaviour of an enhancement n-channel metal
operational amplifier providing various oxide field transistor (NMOSFET) is largely
characteristics such as large bandwidth, High input controlled by the voltage at the gate (usually a
impedance, Large gain, Low output impedance It positive voltage). For the usual drain- source voltage
requires 2 supplies with positive and negative equal drops (i:e , the saturation region positive voltages
magnitude, practically, inverting non-inverting. from or few volts up to some breakdown voltage) the
Actual design of Op-amp using CMOS consists of 5 drain current Id is nearly independent of drain-source
NMOS and 3 PMOS transistors. Based on the voltage Vds and instead depends on gate voltage Vg.
configuration Op-amp can also be used as a In field-effect transistors (FETs), depletion mode and
integrator, differentiator ,ADC converter enhancement mode are two major transistors types,
etc.Generalised block diagram Block Diagram of Op- corresponding to whether the transistor is in an ON
amp is illustrated in fig(a) state or OFF state at zero gate-source voltage.

Considering the transfer characteristics of MOSFTET

as shown below
Fig (a).Generalised Differential Amplifier

Analog or digital integrated circuit designed on either

using semicustom design or full custom design has to
follow the standard V.L.S.I flow along with the 10
fold testing method also.

II. V.L.S.I DESIGN FLOW

Fig (c) V-I Characteristics of MOSFET

The characteristics of an nMOS transistor can be

explained as follows. As the voltage on the top
electrode increases further, electrons are attracted to
the surface. At a particular voltage level, which we
will shortly define as the threshold voltage, the
electron density at the surface exceeds the hole
density. At this voltage, the surface has inverted from
the p-type polarity of the original substrate to an n-
type inversion layer, This inversion region is an
Fig (b)

Design of CMOS Multistage High Gain Differential Amplifier using Cadence

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 International Journal of Electrical, Electronics and Data Communication, ISSN(p): 2320-2084, ISSN(e): 2321-2950
Volume-6, Issue-6, Jun.-2018, http://iraj.in
extremely shallow layer, existing as a charge sheet the source and drain. The type of impurity for the
directly below the gate. channel is the same as for the source and drain. Now
a thin layer of SiO2 dielectric is grown over the entire
E-MOSFET surface and holes are cut through the SiO2 (silicon-
Enhancement mode MOSFET are the common dioxide) layer to make contact with the N-type blocks
switching elements in most MOS. These devices are (Source and Drain). In a depletion mode MOSFET,
off at zero gate-source voltage, and can be turned on the device is normally ON at zero gate-source
by pulling the gate voltage either higher than the voltage. Such devices are used as load “resistors” in
source voltage, logic circuits (in depletion load NMOS logic, for
example) For N-type depletion –load devices, the
threshold voltage might be about -3 V, so it could be
turned of by pulling the gate 3V negative (the drain,
by comparison , is more positive than the source in
NMOS) in PMOS, The polarities are reversed. The
mode can be determined by the sign of the threshold
voltage. Depletion load NMOS logic refers to the
logic family that becomes dominant in silicon.

Differential Amplifier
The semi customized differential amplifier is
designed having following specifications
V =5V ,C = 10fF, ICMR = 0.8 to 1.6V, Slew rate
=5V/usec.A ≥40dB,
Fig (d) Enhancement-MOSFET Identically differential amplifier amplifies difference
between two input signals. Thus the differential
Fig (d) shows the construction of an N-channel E- amplifier is having two input terminal and 1 output
MOSFET. The main difference between the terminal.
construction of DE-MOSFET and that of E-MOSFET V ∝ V −V
is of channel formation. As we see from the figures V = A (V − V )
given below the E-MOSFET substrate extends all the Where V is input signal
way to the silicon dioxide (SiO2) and no channels are V is input signal
doped between the source and the drain. Channels are V is output signal
electrically induced in these MOSFETs, when a Ad is known as differential mode gain of differential
positive gate-source voltage VGS is applied to it. for amplifier .The main advantage of differential
NMOS, or lower than the source voltage, for PMOS. amplifier is that it amplifies actual input signals and
In Most circuits, this means pulling an enhancement cancels the noise signal present at its input.
mode MOSFET gate voltage towards its drain voltage
turns it ON.

D-MOSFET

Fig (e) Depletion MOSFET

Fig(f) Differential Amplifier using BJT
Figure shows the construction of an N-channel
depletion MOSFET. It consists of a highly doped P- The above figure show the differential amplifier
type substrate into which two blocks of heavily doped using BJT but it is used for small scale application.
N-type material are diffused forming the source and Another drawback is it can be used only for low
drain. An N-channel is formed by diffusion between frequency application

Design of CMOS Multistage High Gain Differential Amplifier using Cadence

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 International Journal of Electrical, Electronics and Data Communication, ISSN(p): 2320-2084, ISSN(e): 2321-2950
Volume-6, Issue-6, Jun.-2018, http://iraj.in
The differential amplifier can be constructed using MOSFET m3 and m4 transistors are nmos transistor.
BJT & MOSFET depending upon the requirements. In case of saturation region the current Id is given as
When gain is the important parameter then a bipolar
junction transistors are considered but when high 1 W
frequency operating device is required i:e high ID  ( pco x ) (V G S  V t h ) 2
bandwidth is required the MOSFET is considered. 2 L
Mostly MOSFET is preferred over BJT. Because i (1)
Where
loading effect is not present in case of MOSFET also
it is unipolar device u is mobility of holes
The differential amplifier is having to inputs named C is oxide capacitance
as inverting input terminal and non-inverting input V is gate to source voltage
terminal. If we apply signal at inverting terminal then V is the Threshold voltage.
the output signal is amplified180 phase shift. W 2
Similarly if we apply the signal input at the output we  e ff   n co x (V G S  V th )
L
get amplified signal with 0 phase shift hence it is (2)
known as non-inverting terminal. As shown in In case of amplifier transconductance and device
schematic the differential amplifier consist of 5 conductance plays an important role in gain analysis.
MOSFET transistors it is necessary for a MOSFET to Gain is directly proportional to transconductance and
operate is saturation region because current remains inversely proportional to the device conductance.
constant as voltage goes on increasing. g is known as device transaconductance.
g is output resistance.
In case of load the differential amplifier can be
1. Diode connected load. These parameters are obtained by performing dc
2. Current source load. simulation in given schematic supply voltage is taken
3. Single ended load. as 1.8V. Because power dissipation is also an
important factor in case of IC design. The input
common mode range

Parametric analysis

Schematic

Design of CMOS Multistage High Gain Differential Amplifier using Cadence

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 International Journal of Electrical, Electronics and Data Communication, ISSN(p): 2320-2084, ISSN(e): 2321-2950
Volume-6, Issue-6, Jun.-2018, http://iraj.in

DC
Stimulation

IV. RESULTS

MOSFET W(um) Vds(mV) L(um) Transconductance(uV)

M1 6.06 952 1 126
M2 6.06 952 1 126
M3 13 -598 1 105
M4 13 952 1 105
M5 10.5 630 1 200
M6 10.5 249 1 211

fig(g)

CONCLUSION parameter i:e length constant channel modulation

effect is reduced.
From results and gain bandwidth analysis it can be
concluded that variation is MOSFET parameters that REFERENCES
is device width results into increase in bandwidth but
is mandatory of a MOSFET to operate in Saturation [1] Ong, GeokTeng, and Pak Kwong Chan. "A Power- Aware
[2] Wheatstone Bridge Sensors", IEEE Transactions
region. onDifferential amplifiers and Measurement, 2014.
[3] Feedback Instrumentation Amplifier With 2μV Offset”, IEEE
Another conclusion can be made that If the MOSFET Journal Solid State Circuits, Vol. 47, No. 2, pp. 464-475,
February 2012.
is not in saturation region the increase in width causes
[4] Joachim H. Nagel, “Biopotential Amplifiers”, the biomedical
the current to increase which may lead to burn out of engineering handbook: Second Edition. [5] Ed. Joseph D.
circuit. dominant pole effect has to be considered in Bronzino Boca Raton: CRC Press LLC, 2000.
order to achieve good stability. By keeping the device [5] C. Kitchin and L. Counts, “A designer's guide to
Instrumentation Amplifiers”, 3rd edition, Analog Devices
pp. 10-25, 2006.

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