This paper aims to establish a mathematical error model for surface temperature measurement based on FBG and to enhance its measurement precision. Firstly, an improved temperature-sensing model for FBG is established. Subsequently, the mathematical model for FBG-based surface temperature measurement error is developed. The experiments are conducted using a controllable surface heat source. Experimental results demonstrate good consistency among the errors obtained from the mathematical model, the finite element model, and experimental testing. Finally, corrosion processing and thermally conductive silicone packaging methods are proposed, elevating the bare FBG’s surface temperature measurement accuracy from approximately 4°C to approximately 1°C.

Skew angle (SA) is one of the crucial problems in a bit-patterned magnetic recording (BPMR) system. Practically, during the read process, the read head may be tilted up to 30 degrees (°) away from the target track. Without the SA detection and correction mechanism, the performance of the BPMR system will be unbearable. This paper proposes a SA mitigation strategy for a BPMR system based on a multilayer perceptron (MLP) so as to estimate and rectify the SA. Specifically, the MLP-based SA estimator extracts the SA amount directly from the readback signal, which will then be used in the MLP-based detector to produce the estimated recording bits. Simulation results show that the proposed method can estimate the SA embedded in the readback signal more precisely than the conventional one, which just uses a look-up table to detect the SA from the target coefficients. Particularly, for the system operating at an areal density (AD) of 3 terabits per square inch with SA =15° and 30°, the suggested system performs better than the system without the SA mitigation method.

This article proposes a wide input voltage range DC-DC buck converter based on AOT control mode, which can be used in low-power applications such as the Internet of Things and automotive chips. It includes a zero current detector circuit that dynamically modifies the offset voltage, which can detect the inductor current when the buck circuit is operating in DCM mode. By turning off the power transistor in time, the control loss of the buck circuit can be reduced to improve efficiency. The proposed buck converter is designed using 0.18µm standard CMOS process. When a 12V standard input voltage is used to generate a 5V output voltage, the minimum inductor current can reach about 100uA when the low power transistor is turned off when the load current is in the light load range of 1mA-100mA, and the maximum efficiency can be achieved at light load of 93.7%.

This article presents a second-order cascaded integrator feedforward (CIFF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) reusing a dynamic amplifier. The proposed NS architecture uses a gain-optional floating inverter amplifier (FIA) and a sampling-before-integration technique to realize sharp noise transfer function (NTF) with minor extra capacitance. Implemented in 180-nm CMOS technology, the proposed NS-SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 88.6dB over a sampling frequency of 1.6MHz and an oversampling rate (OSR) of 16 while consuming only 250µW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 171.6dB, proving the proposed ADC fulfils considerable performance with both high resolution and low power consumption.

A low-profile wideband dual-polarized antenna with nonuniform metasurface is proposed for 2G/3G/4G/IMT applications. The proposed antenna maintains broad bandwidth and stable gain but has a low profile of only 0.17λ₀ at 2.0GHz, which contributes to the metasurface designed above the radiator. The nonuniform circular elements of the metasurface are set to reduce the coupling between each element, thus stable radiation patterns and low cross-polarization levels can be realized. The test results show a wide impedance bandwidth range from 1.4GHz to 2.79GHz (66.3%) for |S₁₁|<-10dB and high isolation is more than 27dB. The measured stable gain is 9±1dBi. In the entire frequency band, stable radiation patterns are achieved with low cross-polarization levels below -18dB.

In this paper, we proposed a 0.98-ppm/°C, high power supply rejection (PSR), low-noise and curvature-compensated bandgap reference with a resistor-less low-pass filter in 0.18-µm CMOS process. One prominent feature of the circuit is a low-temperature coefficient (TC) measuring less than 1-ppm/°C, achieved through the implementation of high-order curvature compensation. Another notable enhancement is the incorporation of a resistor-less low-pass filter, which effectively improves the PSR and noise performance at medium and high frequencies. Experimental results indicate that the circuit is able to realize an average output reference voltage of 1.21V@4V and an average low TC of 0.98-ppm/°C@-35°C-135°C at different corners. In addition, AC simulation results show that the circuit has a high PSR over the full frequency range and is capable of achieving PSR of -143.7dB@10Hz, -90.1dB@100KHz, and -134.0dB@100MHz. The output noise of the circuit measures 7.73nV/sqrtHz@10Hz, 30.60pV/sqrtHz@10KHz, and 11.75pV/sqrtHz@1MHz.

In this study, a novel noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) architecture is proposed, incorporating a noise transfer function (NTF) strengthening method (NSM). The order of NTF is strengthened by using an extra capacitive digital-to-analog converter (CDAC) and a cascaded Finite Impulse Response-Infinite Impulse Response (FIR-IIR) filter. The prototype converter uses an 8-bit split capacitor CDAC. The NSM is implemented on an NS SAR ADC in 40nm process technology, achieving an Effective Number of Bits (ENOB) of 16.6 bits at an effective bandwidth of 200kHz with an oversampling ratio (OSR) of 32 and has been validated over process-voltage-temperature (PVT). The proposed ADC consumes 1.32mW at a 1.1V supply voltage which occupies an active area of 0.0903mm². The Schrier figure-of-merit (FoM) of 182.8dB is obtained.

Physical Unclonable Functions (PUF) is a kind of hardware security primitive which is vulnerable to machine learning attacks. This work proposed a structural adjustment method based on Arbiter PUF (APUF), with the Strict Avalanche Criterion (SAC) as a guideline, improves the SAC property by leading multiple arbiters to obfuscation circuits at intermediate positions; quantitative analysis of SAC property by optimization method leads to the best placement of arbiters, which improves the utilization of resources. FPGA experiment results show that the proposed method significantly improves PUF’s resistance to machine learning attack such as logistic regression, evolutionary strategies and deep neural networks, and requires lower hardware resources overhead compared to other similar APUF based schemes with the same attack resistance.

In recent years, the use of metasurface to reduce radar cross section has been paid much attention with the rapid development of detection and stealth technology. In this paper, a 2-bit coding metasurface has been designed to realize broadband of Radar Cross Section (RCS) reduction. The designed metasurface consists of four units “00”, “01”, “10”, “11”. Then, Genetic Algorithm (GA) and Antenna Array Theory are used to optimize the arrangement of elements on the metasurface to obtain the optimal scattering characteristics. The measured result coincides with the simulated results. The RCSr curves of simulation and experiment reach below -10dB in the broadband range of 4.4-16.3GHz almost simultaneously. Compared with the metal plate, the beam manipulation capability of this 2-bit digital metasurface is obviously enhanced.

We conducted a study on the frequency dependence analysis of soft error rates using the test circuit composed of scan flip-flops (FFs) and inverters. By irradiating the circuit with alpha particles while the clock was running, soft error rates were measured. During alpha-particle irradiation, soft errors caused by inverters were almost negligible. Soft errors caused by FFs decreases as the operating frequency increases. On the other hand, during Ar irradiation, soft error rate was nearly constant with varying frequency. This is because, the increase in soft errors caused by inverters was roughly equal to the decrease in soft errors caused by FFs unlike alpha-particle irradiation.

This letter presents a fully monolithic microwave-integrated circuit (MMIC) substrate integrated waveguide (SIW) filter using integrated passive device (IPD) technology for Q-band applications. It is challenging to implement an SIW bandpass filter (BPF) at the chip level due to the complex process rules of chip processing. A possible solution is to use multiple TE101 mode SIW resonators to build a BPF via magnetic coupling. However, this layout method can easily cause a larger chip aspect ratio, which is not conducive to the chip’s reliability. To this end, the proposed SIW filter adopts four SIW resonators to form a highly selective BPF through planar stacking. Measurement results show that the minimum insertion loss of the proposed SIW filter is 3.07dB, and fractional BW (FBW) of 4.4% with a compact size of 0.199λ₀², including pad, which is among the best compared to previously reported SIW chip BPFs.

The bilateral filtering algorithm has broad application in image denoising. However, its complex computational and high bandwidth requirements for image data transmission have been limiting factors in its processing speed. This brief presents a high-throughput hardware architecture designed for the bilateral filtering algorithm, supporting images of arbitrary resolution and three convolution window sizes. This architecture reduces the computational through approximation calculations and enhances throughput for high-definition image processing via a data prefetch strategy. Additionally, we introduce a cost-effective MAC unit that minimizes critical path delays and area consumption. In terms of hardware implementation, even on a low-cost Xilinx Zynq-7000 FPGA platform can process 1024*1024 resolution images at over 160 frames per second, with a maximum working frequency of 192MHz.

A multi-load wireless charging platform based on the principle of magnetic coupling resonant wireless power transfer (MCR-WPT) is proposed in this paper. The platform can simultaneously supply power to multiple receivers with different operating frequencies and each load is independent of the others loads. The system consists of a multi-frequency composite current source, a planar transmitter coil, an LC source multi-frequency tuning network, and several receivers operating at different frequencies. The mutual interference caused by cross-coupling and frequency cross-talk when multiple receivers are charging at the same time was analyzed. A load-independent principle to overcome these interferences was provided in the paper. Finally, a dual-frequency multi-load wireless charging experimental platform was built and measured. The well consistency between the experimental results and the theoretical analysis shows the effectiveness of the design method.