In this paper, we propose a resource and timing optimized PCIe DMA architecture using FPGA internal data buffer memory. Firstly, an optimized PCIe DMA control process is proposed, focusing on reducing the capacity of required data buffer memory in PCIe DMA, which is realized by fastening DMA completion response, optimizing DMA register configuration, and avoiding conflicts between multiple threads. Required data buffer memory capacity is reduced by 97.6% from 24.10 MB to 0.56 MB, making FPGA internal memory resource enough for DMA transmission. Secondly, timing failure problems in FPGA caused by large internal memory utilization as PCIe DMA data buffer are solved, realized by a timing-optimized FIFO structure and a low-delay FIFO control mechanism. FPGA memory resource utilization rate without timing failure is increased from 12.4% to 100%, ensuring the reliability of PCIe DMA data transmission. This paper expands the application of PCIe data transmission, reducing the cost and complexity of relevant circuit design.

This paper reports a method to improve a degraded range resolution for FMCW radar. The proposed post-processing method can achieve an improved range resolution without increasing a signal bandwidth by eliminating factors that can degrade the range resolution based on the non-negative least-squares method. For an FMCW radar adopting the post-processing method with the center frequency of 76.5 GHz and the signal bandwidth of 200 MHz, simulation results show that the degraded range resolution of 160 cm is improved to 70 cm, and measurements show that two corner reflectors with the radar cross section of 10 dBsm located at 70 cm range intervals can be distinguished.

A pulse-width modulation (PWM) strategy based on dual carrier is proposed to suppress the common-mode voltage (CMV) of three-phase voltage source inverters (VSIs). This strategy employs two triangle carriers with opposite phase to reduce the peak value of the generated CMV by avoiding zero voltage vectors. In particular, the effective phase range of the two opposite carriers is derived. The optimal initial phase of the dual carrier is determined through the output performance comparison of VSI. Finally, the experimental results are presented to illustrate the feasibility and validity of the proposed modulation strategy.

In this paper, a new (defected ground structure) DGS unit-cell is introduced and its performance is analyzed. The dumbbell-shaped DGS cell is modified by etching off slots in the ground plane to include (defected microstrip structure) DMS behavior without etching any defect in the microstrip line. The degree of freedom of cell design allows setting the bandgap center frequency while enabling a degree of miniaturization. A circuit-model is proposed to provide accurate cell responses. Simulations of the unit-cell with DGS and DMS behavior show moderate electromagnetic (EM) noise from the ground plane. Advantages are illustrated in a fabricated cell occupying approximately 40% less area.

As a new approach to finding integer motion vectors in SCC, hash-based searches have been proposed recently. In the paper we propose an improved search algorithm for integer motion estimation (IME) that employs hash-based search only for 8 × 8 coding units (CUs) and bottom-up search for larger CUs. Furthermore, it updates the hash function and hash table for each CTU to improve coding efficiency and reduce search complexity. According to simulation results, the proposed algorithm provides similar or better coding performance for screen contents while keeping the complexity at a lower level and constant compared with the reference algorithms.