Aiming at the demand for FPGA-based high-bandwidth NVMe SSD host access, this letter presents an NVMe over PCIe Hardware Acceleration Engine (NoPHAE), which has two innovative aspects. Firstly, an NVMe Queues Engine is integrated into the NoPHAE to enhance I/O performance and reduce resource consumption. The NVMe Queues Engine provides dynamic queue configuration and introduces a virtual completion queue, which reduces resource consumption by 20%. Secondly, a PCIe Acceleration Engine is built in the NoPHAE, which implements the co-design of PCIe and NVMe and optimizes the timing for processing PCIe transport layer transactions, resulting in a significant increase in data throughput. Test results indicate that the sequential read and write speed of the NoPHAE is 7.93 times faster than that of the baseline, and the random read and write performance is two times faster than that of the baseline.

Effectively harnessing the correlation information within data through the covariance matrix, a geometrically informed matrix constant false alarm detector proves proficient in target detection amidst sea clutter, employing a limited number of millimeter-wave pulses. However, current matrix CFAR detectors solely rely on a single data channel, exhibiting high computational complexity, thus resulting in diminished utilization of correlation information and constrained detection scenarios. This letter proposes a low-complexity detector based on the maximum eigenvalue derived from dual-channel data. Leveraging Fast Fourier Transform, the authors preprocess data from two channels, construct eigenvalues of the cross-covariance matrix to capture correlations, and employ the maximum eigenvalue as the detection statistic, subsequently devising a matrix CFAR detector based on this dual-channel maximum eigenvalue suitable for practical scenarios. In addition, the detector is verified to achieve better practical detection performance with the measured sea clutter data.

This paper presents a 14-bit 125MS/s pipeline analog-to-digital converter (ADC) which can be used for communication systems, especially in radar and navigation fields. A high-speed sample-and-hold amplifier (SHA) with a high-linearity bootstrapped switch has been integrated into the ADC to remove the aperture error. To improve the gain bandwidth product of amplifiers, a hybrid 1.8V/3.3V MOSFET technique is proposed, wherein 1.8V MOSFETs are used together with 3.3V devices under a 3.3V supply to utilize the higher intrinsic frequency of the 1.8V MOSFET. Meanwhile, a special bias circuit is designed to guarantee the voltage of each terminal pair of 1.8V devices will not exceed its limit value. The ADC is implemented in 0.18µm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1MHz sine input under 3.3V supply, while consuming 272mW power at 125MS/s. The results show that the ADC is suitable for applications where high-speed and high-resolution devices are required.

In the 0.35um BCD process, a low-temperature coefficient, high PSRR bandgap voltage reference with high-order curvature compensation is designed. The circuit is simulated and verified using Cadence software. The results indicate that, operating with a power supply voltage of 3.3V, and functioning across temperatures ranging from -55°C to +125°C, the temperature coefficient of the output reference voltage is 1.064ppm/°C, the output bandgap reference voltage is 1.227V, and the power supply rejection ratio of the circuit at a low frequency of 100Hz is -89dB. This illustrates that the circuit achieves a favorable balance in temperature coefficient and PSRR, demonstrating its practical utility.

This letter presents an 840µm² 557nW temperature sensor front-end designed for system on chip (SoC) thermal monitoring. The circuit is implemented using MOS transistors exclusively, which enhances its scalability with process technologies and compatibility with digital circuit processes. To address MOSFETs circuit’s process variation issues, a differential voltage readout scheme is employed. Dynamic element matching (DEM) is used to minimize mismatch of the circuit. The sensor is self-referenced, eliminating the need for an external reference voltage. Real-time voltage calibration (RVC) scheme is used to improve the performance of supply sensitivity. It is fabricated using a 55nm process, and the measurement results showed an error of -0.69/0.85°C across 16 samples over a temperature range of 0°C to 100°C with a low-cost one-point calibration at 30°C, while the maximum supply sensitivity is 3.3°C/V.

Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28nm CMOS process indicate that the proposed 50Gb/s PAM4 receiver functions well over a channel with 12dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5ps and 2.5ps, respectively.

A silicon mode multiplexer (MUX) based on the three-stage cascaded wavelength insensitive coupler (3CWINC) is proposed and numerically demonstrated. The 3CWINC is composed of three identical asymmetric directional couplers (ADCs) and two different phase adjustment regions placed between each ADC. We numerically show that high-performance mode MUX is easily designed using 3CWINC, which consists of ADC with transmission higher than 25% over the entire operating wavelength range. The designed TE₀-TE₁ mode MUX based on 3CWINC can maintain transmission 94.4% (-0.25dB) or higher even if fabrication error of waveguide width occurs up to 10nm.

In a GNSS receiver, carrier tracking is the most challenging part, especially in a harsh environment. This paper presents an open tracking loop structure to overcome the matter of losing lock under weak-signal conditions. In order to enhance the stability and sensitivity of weak GNSS signal tracking, a frequency-locked loop structure based on DFT interpolated frequency estimation is proposed. The IF signals are split into two branches in the structure, and each signal is correlated with an equally frequency-spaced local carrier. Then, a new DFT interpolation algorithm of two-point DFT interpolation is used as a frequency discriminator to calculate the carrier frequency deviation. The bias and RMSE performances of the frequency discriminator are comparatively analyzed under different SNRs using computer simulations. Simulation results show that this discriminator is characterized by small computational effort and high estimation accuracy. The signal-tracking performances of the structure are verified by an experiment using a GNSS simulator. Results demonstrate that this method is able to track 26dB-Hz signals using only 8 samples, which improves the tracking threshold by 4dB-Hz over the FFT discriminator, and its tracking error jitter is less than 0.5Hz. The structure needs only two-point interpolation, resulting in a low computation load in a real-time receiver.

The inherent characteristics of Micro Electro Mechanical Systems (MEMS) mirrors are subject to change due to operational conditions and usage duration. Currently, most methods for driving, detecting, and compensating electromagnetic MEMS mirrors require complex modules. This paper introduces an approach based almost entirely on Field Programmable Gate Array (FPGA). The proposed method involves the construction of a Direct Digital Synthesizer (DDS) with adjustable frequency, amplitude and phase, a high-precision digital cross-correlation detector, and a proportion integration differentiation (PID) compensator based on FPGA. The system does not necessitate stringent external module requirements and is capable of achieving precise detection and stable operation of the rotation angle of MEMS mirrors.

This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which a 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced pre-emphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, and naturally consumes less power as it boosts only the desired symbols. The FS-based pre/post1 taps equalize the high-frequency loss, provide a wide compensation range beyond the Nyquist frequency, and realize a flexible equalization capability, while the BS-DE-based post2 tap compensates for the low-frequency channel loss. Fabricated in a 28-nm CMOS process, the 64-Gb/s transmitter obtains a differential output swing of 1.4V_ppd with an energy efficiency of 1.53pJ/bit.

A 4-coil boost DC-DC converter circuit with a large voltage gain and high output power is proposed. The target application is the 400V DC microgrid, and the converter boosts a 20V photovoltaic (PV) module voltage directly to the 400V microgrid voltage using the multiphase control scheme. Four coils in 4 different clock phases are used to drive 3 parallel series-capacitor boost converters. Only one-fourth and one-half of the output voltage is required for the reverse bias voltage of transistor switches and diodes, respectively, and reliability problems are avoided. The proposed converter circuit was SPICE simulated using device parameters from commercially available transistors and diodes, and from inductors and capacitors with parasitic components. Simulation results indicate that an 1.5A and a 370V of the output current and voltage, respectively, are obtained with more than 90% of power efficiency. The device count of the circuit was only 16.