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IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 9, Issue 1
Displaying 1-6 of 6 articles from this issue
LETTER
  • 2012 Volume 9 Issue 1 Pages i-v
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
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  • Mohammad Esmaeildoust, Keivan Navi, MohammadReza Taheri, Amir Sabbagh ...
    2012 Volume 9 Issue 1 Pages 1-7
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
    In this paper, we propose efficient designs of residue number system (RNS) to binary converter for the balanced moduli set {2n, 2n+1-1, 2n-1, 2n-1-1} where n has even values. This new moduli set is completely free from modulo-(2k+1)-type which results in high-speed modulo arithmetic channels for RNS. Also, mixed-radix conversion (MRC) algorithm is used to achieve both an arithmetic-based and reduced-complexity two-level RNS to binary converter architectures. The proposed moduli set provides fast arithmetic operation with higher speed of the reverse converter comparing to other five moduli set which is found in literature.
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  • Mohammad Reza Noorimehr, Mehdi Hosseinzadeh, Reza Farshidi
    2012 Volume 9 Issue 1 Pages 8-15
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
    The speed of reverse converters in Residue Number System is one the most important and effective factors which is strictly dependent on the selected moduli set. In this paper, the four-moduli set {2n+k, 22n-1-1, 2n/2+1, 2n/2-1} is introduced with flexible dynamic range 4n to 5n where n is even and k<n. Then a high-speed two-level architecture reverse converter is designed for it based on mix-radix conversion (MRC) algorithm. A comparison to the similar recently introduced moduli sets {2n/2-1, 2n/2+1, 2n+1, 22n+1-1} and {22n, 22n+1-1, 2n/2+1, 2n/2-1} shows that the proposed reverse converter has more conversion speed.
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  • Shun Ueda, Yusuke Miyawaki, Jun Wang, Toshimasa Matsuoka, Kenji Tanigu ...
    2012 Volume 9 Issue 1 Pages 16-22
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
    A chip with which to manipulate microparticles using wireless power transfer and pulse-driven dielectrophoresis has been designed and fabricated using a 0.18-µm CMOS process. The chip enables microparticle manipulation under a 0.7-V power supply and a 13-MHz clock, which are generated on the chip by means of an on-chip coil, a rectifier, and a Schmitt trigger circuit.
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  • Seung Jun Lee, Seung Hwan Jung, Jong Ok Ha, Hyukjun Oh, Yun Seong Eo
    2012 Volume 9 Issue 1 Pages 23-28
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
    A precisely gain controlled RF front end is developed for T-DMB tuner IC applications. A precise RF gain control with 50dB dynamic range is achieved in RF VGA by employing a capacitive ladder type attenuator. The proposed method enables us to design and analyze very fine gain step VGA concretely. Implemented in 0.13µm CMOS, the tuner RF front end consumes 9.7mA at 1.2V supply. Measured results are NF < 1.5dB at the maximum gain and the accurate 1dB gain step is obtained.
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  • Hiroshi Yamamoto, Hiroshi Ito, Makoto Noshiro
    2012 Volume 9 Issue 1 Pages 29-33
    Published: 2012
    Released on J-STAGE: January 10, 2012
    JOURNAL FREE ACCESS
    The temporal variations of the complex relative dielectric constants for water-containing materials in the desiccation process have been measured by photonic millimeter wave ellipsometry. Both the real and imaginary parts decrease exponentially with time due to water evaporation from the samples. It is found that the variation of the imaginary part for a biological tissue sample is more gradual than that of the real part, reflecting the temporal change of the water distribution in the sample.
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