We propose an efficient tag collection algorithm utilizing empty time slots in active RFID systems. In the proposed tag collection algorithm, the reader recognizes the existence of empty time slots via carrier sensing, and utilizes the redundant empty time slots to transmit sleep commands to the tags collected, resulting in performance improvement for tag collection. The simulation results show that the proposed tag collection algorithm can reduce the average tag collection time by 12.28%, 12.30%, and 13.31%, for the framed slotted aloha with the fixed 128 time slots and 256 time slots, and the dynamic framed slotted aloha anticollision protocols, respectively.

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Hybrid mapping technique is one of the most popular FTL (flash translation layer) mechanisms that perform flash address mapping efficiently. As the amount of flash storage grows, entire mapping tables for FTL cannot be loaded into the fast SRAM and physical page addresses are stored in the spare area. In such schemes, a page address cache is usually applied to decrease spare area searching time. However, significant amount of data information should be abandoned even if only a few cached addresses are lost by any power failure.
The proposed method provides a table management scheme for hybrid mapping with its associated page address cache that can recover any lost data. Entire tables are integrated into the proposed map block, stored in a part of flash storage. The proposed table management scheme integrates various meta-data into a single hybrid map block which contains entire physical page table. The initial scan on this map block can generate various meta-data tables. Finally, the simulation results with general PC workload shows that, the proposed address cache shows miss rates below 1%.

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In this paper, we propose a method for increasing the handover performance of the 802.11 link layer. The method reduces the number of scanning channels by referencing an AP map based on GPS. Also, by monitoring the SNRs of the mobile node and neighbor APs, it enables the handover to maintain a higher SNR than a given threshold. The experimental results establish that it has an average disconnection rate of 6.7% and an average SNR of 16.8dB. It is 8.1% lower rate and 42% higher SNR than the method that makes a handover to the nearest AP without considering SNR. Also, it is 4.1% lower rate and 26% higher SNR than the method used by MadWifi.

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While we speak of the haptic model, we are still limited to a mass-spring representation or an FEM. This paper proposes a unified model which haptically renders an object without reference to its material property in an energy domain. Furthermore, we develop a 3D mouse type haptic interface prototype for evaluating the proposed method. We first represent a simple 1D object with the proposed method and extend it to 2D deformable object. We experiment with a virtual object of size 20x20 elements to verify that our approach conveys stable haptic sensation to users.

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The cdma2000 1xEV-DO system has a probabilistic rate control on the reverse link, but a simple up/down command from the base station may make the reverse link unstable. In this paper, we propose and analyze an enhanced rate control that minimizes the traffic overload on the reverse link by predicting the noise rise and defining a new command for stable operation. It is shown that the proposed rate control has a much higher revere-link throughput than the conventional schemes.

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This paper presents a new class AB folded-cascode operational amplifier in standard CMOS technology for fast-settling switched-capacitor circuits. The proposed amplifier employs the class AB operation in both nMOS and pMOS output current source transistors by employing only a few passive components without any extra static power dissipation and results in large slew rate, enhanced unity-gain bandwidth and DC gain, and reduced input-referred noise compared to the conventional folded-cascode amplifier. Circuit level analysis and simulation results are provided to verify the effectiveness of the proposed amplifier.

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The variable length coding (VLC) has gained greater attention due to its wide application in the international standard, H.264/AVC and Chinese standard, AVS. A First-one detector is an indispensable module of VLC, such as CAVLC and Exp-Golomb coding. In this paper, a novel First-one implementation architecture is proposed, which can locate the First-one in the codeword in only one cycle. The architecture applies the combinational logic to parse the position of the separator ‘1'. Compared with the conventional methods, this approach has higher efficiency.

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A low loss, small crosstalk offset crossing structure for a Si wire waveguide is proposed. We analyzed the properties of the structure for both the TE and TM modes by 2-D FDTD (two-dimensional finite difference time domain) simulation. By optimizing the offset crossing structure, a transmission loss of 0.021dB, and crosstalk of -55.0dB was achieved with a crossing angle of 20 degrees for the TE mode. A transmission loss of 0.070dB, and crosstalk of -48.6dB was also achieved with the same crossing angle for the TM mode. The low losses achieved with a small crossing angle makes this structure very useful for highly integrated optical matrix switches, etc.

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Novel design of large-mode-area leakage channel fibers (LCFs) with a single air-hole ring surrounding a multi-unit-cell solid core is investigated for realizing robust single-mode and low bending loss characteristics. We perform detailed numerical simulations using a finite element method, and we show that the proposed LCFs with a solid core formed by multiple missing neighboring air-holes can achieve much lower bending losses compared with the reported LCF with six large air-holes.

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This paper presents the radio frequency power detector design for the bias control of the power amplifiers using a DC to DC converter. Non-diode type power detector has large bandwidth which is important for fast tracking of the non-constant envelope RF signal such as in WCDMA (wideband CDMA) system. The measured result shows the output voltage of power detector from 0.77V at low output power to 1.806V at 27.5dBm output. The variation of the detector output voltage is less than 60mV because of the temperature compensated current sources when the ambient temperature is varied from -30°C to 85°C.

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On the basis of the formal resemblance between the nonlinear Schrödinger equation that governs the evolution of an optical signal in a single-mode fiber and the telegrapher's equations that describe the voltage and current on an electrical transmission line, the nonlinear Schrödinger equation is modeled in an electrical equivalent circuit. Through the equivalent circuit simulations for the propagation of an optical fundamental soliton, the validity of the proposed model, that is, the correctness of the handling of the dispersion, the nonlinearity, and the attenuation in the model, is verified.

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Many DSP applications such as digital filters and linear transforms are composed of multiple constant multiplication (MCM) circuits. In hardware design of MCM circuits, it is important to decrease the hardware cost to the minimum. For a design of MCM circuits with minimum cost, it is a feasible approach to apply combinatorial optimization algorithms. However, if implemented as software, the time needed for optimization increases rapidly as the circuit scale increases. In the design procedures, circuit synthesis is the most time-consuming module, and it is called the most frequently. The purpose of this study is to develop a hardware-oriented circuit synthesis module using FPGAs to shorten the time spent on the design of MCM circuits.

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