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WO2023108847A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023108847A1
WO2023108847A1 PCT/CN2022/071014 CN2022071014W WO2023108847A1 WO 2023108847 A1 WO2023108847 A1 WO 2023108847A1 CN 2022071014 W CN2022071014 W CN 2022071014W WO 2023108847 A1 WO2023108847 A1 WO 2023108847A1
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WO
WIPO (PCT)
Prior art keywords
airfoil
fan
area
electrically connected
wiring
Prior art date
Application number
PCT/CN2022/071014
Other languages
English (en)
French (fr)
Inventor
徐敬义
孙建
闫伟
肖振宏
张亚东
王珍
霍培荣
刘弘
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/017,572 priority Critical patent/US20240295936A1/en
Priority to CN202280000021.6A priority patent/CN116615775A/zh
Publication of WO2023108847A1 publication Critical patent/WO2023108847A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the fan-out wiring in the fan-out area is very densely arranged, and the fan-out The line width of the outgoing line is narrow, which makes the resistance of the fan-out line large, making it difficult to realize high-frequency charging of display products.
  • an embodiment of the present application provides a display panel, including:
  • a fan-out area located on one side of the display area
  • the display panel includes:
  • part of the fan-out wiring extends from the fan-out area to the area where the first side is located, and is electrically connected to the output terminal; another part of the fan-out wiring is connected to the airfoil wiring through the airfoil
  • the output terminals are electrically connected, and the wing-shaped wiring passes through an area where at least one of the first side, the two third sides, and the second side is located.
  • the airfoil traces pass through the area where the first side is located.
  • the airfoil traces pass through the area where the second side is located.
  • part of the airfoil routing passes through the area where the second side is located, and another part of the airfoil routing passes through at least one of the two third sides The area where the sides are located passes through.
  • part of the airfoil routing passes through the area where the first side is located, and another part of the airfoil routing passes through at least one of the two third sides The area where the sides are located passes through.
  • the display panel further includes a plurality of receiving terminals configured to be bound together with the output terminals of the driver chip;
  • the orthographic projection on the substrate of the panel overlaps the orthographic projection of the output terminal on the substrate; part of the receiving terminal is electrically connected to the fan-out wiring passing through the area where the first side is located , the other part of the receiving terminal is electrically connected to the wing-shaped wiring;
  • the orthographic projection of the wing-shaped wiring on the substrate overlaps with the orthographic projection of at least one receiving terminal on the substrate .
  • the receiving terminals electrically connected to the airfoil traces are divided into a first group arranged along the first side and a second group arranged along the second side. group; the airfoil traces electrically connected to the receiving terminals in the first group are arranged on the same layer, and the airfoil traces electrically connected to the receiving terminals in the second group include a first airfoil trace and a second wing trace Type wiring, and the first airfoil wiring and the second airfoil wiring are located on different layers;
  • the airfoil traces electrically connected to the first group of receiving terminals and the second airfoil traces of the second group of airfoil traces electrically connected to the receiving terminals are arranged on the same layer.
  • the receiving terminal to which the wing-shaped wiring is electrically connected includes:
  • the gate layer on the substrate includes two conductive pads that are independent and opposite to each other;
  • a source-drain metal layer covering the dielectric layer and directly contacting the exposed part of the conductive pad
  • An electrode layer, covering the source-drain metal layer, is configured to be in direct contact with the output terminal of the driving chip.
  • each of the second wings in the wing-shaped traces electrically connected to the first group of receiving terminals and the wing-shaped traces electrically connected to the second group of receiving terminals Type traces are located on the gate layer, and pass through the area between the two conductive pads of the receiving terminal.
  • one wing-shaped trace is electrically connected to the conductive pad, and the first group of receiving terminals is electrically connected to the receiving terminal.
  • the orthographic projections of other connected airfoil traces on the substrate and the orthographic projections of the conductive pads on the substrate do not overlap each other;
  • one of the second wing-shaped traces is electrically connected to its conductive pad, and the other second
  • the orthographic projections of the airfoil traces on the substrate and the orthographic projections of the conductive pads on the substrate do not overlap each other.
  • the display panel further includes a plurality of spare receiving terminals, and the spare receiving terminals have the same structure as the receiving terminals;
  • the spare receiving terminal arranged in the same row as the first group of receiving terminals is a first spare receiving terminal, and the spare receiving terminal arranged in the same row as the second group of receiving terminals is a second spare receiving terminal;
  • At least part of the wing-shaped wiring electrically connected to the first group of receiving terminals passes through the area between the two conductive pads in the first spare terminal, and is connected with the receiving terminal of the second group. At least part of the wing-shaped traces to which the terminals are electrically connected passes through a region between two conductive pads in the second spare terminal.
  • the fan-out routing includes a display fan-out routing and a touch fan-out routing
  • Each of the touch fan-out lines extends from the fan-out area to the area where the first side is located, and is electrically connected to the output terminal; some of the display fan-out lines pass through the airfoil line electrically connected to the output terminal.
  • the airfoil wiring includes a display airfoil wiring and a touch airfoil wiring
  • the fanout wiring includes a display fanout wiring and a touch fanout wiring
  • Part of the display fan-out wiring is electrically connected to the output terminal through the display airfoil wiring, and part of the touch fan-out wiring is electrically connected to the output terminal through the touch airfoil wiring.
  • the airfoil traces are arranged on the same layer.
  • some of the airfoil traces are arranged on the same layer, and another part of the airfoil traces includes a first airfoil trace and a second airfoil trace, and the first airfoil trace
  • the wiring and the second airfoil wiring are located on different layers;
  • the airfoil traces arranged on the same layer extend from the binding area to the fan-out area, and include the first line segment, the second line segment, the third line segment, the fourth line segment and the fifth line segment connected in sequence.
  • the airfoil routing includes a first airfoil routing and a second airfoil routing, and the first airfoil routing and the second airfoil routing are located on different layers ;
  • the first airfoil routing extends along a first direction
  • the second airfoil routing includes a first segment extending along a second direction
  • the first airfoil routing is connected to the fan-out routing and
  • the first line segment is electrically connected
  • the first direction is a direction in which the display area points to the binding area
  • the second direction is parallel to the first direction
  • the orthographic projection of the first line segment on the substrate of the display panel overlaps with the orthographic projection of the first airfoil wiring electrically connected thereto on the substrate.
  • the second airfoil routing further includes a second line segment and a third line segment, the second line segment extends along the third direction, the first line segment, the second line segment sequentially connected to the third line segment, the third line segment is electrically connected to the output terminal; the third direction intersects the first direction;
  • the angle between the extension line of the first line segment and the extension line of the second line segment is a right angle, and the extension line of the second line segment and the extension line of the third line segment The angle between the extension lines is a right angle;
  • the angle between the extension line of the first line segment and the extension line of the second line segment is an obtuse angle
  • the angle between the extension line of the second line segment and the extension line of the third line segment are obtuse angles, and both such obtuse angles are the same angle
  • the angle between the extension line of the first line segment and the extension line of the second line segment and the angle between the extension line of the second line segment and the extension line of the third line segment One of them is a right angle and the other is an obtuse angle.
  • a first corner is provided between the first line segment and the second line segment, and a second corner is provided between the second line segment and the third line segment;
  • At least some of the corners are rounded.
  • At least one island-shaped figure is arranged between two adjacent first corners, and the island-shaped figures between two adjacent first corners are not connected to each other;
  • At least one island-shaped figure is arranged between two adjacent second corners, and the island-shaped figures between two adjacent second corners are not connected to each other.
  • part of the second airfoil routing is located on the same layer, another part of the second airfoil routing is located on the same layer, and the two parts of the second airfoil routing are located on different layers ;
  • every two first line segments are divided into a group, and each group of the first line segment routing groups includes an outer first line segment and an inner first line segment arranged along the third direction.
  • the orthographic projection of the second line segment electrically connected to the outer first line segment on the substrate and the second line segment electrically connected to the inner first line segment Orthographic projections of the second line segment on the substrate overlap.
  • test unit and a plurality of test connection lines are included;
  • test unit is located on a side of the area where each output terminal is located away from the display area; the test connection wiring is configured to connect the test unit and the output terminal;
  • the output terminal electrically connected to the airfoil trace is also directly electrically connected to the test connection trace.
  • the orthographic projection of the airfoil trace on the substrate electrically connected to the same output terminal partially intersects the orthographic projection of the test connection trace on the substrate. stack.
  • a test unit is included, and the test unit is divided into a display test unit and a touch test unit;
  • At least one of the display test unit and the touch test unit is located on a side of the display area away from the fan-out area, and the remaining one is located in the fan-out area or the binding area.
  • the area on the side of the display area away from the fan-out area includes a central area and two corner areas located on both sides of the central area; the display test unit and the touch
  • Each control test unit includes a plurality of test subunits, and the projection shape of the test subunits on the substrate is a rectangle;
  • each of the test subunits in the corner area is arranged around the edge of the display area; the long sides of the rectangles in the corner area are parallel, or the two adjacent rectangles in the corner area There is an included angle of preset angle between the long sides.
  • the display panel includes a plurality of first signal adjustment lines, and the first signal adjustment lines are located between the fan-out line and the airfoil line;
  • the arrangement sequence of each fan-out wiring is different from the arrangement order of each airfoil wiring;
  • the arrangement sequence is the same as that of each fan-out routing, and the arrangement sequence of one end of each of the first signal adjustment lines connected to the airfoil routing is the same as the arrangement sequence of each of the airfoil routings ;
  • the third direction intersects the first direction.
  • the display panel includes a plurality of second signal adjustment lines, and for each of the fan-out lines electrically connected to the output terminal through the area where the first side is located, the fan-out line
  • the second signal adjustment line is also arranged between the line and the output terminal;
  • the arrangement order of each fan-out wiring is different from the arrangement order of each said output terminal; the arrangement order of each end of each second signal adjustment line connected to the fan-out wiring
  • the arrangement order of each of the fan-out wirings is the same, and the arrangement order of one end of each of the second signal adjustment lines connected to the output terminal is the same as the arrangement order of each of the output terminals; the third direction intersects the first direction.
  • At least part of the line segments of each of the first airfoil routings is a serpentine structure.
  • the material of part of the fan-out traces is a first conductive material
  • the material of another part of the fan-out traces is a second conductive material
  • the resistance of the first conductive material is greater than that of the the resistance of the second conductive material
  • the material is a part of each of the fan-out traces of the first conductive material electrically connected to the first airfoil trace, and the material is a part of each of the fan-out traces of the second conductive material and the The first airfoil wiring is electrically connected;
  • the first airfoil trace electrically connected to the fan-out trace whose material is the first conductive material has a serpentine structure.
  • the driving chip further includes a plurality of input terminals, and each of the input terminals is arranged along the extending direction of the second side;
  • the orthographic projection of the airfoil trace on the substrate of the display panel and the orthographic projection of the input terminal on the substrate do not overlap each other.
  • the fan-out routing includes a connected first fan-out segment and a second fan-out segment, the first fan-out segment is electrically connected to the signal line of the display area, and the first fan-out segment is electrically connected to the signal line of the display area.
  • the two fan-out sections are electrically connected to the output terminal;
  • the sine value of the preset included angle is equal to half of the width of the area occupied by all the second fan-out segments along the direction perpendicular to its extension and the width of the display area along the direction parallel to the first side ratio.
  • embodiments of the present application provide a display device, including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in a related art provided by an embodiment of the present application
  • Fig. 2-Fig. 6, Fig. 10 are the structural representations of six different display panels provided by the embodiments of the present application.
  • FIG. 7 is a schematic structural diagram of a binding region of the display panel shown in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a binding region of the display panel shown in FIG. 3;
  • FIG. 9 is a schematic structural diagram of a binding region of the display panel shown in FIG. 10;
  • FIG. 11 and FIG. 12 are two structural schematic diagrams of the corner area of the display panel shown in FIG. 10 ;
  • Fig. 13 is a schematic structural diagram of a first signal adjustment line/second signal adjustment line provided by an embodiment of the present application.
  • Fig. 14 is a schematic diagram of a serpentine structure of a first airfoil routing provided by an embodiment of the present application
  • FIG. 15 is a schematic diagram of an airfoil wiring structure of a display panel displaying touch integration technology provided by an embodiment of the present application.
  • FIG. 16 and FIG. 19 are structural schematic diagrams of two airfoil traces passing through the second side of the driver chip provided by the embodiment of the present application;
  • FIG. 17 is a schematic diagram of a setting position of a fan-out routing provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a binding area and a fan-out area of a display panel provided by an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of a display panel in another related art provided by an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of the receiving terminal in FIG. 20;
  • Fig. 23 is a schematic cross-sectional view of Fig. 22 along the direction A1A2;
  • FIG. 24 is a schematic structural diagram of the receiving terminal in FIG. 21;
  • Fig. 25 is a schematic cross-sectional view along the B1B2 direction of Fig. 24;
  • FIG. 26 is a schematic diagram of a design dimension of the display panel shown in FIG. 20;
  • FIG. 27 is a schematic diagram of a design dimension of the display panel shown in FIG. 21;
  • Fig. 28-Fig. 40 are structural schematic diagrams of twelve kinds of display panels provided by the embodiments of the present application.
  • the fan-out area of the display panel is provided with very dense driving signal lines 1 (also called fan-out routing), which greatly reduces the design space of the fan-out area.
  • driving signal lines 1 also called fan-out routing
  • the line width of the driving signal line 1 is narrow, the resistance of the driving signal line 1 itself is relatively large, making it difficult to realize high-frequency charging of display products.
  • an embodiment of the present application provides a display panel, as shown in FIG. 2 and FIG. 3 , including:
  • a fan-out area F located on one side of the display area AA;
  • the binding area B located on the side of the fan-out area F away from the display area AA; the binding area B is provided with a driver chip IC, and the driver chip IC includes a first side 101 adjacent to the fan-out area F, and the first side The second side 102 opposite to the side 101, the two third sides 103 connecting the first side 101 and the second side 102; the driver chip IC also includes a plurality of output terminals 4, and the output terminals are close to the first side 101 set up;
  • the display panel includes:
  • a plurality of airfoil traces 3 located at least in bonding area B;
  • part of the fan-out wiring 2 extends from the fan-out area F to the area where the first side 101 is located, and is electrically connected to the output terminal 4; another part of the fan-out wiring 2 is electrically connected to the output terminal 4 through the wing-shaped wiring 3, And the airfoil trace 3 passes through the area where at least one of the first side 101 , the two third sides 103 and the second side 102 is located.
  • part of the fan-out routing and another part of the fan-out routing involved in the embodiments of this application refers to two different fan-out routings, but the embodiments of this application provide The fan-out routing includes but is not limited to these two parts, and may also include fan-out routing of other parts.
  • the relevant descriptions of "one part, another part; one part, another part” mentioned elsewhere in the following text have similar meanings here, and will not be repeated here.
  • part of the fan-out trace 2 is electrically connected to the output terminal 4 through the airfoil trace 3. It can be understood that the airfoil trace 3 is located between the fan-out trace 2 and the output terminal 4, And the airfoil trace 3 is at least located in the bonding area B.
  • each airfoil trace 3 is located in the binding area B; or, part of the airfoil traces 3 is located in the binding area B, and the other part
  • the airfoil trace 3 may extend from the bonding area B to the fan-out area F; or, a part of the airfoil trace 3 is located in the bonding area B, and another part of the airfoil trace is located in the fan-out area F.
  • the airfoil trace 3 is located in the bonding area B, and is wound from the bonding area B through the airfoil trace 3 to electrically connect a part of the fan-out trace 2 with the corresponding output terminal.
  • part of the line segment of the airfoil trace 3 is located in the bonding area B, and another part of the line segment of the airfoil trace 3 is located in the fan-out area F. It can be understood that the airfoil trace 3 is located in the bonding area B Area B extends to the fan-out area F, winds from the bonding area B to the fan-out area F through the airfoil trace 3, and then passes through the first side 101 to connect part of the fan-out trace 2 and the corresponding output terminal 4 connect.
  • the specific type of the above-mentioned driving chip IC is not limited here.
  • the above-mentioned driving chip may be a display driving chip; or, the above-mentioned driving chip may also be a TDDI chip.
  • the above-mentioned fan-out wiring 2 may include a display fan-out wiring (also called a display driving line or a source driving line); or, the above-mentioned fan-out wiring 2 may include a touch fan-out wiring; or, the above-mentioned fan-out wiring 2 Also includes display fan-out routing and touch fan-out routing.
  • a display fan-out wiring also called a display driving line or a source driving line
  • the above-mentioned fan-out wiring 2 may include a touch fan-out wiring
  • the above-mentioned fan-out wiring 2 also includes display fan-out routing and touch fan-out routing.
  • the fan-out traces include display fan-out traces and touch fan-out traces at the same time.
  • part of the display fan-out wiring can be set to be electrically connected to the output terminal 4 through the wing-shaped wiring 3, and the wing-shaped wiring 3 connects from the first side 101, the two third sides 103 and the second The area where at least one side of the two sides 102 is located passes through, and the touch fan-out wiring and another part of the display fan-out wiring extend from the fan-out area F to the area where the first side 101 is located, and are electrically connected to the output terminal 4 connect.
  • part of the touch fan-out wiring can be set to be electrically connected to the output terminal 4 through the wing-shaped wiring 3, and the wing-shaped wiring 3 is connected from the first side 101, the two third sides 103 and the second side 102. Passes through the area where at least one side is located, showing that the fan-out wiring and another part of the touch fan-out wiring extend from the fan-out area F to the area where the first side 101 is located, and are electrically connected to the output terminal 4 .
  • part of the touch fan-out wiring and part of the display fan-out wiring can be electrically connected to the output terminal 4 through the wing-shaped wiring 3, and the wing-shaped wiring 3 connects from the first side 101, the two third sides 103 and The area where at least one side of the second side 102 is located passes through, the other part shows the fan-out wiring and the other part of the touch fan-out wiring extends from the fan-out area F to the area where the first side 101 is located, and is connected with the output Terminal 4 is electrically connected.
  • the display panel includes a touch sensor Sensor for realizing the touch function, and a plurality of touch electrode lines for connecting each touch sensor and each touch fan-out line.
  • the line TX is used to connect each pixel unit and a plurality of data signal lines Data of each display fan-out line.
  • each touch electrode trace TX is located on both sides of the display area AA, and each data signal line Data is located in the display area AA
  • the display fan-out trace (not drawn in FIG. 5 ) electrically connected to the data signal line Data can be arranged in In the middle area of the fan-out area F, the touch fan-out lines electrically connected to the touch electrode lines TX are arranged on both sides of the display fan-out lines, wherein the fan-out area F shown in FIG. 5 is drawn as Touch fan-out wiring.
  • the display fan-out wiring that is electrically connected to the data signal line Data can extend from the fan-out area F to the area where the first side 101 is located, and be electrically connected to the output terminal 4, so that the touch electrode wiring TX is electrically connected to the display fan-out wiring.
  • the touch fan-out wiring is electrically connected to the output terminal 4 through the wing-shaped wiring 3 .
  • each touch electrode trace TX and each data signal line Data are located in the display area AA, the extension direction and the arrangement direction of the touch electrode trace TX and the data signal line Data are the same, and the touch electrode trace TX and the data signal line
  • the signal lines Data are arranged alternately.
  • two touch electrode traces TX and one data signal line Data may be alternately arranged sequentially, or alternately arranged in other ways.
  • the touch fan-out lines electrically connected to the touch electrode lines TX in the fan-out area F and the display fan-out lines electrically connected to the data signal lines Data may also be alternately arranged.
  • part of the fan-out wiring can be set to directly extend from the fan-out area F to the area where the first side 101 is located, and be electrically connected to the output terminal 4, and the other part can be set to show that the fan-out wiring passes through the airfoil wiring 3 and the output terminal 4 Electrical connection; part of the touch fan-out wiring is set to extend from the fan-out area F to the area where the first side 101 is located, and is electrically connected to the output terminal 4, and the other part of the touch fan-out wiring is connected to the output terminal through the airfoil wiring 3 4 electrical connections.
  • the setting part shows the fan-out lines 21 It is electrically connected to the output terminal 4 through the wing-shaped wiring 3 (the first wing-shaped wiring 31 and the second wing-shaped wiring 32 ).
  • the above-mentioned display panel may be any one of an LCD (Liquid Crystal Display, Liquid Crystal Display) display panel, an OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display panel, a Mini LED display panel or a Micro LED display panel.
  • LCD Liquid Crystal Display, Liquid Crystal Display
  • OLED Organic Light Emitting Diode, Organic Light Emitting Diode
  • Mini LED Organic Light Emitting Diode
  • Micro LED display panel a Micro LED display panel.
  • the size of the above-mentioned display panel is not limited, and it can be applied to a UHD (Ultra High Definition, ultra-high definition) display device or an HD (High Definition, high-definition) display device of a large size or an ultra-large size (for example: 86 inches), or, Small-sized (for example: 23.6 inches) UHD display device or HD display device can be applied.
  • UHD Ultra High Definition, ultra-high definition
  • HD High Definition, high-definition
  • the above-mentioned display panel may be a display panel of non-TDDI (Touch and Display Driver Integration, touch and display integration) technology, or may be a display panel of TDDI technology.
  • TDDI Touch and Display Driver Integration, touch and display integration
  • the display panel of TDDI technology can be divided into ADS (Advanced Super Dimension Switch, Advanced Super Dimension Switch) liquid crystal touch display or HADS liquid crystal touch display, and the specific type of the display panel is not discussed here. limited.
  • ADS Advanced Super Dimension Switch, Advanced Super Dimension Switch
  • HADS HADS liquid crystal touch display
  • the driver chip IC is a display driver chip
  • the drive signal line 1 is a display driver line (Source line)
  • the display driver line can transmit the display driver signal output from the display driver chip to
  • the data signal lines (Data lines) in the display panel are used to control the display of each pixel unit in the display area.
  • the driving chip IC is a TDDI chip
  • the driving signal line 1 includes a display driving line and a touch driving line
  • the display driving line can transmit the display driving signal output from the TDDI chip to the data signal in the display panel.
  • line (Data line) to control the display of each pixel unit in the display area
  • the touch drive line can transmit the touch drive signal output from the TDDI chip to the touch electrode line (TX line) in the display panel to control Touch sensor (Touch sensor) realizes the touch function.
  • Touch sensor Touch sensor
  • the fan-out area of the display panel with TDDI technology is not only provided with display drive lines, but also with touch drive lines, the design space for the fan-out area of the display panel with TDDI technology is more limited, and it is difficult to achieve high-frequency charging. bigger.
  • a plurality of airfoil traces 3 are arranged in the bonding area B, and the wires are wound through the airfoil traces 3 (including from the upper side, the left and right sides and the lower side of the driver chip). Winding at the position of the side), so that part of the fan-out trace 2 is electrically connected to the output terminal 4 of the driver chip through the airfoil trace 3, thereby utilizing the area where the driver chip is not set in the bonding area B, and shortening the airfoil The length of the fan-out trace 2 electrically connected to the trace 3 greatly reduces the space occupied by the fan-out trace 2 in the fan-out area B.
  • the distance between the fan-out wires 2 can greatly reduce the resistance of the fan-out wires 2 itself, so that high-frequency charging of each pixel unit in the display area AA can be realized, the charging rate of the display panel can be improved, and the charging time can be shortened. time, reducing the power consumption of the display panel.
  • the area where the driver chip is set shortens the length of the fan-out line 2 electrically connected to the airfoil line 3, thereby reducing the dimension d2 of the fan-out area F along the direction of the display area AA pointing to the fan-out area F, compared with the related In the technology, the dimensions d1 and d2 of the fan-out region F along the display area AA pointing to the direction of the fan-out region F can be 0.1mm-0.2mm smaller than d1, which is conducive to the preparation of a display panel with a narrow frame.
  • the airfoil trace 3 passes through the area where the first side 101 is located.
  • the airfoil trace 3 can extend from the bonding area B to the fan-out area F, and wrap the wire from the area where the first side 101 is located, so that this part of the fan-out trace 2 passes through the airfoil trace 3 and the output Terminal 4 is electrically connected.
  • a small number of airfoil traces 3 can be set to pass through the area where the first side 101 is located and electrically connected to the output terminal 4 according to the situation, so that to a certain extent Reduce the design space occupied by the fanout trace 2 in the fanout area B.
  • part of the airfoil traces 3 passes through the area where the first side 101 is located, and part of the airfoil traces 3 passes through the area where the third side 103 is located as an example.
  • the airfoil wire 3 passes through the area where the second side 102 of the driving chip IC is located.
  • a circuit board is also provided between the second side 102 of the driver chip IC and the edge of the display panel, and the wing-shaped wiring 3 can pass through the area between the second side 102 and the circuit board, and then pass through The area where the second side 102 is located is electrically connected to the output terminal 4 of the driver chip.
  • part of the wing-shaped wiring 3 passes through the area where the second side 102 of the driver chip IC is located, and another part of the wing-shaped wiring 3 passes through the two third sides 103 of the driver chip IC. Crosses the area where at least one side of the .
  • the airfoil wire 3 passes through the area where at least one of the two third sides 103 of the driver chip IC is located.
  • the airfoil traces 3 can be arranged to connect from both sides (103) and the lower side of the driver chip IC. (102) area winding.
  • the wiring quantity of the wing-shaped wiring 3 that is, the fan-out wiring 2 the number of windings
  • the minimum distance between the area where the output terminal 4 of the driver chip is located and the area where the input terminal 5 of the driver chip is located the line width of the airfoil trace 3, and the width of two adjacent airfoil traces
  • the gap between 3 is related.
  • the sum (Pitch) of the line width of the airfoil trace 3 and the gap between two adjacent airfoil traces 3 is 4.0 ⁇ m, and the area from the area where the output terminal 4 of the driver chip is to the area where the input terminal 5 of the driver chip is located is 4.0 ⁇ m.
  • the minimum distance between the regions is 400 ⁇ m, 100 airfoil traces 3 can be set, and 100 fan-out traces 2 can be routed.
  • the number of windings of each fan-out wire 2 can be determined according to the situation, which is not limited here.
  • FIG. Crosses the area where at least one side of the .
  • the fan-out trace 2 since part of the fan-out trace 2 is electrically connected to the output terminal 4 of the driver chip after being wound from the bonding area B through the airfoil trace 3, in the fan-out area F, it is electrically connected to the airfoil trace 3
  • the display panel further includes a plurality of receiving terminals 41, and the receiving terminals 41 are configured to be bound together with the output terminals 4 of the driver chip;
  • the orthographic projection on the substrate and the orthographic projection of the output terminal 4 on the substrate overlap; part of the receiving terminal 41 is electrically connected to the fan-out wiring 2 passing through the area where the first side 101 is located, and the other part of the receiving terminal 41 is connected to the wing Type 3 electrical connection;
  • the orthographic projection of the wing-shaped wiring 3 on the substrate overlaps with the orthographic projection of at least one receiving terminal 4 on the substrate.
  • the overlapping meaning of the orthographic projection of the receiving terminal 41 on the substrate of the display panel and the orthographic projection of the output terminal 4 on the substrate means that the outer contour of the receiving terminal 41 is on the substrate of the display panel
  • the orthographic projection on the substrate and the orthographic projection of the output terminal 4 on the substrate overlap; or, the orthographic projection of the receiving terminal 41 on the substrate of the display panel and the output terminal 4 on the substrate
  • the orthographic projections on the bottom overlap completely.
  • the receiving terminal 41 is connected to the output terminal 4 of the driver chip in a one-to-one correspondence, and the airfoil trace 3 or the fan-out trace 2 are first electrically connected to the receiving terminal 41, and the receiving terminal 41 is then bonded (Bonding) is electrically connected to the output terminal 4 of the driver chip.
  • the first group of receiving terminals S1 is used as an example for illustration.
  • the first group of receiving terminals S1 includes five receiving terminals 41; wherein, for the first receiving terminal 41, the first group of receiving terminals S1 The wing-shaped traces 3 electrically connected to the five receiving terminals 41 in the group overlap with it in the direction perpendicular to the substrate; for the second receiving terminal 41, except for the first receiving terminal S1 in the first group of receiving terminals S1 The other four wing-shaped traces 3 other than the wing-shaped trace 3 electrically connected to the terminal 41 overlap with it in the direction perpendicular to the substrate; for the third receiving terminal 41, the first group of receiving terminals S1 Except for the wing-shaped wiring 3 electrically connected to the first and second receiving terminals 41, the other three wing-shaped wirings 3 overlap with it in the direction perpendicular to the substrate; for the fourth receiving terminal 41.
  • the other two wing-shaped wirings 3 are all running along the direction perpendicular to the substrate.
  • the fifth receiving terminal 41 only the airfoil trace 3 electrically connected to the fifth receiving terminal 41 overlaps with it in the direction perpendicular to the substrate.
  • the accompanying drawing 21 provided in the embodiment of the present application only includes 5 receiving terminals in the first group of receiving terminals S1, and 5 receiving terminals in the second group of receiving terminals S2, and the left area of the binding area B includes 10 receiving terminals.
  • the airfoil alignment is drawn as an example. In practical applications, the specific number is not limited and can be determined according to design requirements.
  • the accompanying drawing 21 provided in the embodiment of the present application only takes a plurality of receiving terminals 41 arranged in two rows as an example.
  • the plurality of receiving terminals 41 can also be arranged as Three rows, or a plurality of receiving terminals 41 arranged in four rows, or arranged in other ways, which can be determined according to the arrangement of the output terminals 4 , which is not limited here.
  • the orthographic projection of the fan-out trace 2 on the substrate and the orthographic projection of the receiving terminal 41 on the substrate are not overlapped, as shown in FIG. 21 .
  • the orthographic projection of the wing-shaped wiring 3 on the substrate is consistent with at least one receiving terminal 4
  • the overlap of the orthographic projection on the substrate saves the design space of the fan-out area F of the display panel; on the other hand, saves the space between the receiving terminals 41, and can design the receiving terminals 41 more flexibly Therefore, the arrangement position of the output terminal 4 in the driver chip can be set more flexibly, or in other words, the type of the driver chip that can be matched can be selected more flexibly.
  • the design size of the display panel in the related art shown in FIG. 20 is shown in FIG. 26 .
  • the width of the fan-out region F of the display panel shown in FIG. 21 provided by the embodiment of the present application is ( The distance between the edge of the display area AA and the first side of the driving chip IC) is 0.1 mm smaller than the width of the fan-out area F of the display panel in the related art.
  • the units of the numbers marked in Fig. 26 and Fig. 27 are all millimeters (mm).
  • the airfoil wires 3 electrically connected to the first group of receiving terminals S1 and the second airfoil wires 32 electrically connected to the second group of receiving terminals S2 are arranged on the same layer.
  • each second wing-shaped wiring 32 in the wing-shaped wiring 3 electrically connected to the first group of receiving terminals S1 and the second group of receiving terminals S2 is the same.
  • its material is the same as that of the source-drain metal layer (SD) in the display area AA; or, its material is the same as that of the gate (Gate) in the display area AA.
  • the material of the wing-shaped wiring 3 when the material of the wing-shaped wiring 3 is the same as that of the source-drain metal layer (SD) in the display area AA, the material of the wing-shaped wiring 3 and the source-drain metal layer (SD) in the display area AA may be the same. SD) Fabrication on the same layer; when the material of the airfoil wiring 3 is the same as that of the gate (Gate) in the display area AA, the airfoil wiring 3 can be fabricated on the same layer as the gate (Gate) in the display area AA.
  • the receiving terminal 41 electrically connected to the airfoil trace 3 includes:
  • the gate layer on the substrate 401 includes two conductive pads 404 that are independent and opposite to each other;
  • the source-drain metal layer 406 covers the dielectric layer 405 and is in direct contact with the exposed part of the conductive pad 404;
  • the electrode layer 407 covering the source-drain metal layer 406 , is configured to be in direct contact with the output terminal 4 of the driver chip.
  • the above gate layer is made of the same material as the gate layer in the display area AA, and is arranged in the same layer, and is prepared in one patterning process.
  • the electrode layer 407 is made of the same material as the pixel electrodes in the display area AA, and is arranged in the same layer, and is prepared in one patterning process.
  • the electrode layer 407 covering the source-drain metal layer 406 means that the orthographic projection of the electrode layer 407 on the substrate covers the orthographic projection of the source-drain metal layer 406 on the substrate, and the orthographic projection area of the electrode layer 407 on the substrate is larger than the orthographic projection area of the source-drain metal layer 406 on the substrate. In this way, the source-drain metal layer 406 can be protected.
  • the receiving terminal 41 further includes a buffer layer 402 on the substrate 401, and a gate insulating layer 403 on the buffer layer 402.
  • the gate insulating layer 403 can also be located on the side of the gate layer away from the substrate 401. On one side, it can be determined according to the design of the actual product, and there is no limitation here.
  • FIG. 24 shows a top structural view of a receiving terminal 41 provided by an embodiment of the present application, wherein FIG. 25 is a cross-sectional view along the B1B2 direction of FIG. 24 .
  • the conductive pad 404 of the receiving terminal 41 is arranged as an integrated block structure and occupies the central area of the receiving terminal 41, in the embodiment of the present application, refer to Fig. 24 and FIG.
  • FIG. 23 is a cross-sectional view along the direction A1A2 of FIG. 22 .
  • each of the wing-shaped wiring 3 electrically connected to the first group of receiving terminals S1 and the wing-shaped wiring 3 electrically connected to the second group of receiving terminals S2 The second airfoil traces 32 are all located at the gate layer, and both pass through the area between the two conductive pads 404 of the receiving terminal 41 .
  • the design method in the embodiment greatly saves the design space of the bonding area and the fan-out area of the display panel while ensuring the normal and stable transmission of electrical signals. Wide to achieve high-frequency charging, on the other hand, is conducive to the preparation of narrow border display products.
  • a wing-shaped trace 3 is electrically connected to its conductive pad 404, and the first group of receiving terminals S1
  • the orthographic projections of other electrically connected airfoil traces 3 on the substrate and the orthographic projections of their conductive pads 404 on the substrate do not overlap each other;
  • one second wing-shaped wiring 32 is electrically connected to its conductive pad 404, and the other second wing-shaped wiring 32 electrically connected to the second group of receiving terminals S2 is on the substrate.
  • the orthographic projections on the bottom and the orthographic projections of the conductive pads 404 on the substrate do not overlap each other.
  • the conductive pad 404 of the receiving terminal 41 is also located at the gate layer, in order to ensure There is no problem of signal transmission disorder between the receiving terminal 41 and each airfoil wiring 3.
  • the display panel further includes a plurality of spare receiving terminals 42, and the spare receiving terminals 42 and the receiving terminals 41 have the same structure;
  • the spare receiving terminal 42 arranged in the same row as the first group of receiving terminals S1 is the first spare receiving terminal, and the spare receiving terminal 42 arranged in the same row as the second group of receiving terminals S2 is the second spare receiving terminal;
  • At least part of the airfoil wiring 3 electrically connected to the first group of receiving terminals passes through the area between the two conductive pads 404 in the first spare terminal, and the airfoil electrically connected to the second group of receiving terminals At least part of the wire 3 passes through the area between the two conductive pads 404 in the second spare terminal.
  • the spare receiving terminal 42 is not electrically connected to the airfoil trace 3 .
  • the specific number of spare receiving terminals (Dummy receiving terminals) 42 in the display panel is not limited here. Exemplarily, the number of spare receiving terminals 42 is 5, wherein, the number of first spare receiving terminals is 2, and the number of second spare receiving terminals is 3.
  • the spare receiving terminals 42 are located at both ends of the plurality of receiving terminals 41; or, as shown in FIG. terminal is located on the left side of the first group of receiving terminals 41, and the second spare receiving terminal is located on the left side of the second group of receiving terminals 41); or, the spare receiving terminal 42 and the receiving terminal 41 are arranged at intervals.
  • the area between the two conductive pads 404 in some receiving terminals 41 is not provided with airfoil traces 3; At least one airfoil trace 3 passes through the area between the two conductive pads 404 .
  • the details can be determined according to the actual situation.
  • the fan-out wiring 2 includes a display fan-out wiring 21 and a touch fan-out wiring 22 ;
  • Each touch fan-out line 22 extends from the fan-out area F to the area where the first side 101 is located, and is electrically connected to the output terminal 4 ; some display fan-out lines 21 are electrically connected to the output terminal through the airfoil line 3 .
  • the display fan-out wires 21 are connected to the output terminal 4 by winding through the airfoil wire 3. so as to facilitate the arrangement of the fan-out wires 2 in the fan-out area F.
  • the display fan-out wires 21 are set to be electrically connected to the output terminal 4 by winding the airfoil wire 3.
  • the touch fan-out wiring 22 is also possible to set the touch fan-out wiring 22 to be electrically connected to the output terminal 4 by winding the airfoil wiring 3.
  • FIG. 15 provided in the embodiment of the present application only shows an example where the airfoil trace 3 passes through the area where the second side 102 is located.
  • the fan-shaped traces electrically connected to this part of the airfoil 3 2.
  • a certain design space is released between the fan-out trace 2 electrically connected to the airfoil trace 3 and the fan-out trace 2 not electrically connected to the airfoil trace 3, and the airfoil trace 3 can be routed from the bonding area B
  • the wire is wound from the area where the first side 101 is located, so that this part of the fan-out wire 2 is electrically connected to the output terminal 4 through the airfoil wire 3 .
  • the wing-shaped wiring 3 electrically connected to the display fan-out wiring 21 may pass through the area where the first side 101 is located and be electrically connected to the output terminal 4 .
  • the fan-out wires 2 can be set to be the display fan-out wires 21, so that the display fan-out wires 21 pass through the area where the second side 102 of the driver chip IC is located, and then connect to the output terminal 4 connection, so that another part of the display fan-out wiring 21 and all the touch fan-out wiring 22 extend from the fan-out area F to the binding area B, pass through the area where the first side is located, and then electrically connect to the output terminal 4 .
  • the fan-out wiring 2 includes a display fan-out wiring 21 and a touch fan-out wiring 22 , and each touch fan-out wiring 22 extends from the fan-out area F to the first side.
  • the area where the side 101 is located is electrically connected to the receiving terminal 41, and the receiving terminal 41 is electrically connected to the output terminal 4 (the structure of the output terminal 4 of the driver chip is not shown in FIG.
  • the wire 3 is electrically connected to the receiving terminal 41 , and the airfoil wire 3 passes through the area where both sides (the third side 103 ) of the driver chip are located.
  • the display fan-out wiring 21 electrically connected to the receiving terminal 41 through the airfoil wiring 3 can be divided into two parts.
  • the first part shows that the wing-shaped wiring 3 electrically connected to the fan-out wiring 21 is located at the gate layer, and this part of the wing-shaped wiring 3 passes through the area between the two conductive pads 404 of the receiving terminal 41, and is connected with the One of the conductive pads 404 of the corresponding receiving terminal 41 is electrically connected.
  • each airfoil trace 3 electrically connected to the fanout trace 21 includes a first airfoil trace 31 and a second airfoil trace 32, and the first airfoil trace 31 and the second airfoil trace 32 Located on different layers, and for each first airfoil-shaped wiring 31, the second airfoil-shaped wiring 32 electrically connected to it overlaps in a direction perpendicular to the substrate, and the extending direction of the overlapping area is the same as
  • the extension directions of the first airfoil traces 31 and the second airfoil traces 32 are parallel, and the second part shows that the second airfoil traces 32 among the airfoil traces 3 electrically connected with the fan-out traces 21 are located at the gate layer , and this part of the second airfoil trace 32 passes through the area between the two conductive pads 404 of the receiving terminal 41 , and is electrically connected to one of the conductive pads 404 of the corresponding receiving terminal 41 .
  • the receiving terminals 41 electrically connected to the airfoil traces 3 can be divided into a first group S1 arranged along the first side 101 and a second group S1 arranged along the second side 102 .
  • each second wing-shaped wiring 32 of the wing-shaped wiring 3 electrically connected to the first group of receiving terminals S1 and the second wing-shaped wiring 3 electrically connected to the second group of receiving terminals S2 is located at the gate layer, and is connected from The area between the two conductive pads 404 of the receiving terminal 41 passes through.
  • each touch fan-out wiring 22 extends from the fan-out area F to the area where the first side 101 is located, and is electrically connected to the receiving terminal 41.
  • the receiving terminal 41 and The output terminal 4 is electrically connected (the structure of the output terminal 4 of the driver chip is not shown in Figure 29); partly shows that the fan-out wiring 21 is electrically connected to the receiving terminal 41 through the wing-shaped wiring 3, and the wing-shaped wiring 3 is connected from the driver The area where the two sides of the chip (third side 103 ) are located passes through.
  • the display fan-out wiring 21 electrically connected to the receiving terminal 41 through the airfoil wiring 3 can be divided into three parts.
  • the first part shows that the fan-out trace 21 is electrically connected to the receiving terminal 41 through the airfoil trace 3 , and the airfoil trace 3 passes through the area where the first side 101 is located.
  • each wing-shaped wiring 3 electrically connected to the fan-out wiring 21 is located at the gate layer, and this part of the wing-shaped wiring 3 passes through the area between the two conductive pads 404 of the receiving terminal 41, and It is electrically connected with one of the conductive pads 404 of the corresponding receiving terminal 41 .
  • each airfoil trace 3 electrically connected with the fanout trace 21 includes a first airfoil trace 31 and a second airfoil trace 32, and the first airfoil trace 31 and the second airfoil trace 32 Located on different layers, and for each first airfoil-shaped wiring 31, the second airfoil-shaped wiring 32 electrically connected to it overlaps in a direction perpendicular to the substrate, and the extending direction of the overlapping area is the same as The extension direction of the first airfoil traces 31 is parallel, and the second part shows that the second airfoil traces 32 among the airfoil traces 3 electrically connected to the fan-out traces 21 are located in the gate layer, and this part of the second airfoil traces
  • the wiring 32 passes through the area between the two conductive pads 404 of the receiving terminal 41 and is electrically connected to one of the conductive pads 404 of the corresponding receiving terminal 41 .
  • each touch fan-out line 22 and part of the display fan-out line 21 can be set to extend from the fan-out area F to the area where the first side 101 is located, and be electrically connected to the output terminal 4, and some It is shown that the fan-out wiring 21 passes through the area where the lower side (second side 102 ) of the driver chip is located through the wing-shaped wiring 3 , and is electrically connected to the output terminal 4 through the area where the input terminal 5 is located.
  • the part shows that the fan-out trace 21 is electrically connected with the receiving terminal 41 through the airfoil trace 3 .
  • the display fan-out line 21 electrically connected to the receiving terminal 41 through the airfoil line 3 is divided into two parts, the first part shows that the fan-out line 21 passes through the airfoil line 3 from the lower side of the drive chip (the second side 102 ) passes through and passes through the area where the input terminal 5 is located to be electrically connected to the output terminal 4 (actually, it is first electrically connected to the receiving terminal 41, and the receiving terminal 41 is electrically connected to the output terminal 4).
  • the second part shows that the wing-shaped wiring 3 connected by the fan-out wiring 21 passes through the area where both sides of the driver chip (third side 103) are located, and passes through the area between the two conductive pads 404 of the receiving terminal 41, and then It is electrically connected to one of the conductive pads 404 of the corresponding receiving terminal 41 , wherein the second part shows that the wing-shaped traces 3 connected to the fan-out traces 21 are located at the gate layer and arranged on the same layer as the conductive pads 404 .
  • the part shows that the fan-out wiring 21 is electrically connected with the output terminal 4 through the airfoil wiring 3 .
  • the display fan-out line 21 electrically connected to the output terminal 4 through the airfoil line 3 is divided into two parts, and the first part shows that the fan-out line 21 passes through the airfoil line 3 from the upper side (first side 101) of the driver chip. The area where it is located passes through and is electrically connected to the output terminal 4.
  • the second part shows that the airfoil traces 3 electrically connected to the fan-out traces 21 include the first airfoil traces 31 and the second airfoil traces 32.
  • the first wing traces The airfoil-shaped traces 31 and the second airfoil-shaped traces 32 are located on different layers, and for each first airfoil-shaped trace 31, the second airfoil-shaped traces 32 electrically connected to it exist along the direction perpendicular to the substrate. overlapping, and the extending direction of the overlapping area is parallel to the extending direction of the first airfoil trace 31 .
  • airfoil traces 3 include display airfoil traces and touch airfoil traces;
  • fanout traces 2 include display fanout traces 21 and touch fanout traces. Exit line 22;
  • Part of the display fan-out wiring 21 is electrically connected to the output terminal 4 through the display airfoil wiring, and part of the touch fan-out wiring 22 is electrically connected to the output terminal 4 through the touch wing-shaped wiring.
  • the receiving terminal 41 is electrically connected to the output terminal 4 (the structure of the output terminal 4 of the driver chip is not shown in Figure 37);
  • the touch fan-out wiring 22 is electrically connected through the touch wing-shaped wiring receiving terminal 41 .
  • the airfoil traces 3 (including the display airfoil traces and the touch airfoil traces) pass through the area where both sides of the driver chip (the third side 103 ) are located.
  • part of the touch fan-out wiring 22 and part of the display fan-out wiring 21 can be set to extend from the fan-out area F to the area where the first side 101 is located, and be electrically connected to the output terminal 4;
  • a part of the display fan-out wiring 21 passes through the area where the lower side (second side 102) of the driver chip is located through the display airfoil wiring, and passes through the area where the input terminal 5 is located to be electrically connected to the output terminal 4, and the other part contacts the output terminal 4.
  • the fan-out control wiring 22 passes through the area where the lower side (second side 102 ) of the driver chip is located through the touch wing-shaped wiring, and is electrically connected to the output terminal 4 through the area where the input terminal 5 is located.
  • part of the touch fan-out wiring 22 and part of the display fan-out wiring 21 are set to extend from the fan-out area F to the area where the first side 101 is located, and are connected to the output terminal 4 Electrical connection; another part of the display fan-out wiring 21 is electrically connected to the output terminal 4 through the display wing-shaped wiring, and another part of the touch fan-out wiring 22 is electrically connected to the output terminal 4 through the touch wing-shaped wiring.
  • the display fan-out trace 21 electrically connected to the output terminal 4 through the display airfoil trace (the airfoil trace 3 electrically connected to the display fan-out trace 21) is divided into two parts, and the first part shows that the fan-out trace 21 passes through the display
  • the wing-shaped wiring passes through the area where the upper side (first side 101) of the driver chip is located and is electrically connected to the output terminal 4.
  • the second part shows that each display wing-shaped wiring electrically connected to the fan-out wiring 21 includes the first wing
  • the first wing-shaped wiring 31 and the second airfoil-shaped wiring 32 are located on different layers, and for each first airfoil-shaped wiring 31, the first airfoil-shaped wiring 31 is electrically connected to it.
  • the two airfoil traces 32 overlap along a direction perpendicular to the substrate, and the extending direction of the overlapping area is parallel to the extending direction of the first airfoil trace 31 .
  • the touch fan-out wire 22 electrically connected to the output terminal 4 through the touch airfoil wire (the airfoil wire 3 electrically connected to the touch fan-out wire 22 ) is also divided into two parts, the first part of the touch fan-out wire 22 passes through the area where the upper side of the driver chip (the first side 101 ) is located through the touch airfoil wiring and is electrically connected to the output terminal 4, and the second part of the touch fan-out wiring 22 is electrically connected to each touch airfoil
  • the wiring also includes a first airfoil wiring 31 and a second airfoil wiring 32, the first airfoil wiring 31 and the second airfoil wiring 32 are located on different layers, and for each first airfoil wiring 31 , the second airfoil traces 32 electrically connected thereto overlap in a direction perpendicular to the substrate, and the extending direction of the overlapping region is parallel to the extending direction of the first airfoil traces 31 .
  • the airfoil traces 3 may be located in the same layer.
  • the wing-shaped wiring 3 When the material of the wing-shaped wiring 3 is the same as that of the source-drain metal layer (SD) in the display area AA, the wing-shaped wiring 3 can be made on the same layer as the source-drain metal layer (SD) in the display area AA; When the material of the wing-shaped wiring 3 is the same as that of the gate (Gate) in the display area AA, the material of the wing-shaped wiring 3 and the gate (Gate) in the display area AA can be made on the same layer.
  • FIG. 7 is an enlarged schematic diagram of a local area of FIG. 6 .
  • part of the airfoil traces 3 are arranged on the same layer, and another part of the airfoil traces 3 includes a first airfoil trace 31 and a second airfoil trace 32 , and The first airfoil wiring 31 and the second airfoil wiring 32 are located on different layers;
  • the airfoil traces 3 arranged on the same layer include the first line segment a, the second line segment b, the third line segment c, the fourth line segment d and the fifth line segment e connected in sequence, wherein the first line segment a and the second line segment b are located in the binding area B, the third line segment c extends from the binding area B to the fan-out area F, the fourth line segment d and the fifth line segment e are located in the fan-out area F; the first line segment a and the fan-out area go The line 2 is electrically connected, and the fifth line segment e is electrically connected to the output terminal 4 .
  • the arrangement order of the fan-out wiring 2 electrically connected to the first line segment a, the arrangement order of the first line segment a, the arrangement order of the fifth line segment e, and the output terminal 4 electrically connected to the fifth line segment e The arrangement sequence of the fan-out lines 2 is the same, so as to ensure that each fan-out line 2 is electrically connected to the output terminal 4 corresponding to the signal, thereby avoiding the problem of signal confusion.
  • the fan-out trace 2 since part of the fan-out trace 2 is electrically connected to the output terminal 4 of the driver chip after being wound from the bonding area B through the airfoil trace 3, in the fan-out area F, it is electrically connected to the airfoil trace 3 There is an available space F1 between the connected fan-out trace 2 and the fan-out trace 2 that is not electrically connected to the airfoil trace 3, so that the airfoil trace 3 extends from the bonding area B to F1 as shown in Figure 18 , and then pass through the area where the first side 101 of the driver chip is located, and be electrically connected to the output terminal 4 . In this way, more fan-out traces 2 can be arranged to be electrically connected to the output terminal 4 by winding the wing-shaped trace 3 , thereby reducing the design space of the fan-out area F and the bonding area B.
  • the second airfoil traces 32 are located on different layers.
  • the first wing-shaped wiring 31 when the material of the first wing-shaped wiring 31 is the same as that of the source-drain metal layer (SD) in the display area AA, the first wing-shaped wiring 31 can be the same as the material of the source-drain metal layer (SD) in the display area AA. ) on the same layer; when the material of the second airfoil wiring 32 is the same as that of the grid (Gate) in the display area AA, the second airfoil wiring 32 can be on the same layer as the grid (Gate) in the display area AA make.
  • the first airfoil wiring 31 can be fabricated on the same layer as the grid (Gate) in the display area AA;
  • the second wing-shaped wiring 32 can be on the same layer as the source-drain metal layer (SD) in the display area AA make.
  • the first airfoil routing 31 extends along the first direction AF
  • the second airfoil routing 32 includes a first line segment 321 extending along the second direction FA; the first airfoil routing 31 and the fan-out routing 2 respectively It is electrically connected to the first line segment 321;
  • the first direction AF is the direction in which the display area AA points to the binding area B, and the second direction FA is parallel to the first direction AF;
  • the orthographic projection of the first line segment 321 on the substrate of the display panel overlaps with the orthographic projection of the first airfoil trace 31 electrically connected thereto on the substrate.
  • the orthographic projection of the first line segment 321 on the substrate of the display panel is located
  • the connected first airfoil trace 31 is within the orthographic projection on the substrate.
  • the projection overlaps, extending the distance between the fan-out trace 2 electrically connected to the airfoil trace 3 and the output terminal 4, so that the fan-out trace 2 electrically connected to the airfoil trace 3 can be offset to a certain extent
  • the shortened length improves the resistance matching between different traces, thereby improving the stability of signal transmission.
  • the second airfoil routing 32 further includes a second line segment 322 and a third line segment 323 , the second line segment 322 extends along the third direction MN, and the first line segment 321 1.
  • the second line segment 322 is connected to the third line segment 323 in sequence, and the third line segment 323 is electrically connected to the output terminal 4; the third direction MN intersects the first direction AF;
  • each first airfoil trace 31 is the same.
  • Line 31 and the fifth first airfoil routing 31 are arranged in sequence along the third direction MN; the first first line segment 321, the second first line segment 321, the third first line segment 321, the first The four first line segments 321 and the fifth first line segment 321 are arranged in sequence along the third direction MN; the first third line segment 323, the second third line segment 323, the third third line segment 323, the third line segment The four third line segments 323 and the fifth third line segment 323 are sequentially arranged along the third direction MN.
  • the angle formed after the intersection of the third direction and the first direction may be a right angle, or the angle formed after the intersection of the third direction and the first direction may be an obtuse angle.
  • the third direction MN marked in the drawings provided in the embodiments of the present application is drawn as an example by taking the angle between the third direction MN and the first direction AF as a right angle after intersection.
  • the order adjustment between the airfoil trace 3 and the output terminal 4 is realized, so that the fan-out trace 2 is electrically connected to the corresponding output terminal 4, and there is no need for a driver chip to be connected to each output terminal 4. Adjust the output signal sequence in terminal 4.
  • the jumper design shown in FIG. 8 can also be used.
  • the winding on the left side (the third side) is shown as an example.
  • the angle between the extension line of the first line segment 321 and the extension line of the second line segment 322 is a right angle
  • the extension line of the second line segment 322 and the third line segment is a right angle
  • the angle between the extension line of the first line segment 321 and the extension line of the second line segment 322 is an obtuse angle
  • the angle between the extension line of the second line segment 322 and the extension line of the third line segment 323 The included angle is an obtuse angle, and the angles of the two obtuse angles are the same;
  • one of the angles between the extension line of the first line segment and the extension line of the second line segment and the angle between the extension line of the second line segment and the extension line of the third line segment is a right angle, and the other is obtuse angle.
  • the first line segment 321 of the second airfoil trace 32 on the substrate partially overlaps the orthographic projection of the first airfoil trace 32 connected to it on the substrate, so , the first line segment 321 can extend the distance between the fan-out trace 2 electrically connected to the airfoil trace 3 and the output terminal 4, so as to offset the fan-out trace electrically connected to the airfoil trace 3 to a certain extent.
  • the shortened length of the line 2 improves the resistance matching between different lines, thereby improving the stability of signal transmission. In practical applications, the lengths of the traces that need to be offset are different.
  • the first line segment 321 and the second line segment 322 can be set to be perpendicular, or the angle between the first line segment 321 and the second line segment 322 can be set to be an obtuse angle.
  • each airfoil trace 3 is arranged on the same layer
  • the airfoil traces 3 arranged on the same layer include the first line segment a, the second line segment b, the third line segment c, the fourth line segment d and the fifth line segment e connected in sequence, wherein the first line segment a and the second line segment b are located in the binding area B, the third line segment c extends from the binding area B to the fan-out area F, the fourth line segment d and the fifth line segment e are located in the fan-out area F; the first line segment a and the fan-out area go Line 2 is electrically connected, the fifth line segment e is electrically connected to output terminal 4, and the angle between the extension line of the second line segment b and the extension line of the third line segment c is a right angle, the extension line of the third line segment c and the fourth line segment
  • the angle between the extensions of the line segment d is a right angle; or, the angle between the extension of the second line segment b and the extension of the third line segment c is an obtuse angle, the extension
  • each touch fan-out wire 22 extends from the fan-out area F to the area where the first side 101 is located, and is electrically connected to the receiving terminal 41, and the receiving terminal 41 is electrically connected to the output terminal 4;
  • a part shows that the fan-out wiring 21 is electrically connected to the receiving terminal 41 through the wing-shaped wiring 3 , and the wing-shaped wiring 3 passes through the area where both sides of the driver chip (the third side 103 ) are located.
  • the display fan-out wiring 21 electrically connected to the receiving terminal 41 through the airfoil wiring 3 can be divided into three parts.
  • the first part shows that the fan-out trace 21 is electrically connected to the receiving terminal 41 through the airfoil trace 3, and the airfoil trace 3 passes through the area where the first side 101 is located.
  • the airfoil routing 3 passing through the area where the edge 101 is located can be divided into three sections, wherein the included angle between the first section and the second section is equal to the included angle between the second section and the third section.
  • the second airfoil routing 32 includes a first line segment 321 , a second line segment 322 and a third line segment 323 connected in sequence;
  • a first corner G is provided between the first line segment 321 and the second line segment 322, and a second corner (not drawn in FIG. 36 ) is provided between the second line segment 322 and the third line segment 323;
  • At least some of the corners are rounded.
  • Fig. 36 is a partially enlarged view of the area where the first line segment 321 and the second line segment 322 are located in Fig. 8, and Fig. 36 provides a schematic structural diagram of the first corner, and the structure of the second corner is similar to that of the first corner ,No longer.
  • each corner is rounded means: a portion of each first corner is rounded; or, each first corner is rounded; or, each second corner is rounded.
  • the portion of is rounded; or, each second corner is rounded; or, each first corner and second corner is rounded.
  • each corner can also be a right angle, which can be determined according to the actual situation.
  • At least one island-shaped figure D is provided between two adjacent first corners G, and each island-shaped figure D between two adjacent first corners G Not connected to each other;
  • At least one island-shaped figure is arranged between two adjacent second corners, and the island-shaped figures between two adjacent second corners are not connected to each other.
  • the meaning of the island-shaped figure is that the figure is not connected to other structures around the area where it is located, and the figure is set independently.
  • the island-shaped pattern is made of the same material as the source-drain metal layer, or the same material as the gate layer, the island-shaped pattern can have conductivity, but it is not compatible with Any other traces or signal lines are electrically connected.
  • At least one island-shaped figure is arranged between two adjacent first corners, and the island-shaped figures between two adjacent first corners are not connected to each other; or, two adjacent first corners At least one island-shaped figure is set between two corners, and the island-shaped figures between two adjacent second corners are not connected to each other; or, at least one island-shaped figure is set between two adjacent first corners, and the The island-shaped figures between two adjacent first corners are not connected to each other, and at least one island-shaped figure is arranged between two adjacent second corners, and the island-shaped figures between two adjacent second corners are mutually connected. not connected.
  • the number of island-shaped figures D between two adjacent first corners is not completely the same, or the number of island-shaped figures D between two adjacent first corners is completely the same.
  • FIG. 36 it is drawn as an example that the number of island-shaped figures D between two adjacent first corners is not exactly the same. It should be noted that the number of island-shaped figures D between two adjacent first corners is not exactly the same meaning: for some first corners, the number of island-shaped figures D between two adjacent first corners The same; for another part of the first corners, the number of island-shaped figures D between two adjacent first corners is different.
  • the number of island-shaped figures D between two adjacent second corners there is no limitation on the number of island-shaped figures D between two adjacent second corners.
  • the number of island-shaped figures D between two adjacent first corners is not completely the same, or the number of island-shaped figures D between two adjacent first corners is completely the same.
  • the number of island-shaped figures D between two adjacent first corners may be the same as the number of island-shaped figures D between two adjacent second corners, or, the number of island-shaped figures D between two adjacent first corners The number of island-shaped figures D may be different from the number of island-shaped figures D between two adjacent second corners.
  • the specific shape and size of the island-shaped figure D between two adjacent first corners are not limited here.
  • the specific shape and size of the island-shaped figure D between two adjacent second corners are not limited here.
  • the shape of the island-shaped figure D between two adjacent first corners can be set to be the same as the shape of the island-shaped figure D between two adjacent second corners.
  • the projection shape of the island figure D between two adjacent first corners on the substrate is arc, polygon, or a shape formed by a combination of arc and polygon.
  • the arc may include sector, semicircle, semiellipse, circle and ellipse.
  • Polygons may include triangles, quadrilaterals, pentagons or hexagons.
  • the projected shape of the island-shaped figure D between two adjacent second corners on the substrate is the same as the projected shape of the island-shaped figure D between two adjacent first corners on the substrate.
  • the third line segment 323) is arranged on the same layer, and the second airfoil trace 32 and the first airfoil trace 31 are located on different layers.
  • the island pattern can be located on the same layer as the gate layer; alternatively, the island pattern can be located on the same layer as the source-drain metal layer. Specifically, it may be determined according to data conditions, and no limitation is imposed here.
  • the island pattern D and the second airfoil trace 32 may be disconnected.
  • each island pattern D between two adjacent first corners does not completely intersect with the first airfoil trace 31 along the direction perpendicular to the substrate. overlapping area.
  • the orthographic profile of the first line segment 321 on the substrate is located within the orthographic profile of the first airfoil trace 31 on the substrate.
  • the orthographic projection of at least part of the island-shaped figure D between two adjacent first corners on the substrate may partially overlap with the orthographic projection of the first airfoil trace 31 on the substrate.
  • the orthographic profile of the first line segment 321 on the substrate overlaps with the orthographic profile of the first airfoil trace 31 on the substrate.
  • the orthographic projection of at least part of the island-shaped figure D between two adjacent first corners on the substrate and the orthographic projection of the first airfoil trace 31 on the substrate do not overlap each other.
  • the stability of the manufacturing process can be improved, and the first corner can be improved. and linewidth uniformity of traces near the second corner.
  • every two first line segments 321 are divided into one group, and each group of first line segment routing groups (G1, G2, G3, G4 or G5 ) includes the outer first line segment W and the inner first line segment N arranged along the third direction MN; wherein, for each group of first line segment wiring groups, the second line segment 322 electrically connected to the outer first line segment W.
  • the orthographic projection on the substrate and the orthographic projection on the substrate of the second line segment 322 electrically connected to the inner first line segment N overlap.
  • the airfoil traces 3 are respectively arranged on three conductive film layers. Specifically, as shown in FIG. 9 , the first airfoil traces 31 and the second airfoil traces 32 are located on different layers. The second airfoil traces 32 respectively corresponding to the outer first line segment W and the inner first line segment N in each group of first line segment routing groups are located in different layers.
  • the first airfoil trace 31 is made of the same material as the gate (Gate) in the display area AA, that is, the first airfoil trace 31 and the gate layer are arranged on the same layer; a part of the second airfoil trace 32 adopts the same material as the source-drain metal layer (SD) in the display area AA, and another part of the second airfoil wiring 32 adopts the same material as the light-shielding layer (LS) in the display area AA, that is, a part of the second airfoil The wiring 32 is arranged on the same layer as the source-drain metal layer, and another part of the second wing-shaped wiring 32 is arranged on the same layer as the light-shielding layer.
  • SD source-drain metal layer
  • LS light-shielding layer
  • molybdenum (Mo) in a single layer structure molybdenum/aluminum/molybdenum (Mo/Al/Mo) in a stacked structure, titanium/aluminum/titanium (Ti/Al/ Ti), molybdenum-niobium/copper (MoNb/Cu) with a double-layer structure, molybdenum-niobium-titanium/copper (MoNiTi/Cu) with a double-layer structure, or titanium/copper (Ti/Cu) with a double-layer structure as the gate layer.
  • the thickness range of the gate layer along the direction perpendicular to the substrate may be For example: the thickness of each sublayer of molybdenum/aluminum/molybdenum (Mo/Al/Mo) in the laminated structure is 200A/3000A/200A; the thickness of each sublayer of titanium/aluminum/titanium (Ti/Al/Ti) in the laminated structure The thickness of the layer is 150/4000/200A; the thickness of the two sublayers of molybdenum-niobium-titanium/copper (MoNiTi/Cu) of the double-layer structure is 200A/4000A.
  • molybdenum (Mo) in a single layer structure molybdenum/aluminum/molybdenum (Mo/Al/Mo) in a stacked structure, titanium/aluminum/titanium (Ti/Al/ Ti), double-layer molybdenum-niobium/copper (MoNb/Cu), double-layer molybdenum-niobium-titanium/copper (MoNiTi/Cu) or double-layer titanium/copper (Ti/Cu) Source-drain metal layer (SD).
  • the thickness range of the source-drain metal layer (SD) along the direction perpendicular to the substrate can be
  • the light-shielding layer can adopt a double-layer structure of aluminum/molybdenum metal layer (Al/Mo), a single-layer structure of molybdenum metal layer (Mo), a single-layer structure of molybdenum-niobium metal layer (MoNb) or Titanium metal layer metal preparation of single layer structure, its thickness range can be
  • the airfoil wiring 3 is wound from the right side (the other third side 103) and the lower side (the second side 102) of the driver chip, the first outer line segment W can also be set.
  • the orthographic projection of the connected second line segment 322 on the substrate overlaps with the orthographic projection of the second line segment 322 electrically connected to the inner first line segment N on the substrate.
  • the left winding of the driver chip is taken as an example for illustration.
  • the orthographic projection of the second line segment 322 electrically connected to the outer first line segment W on the substrate is electrically connected to the inner first line segment N.
  • the overlapping of the orthographic projections of the second line segment 322 on the substrate can greatly reduce the height H of the area occupied by each second airfoil trace 32 along the first direction AF, so that it can be largely increase the design space.
  • the line width of the second airfoil wiring 32 and the distance between two adjacent second airfoil wiring 32 can greatly reduce the distance between the second airfoil wiring 32 itself. Resistors, so that high-frequency charging of each pixel unit in the display area AA can be realized, the charging rate of the display panel can be improved, the charging time can be shortened, and the power consumption of the display panel can be reduced.
  • the height H of the area occupied by the second airfoil trace 32 along the first direction AF is relatively small, more fan-out traces 2 can be arranged to connect with the output terminal 4 by winding the airfoil trace 3 . Electrical connection, thereby shortening the length of each fan-out trace 2 electrically connected with the airfoil trace 3, thereby further reducing the space occupied by the fan-out trace 2 in the fan-out area B. Further, as the number of fan-out wires 2 electrically connected to the output terminal 4 through the airfoil wire 3 increases, the fan-out area F can be further reduced along the display area AA to the fan-out area F The size in the direction is more conducive to the preparation of a display panel with a narrow frame.
  • the display panel includes a test unit CT and a plurality of test connection wires 6;
  • test unit CT is located on the side where each output terminal 4 is located away from the display area AA; the test connection wiring 6 is configured to connect the test unit CT and the output terminal 4;
  • the output terminal 4 electrically connected to the airfoil trace 3 is directly electrically connected to the test connection trace 6 .
  • the above test unit CT includes at least one of a display test unit Data CT and a touch test unit VCOM CT.
  • the above-mentioned test unit CT may include a display test unit Data CT; or, the above-mentioned test unit CT may include a touch test unit VCOM CT; or, the above-mentioned test unit CT includes a display test unit Data CT and a touch test unit VCOM CT. .
  • the output terminals 4 are not only connected to a wing-shaped wiring 3, but also connected to a test connection wiring 6, and the wing-shaped wiring 3 electrically connected to the same output terminal 4 is connected to the substrate
  • the orthographic projection on the substrate overlaps with the orthographic projection of the test connection trace 6 on the substrate.
  • test connection wiring 6 and the wing-shaped wiring 3 can be arranged on different layers, thereby saving the design space between the area where the output terminal 4 is located and the area where the test unit CT is located.
  • the display panel includes a test unit CT, and the test unit CT is divided into a display test unit Data CT and a touch test unit VCOM CT; a display test unit Data CT and a touch test unit At least one of the VCOM CTs is located on the side of the display area AA away from the fan-out area F, and the remaining one is located in the fan-out area F or the binding area B.
  • both the display test unit Data CT and the touch test unit VCOM CT can be arranged on the side of the display area AA away from the fan-out area F.
  • one of the display test unit Data CT and the touch test unit VCOM CT can be set on the side of the display area AA away from the fan-out area F, and the other can be set in the fan-out area F or the binding area B.
  • the display test unit Data CT or the touch test unit VCOM CT when the display test unit Data CT or the touch test unit VCOM CT is located in the fan-out area F, the display test unit Data CT or the touch test unit VCOM CT can be located between the driver chip IC and the MUX circuit.
  • the MUX circuit is used to electrically connect the signal line in the display area AA with the fan-out line 2 in the fan-out area F.
  • the specific content related to the MUX circuit can refer to related technologies, and will not be repeated here. .
  • the display test unit Data CT or the touch test unit VCOM CT can be located in the area where the driver chip IC is located, and the test unit is located on the substrate.
  • the projection overlaps with the orthographic projection of the driver chip IC on the substrate; or, the display test unit Data CT or the touch test unit VCOM CT can be located in any area in the binding area B except the area where the driver chip IC is located.
  • the binding area B or the fan-out area can be released to a large extent.
  • the design space of the area F so that space can be provided to increase the line width of the wiring in the bonding area B or the fan-out area F, and increase the distance between two adjacent wirings, thereby reducing the resistance of the wiring itself , which is beneficial to realizing high-frequency charging of the display panel, improving charging efficiency, shortening charging time, and reducing power consumption.
  • the area on the side of the display area AA away from the fan-out area F includes a central area and two corner areas R located on both sides of the central area; a display test unit Data CT and a touch test unit VCOM CT Each includes a plurality of test subunits T, and the projection shape of the test subunit T on the substrate is a rectangle;
  • each test subunit T of the corner area R is arranged around the edge of the display area AA; as shown in FIG. 11, the long sides of the rectangles in the corner area R are parallel; or, as shown in FIG. An included angle of a preset angle exists between the long sides of two adjacent rectangles.
  • the aforementioned preset angle may be an acute angle.
  • the included angles between the long sides of every two adjacent rectangles are the same.
  • the above-mentioned test subunit T can be a test pad (PAD); or, the above-mentioned test subunit T can be a switching transistor (STFT); or, part of the test subunit T is a test pad, and another part of the test subunit T is switching transistor.
  • PAD test pad
  • STFT switching transistor
  • the projection shape of the test subunit T on the substrate is a rectangle, where the rectangle can be understood as a standard rectangle; or, it can also be a rectangle with rounded corners.
  • the display panel includes a plurality of first signal adjustment lines 11, and the first signal adjustment lines 11 are located between the fan-out line 2 and the airfoil line 3;
  • the arrangement order of each fan-out routing 2 is different from the arrangement order of each airfoil routing 3;
  • the sequence is the same as the arrangement sequence of each fan-out routing 2, and the arrangement sequence of one end END2 of each first signal adjustment line 11 connected to the airfoil routing 3 is the same as that of each airfoil routing 3;
  • the third direction MN intersects the first direction AF.
  • the arrangement order of multiple airfoil traces 3 in area B is inconsistent.
  • the first signal is set between fanout trace 2 and airfoil trace 3.
  • the adjustment line 11 is designed through the jumper of the first signal adjustment line 11, so that the fan-out line 2 is electrically connected to the airfoil line 3 that is consistent with the signal to be transmitted.
  • the wires located in the fan-out area F are electrically connected to the airfoil wiring 3
  • the arrangement order of the fanout trace 2 and the arrangement order of the airfoil trace 3 located in the binding area B are more obvious.
  • the order of the signals is consistent, and by setting a plurality of first signal adjustment lines 11, the fan-out line 2 is electrically connected to the airfoil line 3 that is consistent with the signal to be transmitted.
  • the arrangement order of the plurality of fan-out traces 2 electrically connected to the airfoil trace 3 is as follows: the second fan-out trace 2, the third fan-out trace 2, and the first fan-out trace.
  • Airfoil routing 3 is electrically connected to fan-out routing 2
  • the order of one end of the airfoil is as follows: the first airfoil trace 3, the second airfoil trace 3, the third airfoil trace 3... Obviously, the positions of the fan-out trace 2 and the airfoil trace 3
  • the arrangement order is inconsistent.
  • the arrangement order of the first signal adjustment line 11 and the end END1 electrically connected to the fan-out line 2 is the same as the arrangement order of the fan-out line 2.
  • the arrangement order of one end END2 of a signal adjustment line 11 connected to the airfoil line 3 is the same as that of the airfoil line 3 , so that the order of the line positions is inconsistent, but the order of the signals to be transmitted is consistent.
  • the airfoil traces 3 and the fanout traces 2 are not drawn in FIG. 13 , and only the two ends of the first signal adjustment line 11 are marked to indicate the arrangement sequence of the airfoil traces 3 and the fanout traces 2. digital markers.
  • the arrangement order of each fan-out routing 2 is different from the arrangement order of each output terminal 4;
  • the arrangement order of each fan-out routing 2 is the same, and the arrangement order of one end END2 of each second signal adjustment line 12 connected to the output terminal 4 is the same as that of each output terminal 4; the third direction MN and the first direction AF intersect.
  • the fan-out trace 2 electrically connected to the output terminal 4 (part of the fan-out trace 2 not electrically connected to the airfoil trace 3), the fan-out trace electrically connected to the output terminal 4 located in the fan-out area F
  • the arrangement order of the outgoing trace 2 is inconsistent with the arrangement sequence of the output terminal 4 located in the binding area B.
  • the fan-out trace 2 and the A plurality of second signal adjustment lines 12 are arranged between the output terminals 4 , and through the jumper design of the plurality of second signal adjustment lines 12 , the fan-out routing 2 is electrically connected to the output terminal 4 that is consistent with the signal to be transmitted.
  • the arrangement order of the plurality of fan-out traces 2 electrically connected to the output terminal 4 is as follows: the second fan-out trace 2, the third fan-out trace 2, and the first fan-out trace.
  • Line 2 the 5th fan-out line 2, the 6th fan-out line 2, the 4th fan-out line 2, the 9th fan-out line 2...
  • the arrangement order of the output terminal 4 is: the first output terminal 4.
  • the second output terminal 4, the third output terminal 4 is inconsistent, and the second signal adjustment line 12 is set between the two, so that the first The arrangement sequence of the end END1 of the second signal adjustment line 12 electrically connected to the fan-out line 2 is the same as that of the fan-out line 2, and the arrangement order of the end END2 of the second signal adjustment line 12 connected to the output terminal 4 is the same as that of the output terminal. 4 are arranged in the same order, so that the positions of the fan-out wiring 2 and the output terminal 4 are not in the same order, but the order of the signals to be transmitted is the same. It should be noted that, in FIG. 13 , the output terminal 4 and the fan-out line 2 are not drawn, and only numbers indicating the arrangement order of the output terminal 4 and the fan-out line 2 are marked on both ends of the second signal adjustment line 12 .
  • At least part of the line segments of each first airfoil routing 31 is a serpentine structure.
  • part of the line segment of the first airfoil line 31 may be a serpentine structure; or, it may be a whole first airfoil line 31 It is a serpentine structure.
  • the above-mentioned serpentine structure may be formed by connecting multiple curved line segments; or, the above-mentioned serpentine structure may be formed by connecting multiple broken-line line segments.
  • the trace between the fan-out trace 2 electrically connected to the airfoil trace 3 and the output terminal 4 is extended.
  • the distance between the wires can offset the shortened length of the fan-out trace 2 electrically connected to the airfoil trace 3 to a certain extent, and the resistance matching between different traces is improved, thereby improving the stability of signal transmission and improving the Brightness uniformity of the display panel.
  • the material of part of the fan-out lines 2 is the first conductive material, and the material of another part of the fan-out lines 2 is the second conductive material, and the resistance of the first conductive material is greater than the resistance of the second conductive material ;
  • each fan-out trace 2 made of a first conductive material is electrically connected to the first airfoil trace 3
  • a part of each fan-out trace 2 made of a second conductive material is electrically connected to the first airfoil trace 3.
  • Connection; wherein, the first airfoil trace 3 electrically connected to the fan-out trace 2 made of the first conductive material is a serpentine structure.
  • a part of the fan-out wiring 2 is prepared on the same layer as the source-drain metal layer in the display area AA, and the material is the same, for example, the material is aluminum (Al); another part of the fan-out wiring 2 and the display area AA
  • the gate lines in the region AA are made in the same layer and made of the same material, for example, the material is all molybdenum (Mo).
  • the resistance of the part of the fan-out wiring 2 prepared on the same layer as the gate line in the display area AA is relatively large.
  • the fan-out wiring 2 prepared on the same layer as the gate line in the display area AA there is a fan-out wiring 2 electrically connected to the output terminal 4 through the wing-shaped wiring 3; the same as the source-drain metal layer in the display area AA
  • the fan-out traces 2 prepared in layers there are also fan-out traces 2 electrically connected to the output terminal 4 through the airfoil traces 3 . Since the resistance of some fan-out traces 2 prepared on the same layer as the gate lines in the display area AA is relatively large, and the influence of the difference in trace length on the resistance is superimposed, this part of the fan-out traces 2 is different from other fan-out traces 2. The difference in resistance is greater.
  • At least part of the line segment of the first airfoil line 3 electrically connected to the high-resistance fan-out line 2 is set as a serpentine structure.
  • the resistance matching between different lines is improved. Therefore, the stability of signal transmission is improved, and the brightness uniformity of the display panel is improved; on the other hand, the problem of increasing the difficulty of the manufacturing process caused by setting at least part of the line segments of all the first airfoil traces 3 in a serpentine structure is avoided.
  • the driver chip IC further includes a plurality of input terminals 5, and each input terminal 5 is arranged along the extending direction of the second side 102;
  • the orthographic projection of the airfoil trace 3 on the substrate of the display panel and the orthographic projection of the input terminal 5 on the substrate do not overlap each other.
  • the distances from the output terminals 4 to the second side 102 along the extending direction parallel to the third side 103 are not completely the same.
  • the distance between the output terminals 4 close to both sides of the driver chip and the output terminal 5 along the extension direction parallel to the third side 103 is greater than that of the output terminals in the middle position. 4 is the distance from the output terminal 5 along the extending direction parallel to the third side 103 .
  • the airfoil trace 3 is usually arranged from the second side 102 of the driver chip. The area passes through and is then electrically connected to the output terminal 4.
  • the fan-out routing 2 includes a connected first fan-out segment 201 and a second fan-out segment 202, the first fan-out segment 201 and the display area AA
  • the signal line is electrically connected
  • the second fan-out section 202 is electrically connected to the output terminal 4;
  • the sine value of the preset included angle is equal to the ratio of the width d5 of the area occupied by all the second fan-out segments 202 along the direction perpendicular to its extension to half the width d6 of the display area AA along the direction parallel to the first side 101 .
  • each fan-out routing 2 has a first inflection point and a second inflection point, and the connection of the first inflection points of all fan-out routings 2 is the first line segment L1
  • the line connecting the second inflection points of each fan-out line 2 electrically connected to the airfoil line 3 is the second line segment L2
  • the line connecting the second inflection points of the fan-out lines 2 not electrically connected to the airfoil line 3 is The third line segment L3, wherein the first line segment L1 is parallel to the second line segment L2, and the second line segment L2 is parallel to the third line segment L3.
  • An embodiment of the present application provides a display device, including the above display panel.
  • the display device may be a touch display panel, and any product or component with a display function, such as a TV, a digital camera, a mobile phone, a tablet computer, etc. including these touch display panels.
  • a plurality of airfoil traces 3 are arranged in the binding area B, and through the airfoil traces 3 from the binding area B (including the left and right sides and the lower side of the driver chip)
  • the way of winding makes part of the fan-out wiring 2 electrically connected to the output terminal 4 of the driver chip through the airfoil wiring 3, thereby utilizing the area where the driver chip is not set in the binding area B, and shortening the electrical connection of the airfoil wiring 3.
  • the length of the connected fan-out trace 2 greatly reduces the space occupied by the fan-out trace 2 in the fan-out area B.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供了一种显示面板及显示装置，涉及显示技术领域，显示面板包括显示区；扇出区；位于扇出区远离显示区一侧的绑定区；绑定区中设置有驱动芯片，驱动芯片包括与扇出区相邻的第一侧边、与第一侧边相对的第二侧边、连接第一侧边和第二侧边的两个第三侧边；驱动芯片还包括多个输出端子，输出端子靠近第一侧边设置；显示面板包括：位于扇出区的多条扇出走线；位于绑定区的多条翼型走线；其中，部分扇出走线从扇出区延伸至第一侧边所在的区域，并与输出端子电连接；另一部分扇出走线通过翼型走线与输出端子电连接，且翼型走线从第一侧边、两个第三侧边和第二侧边中的至少一个侧边所在的区域穿过。该显示面板的设计空间大，功耗低。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的快速发展，人们对显示产品的性能要求越来越高，然而，由于当前显示产品的扇出区的设计空间有限，扇出区中的扇出走线排布非常密集，且扇出走线的线宽较窄，使得扇出走线的电阻较大，难以实现显示产品的高频充电。
目前，亟需一种新的显示面板，以解决上述问题。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种显示面板，包括：
显示区；
位于所述显示区一侧的扇出区；
位于所述扇出区远离所述显示区一侧的绑定区；所述绑定区中设置有驱动芯片，所述驱动芯片包括与所述扇出区相邻的第一侧边、与所述第一侧边相对的第二侧边、连接所述第一侧边和所述第二侧边的两个第三侧边；所述驱动芯片还包括多个输出端子，所述输出端子靠近所述第一侧边设置；
所述显示面板包括：
位于所述扇出区的多条扇出走线；
至少位于所述绑定区的多条翼型走线；
其中，部分所述扇出走线从所述扇出区延伸至所述第一侧边所在的区域，并与所述输出端子电连接；另一部分所述扇出走线通过所述翼型走线与所述输出端子电连接，且所述翼型走线从所述第一侧边、两个所述第三侧边和所述第二侧边中的至少一个侧边所在的区域穿过。
在本申请的一些实施例中，所述翼型走线从所述第一侧边所在的区域穿过。
在本申请的一些实施例中，所述翼型走线从所述第二侧边所在的区域穿过。
在本申请的一些实施例中，部分所述翼型走线从所述第二侧边所在的区域穿过，另一部分所述翼型走线从两个所述第三侧边中的至少一个侧边所在的区域穿过。
在本申请的一些实施例中，部分所述翼型走线从所述第一侧边所在的区域穿过，另一部分所述翼型走线从两个所述第三侧边中的至少一个侧边所在的区域穿过。
在本申请的一些实施例中，所述显示面板还包括多个接收端子，所述接收端子被配置为与所述驱动芯片的所述输出端子绑定在一起；所述接收端子在所述显示面板的衬底上的正投影和所述输出端子在所述衬底上的正投影交叠；部分所述接收端子和穿过所述第一侧边所在的区域的所述扇出走线电连接，另一部分所述接收端子和所述翼型走线电连接；
其中，对于所述翼型走线电连接的所述接收端子，所述翼型走线在所述衬底上的正投影与至少一个所述接收端子在所述衬底上的正投影交叠。
在本申请的一些实施例中，所述翼型走线电连接的所述接收端子划分为沿所述第一侧边排布的第一组和沿所述第二侧边排布的第二组；第一组所述接收端子电连接的各所述翼型走线同层设置，第二组所述接收端子电连接的所述翼型走线包括第一翼型走线和第二翼型走线，且所述第一翼型走线和所述第二翼型走线位于不同层；
其中，第一组所述接收端子电连接的所述翼型走线和第二组所述接收端子电连接的所述翼型走线中的各所述第二翼型走线同层设置。
在本申请的一些实施例中，所述翼型走线电连接的所述接收端子包括：
位于所述衬底上的栅极层，包括相互独立且相对设置的两个导电垫；
介质层，覆盖所述栅极层并暴露出各所述导电垫的部分区域；
源漏金属层，覆盖所述介质层并与所述导电垫暴露出的部分区域直接接触；
电极层，覆盖所述源漏金属层，被配置为与所述驱动芯片的所述输出端子直接接触。
在本申请的一些实施例中，第一组所述接收端子电连接的所述翼型走 线和第二组所述接收端子电连接的所述翼型走线中的各所述第二翼型走线均位于所述栅极层，且均从所述接收端子的两个所述导电垫之间的区域穿过。
在本申请的一些实施例中，对于第一组所述接收端子中的其中一个所述接收端子，一条所述翼型走线与其所述导电垫电连接、且第一组所述接收端子电连接的其它所述翼型走线在所述衬底上的正投影与其所述导电垫在所述衬底上的正投影互不交叠；
对于第二组所述接收端子中的其中一个所述接收端子，一条所述第二翼型走线与其所述导电垫电连接、且第二组所述接收端子电连接的其它所述第二翼型走线在所述衬底上的正投影与其所述导电垫在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，所述显示面板还包括多个备用接收端子，所述备用接收端子和所述接收端子的结构相同；
与第一组所述接收端子同排设置的所述备用接收端子为第一备用接收端子，与第二组所述接收端子同排设置的所述备用接收端子为第二备用接收端子；
其中，与第一组所述接收端子电连接的所述翼型走线中的至少部分从所述第一备用端子中的两个导电垫之间的区域穿过，与第二组所述接收端子电连接的所述翼型走线中的至少部分从所述第二备用端子中的两个导电垫之间的区域穿过。
在本申请的一些实施例中，所述扇出走线包括显示扇出走线和触控扇出走线；
各所述触控扇出走线均从所述扇出区延伸至所述第一侧边所在的区域，并与所述输出端子电连接；部分所述显示扇出走线通过所述翼型走线与所述输出端子电连接。
在本申请的一些实施例中，所述翼型走线包括显示翼型走线和触控翼型走线；所述扇出走线包括显示扇出走线和触控扇出走线；
部分所述显示扇出走线通过所述显示翼型走线和所述输出端子电连接，部分所述触控扇出走线通过所述触控翼型走线和所述输出端子电连接。
在本申请的一些实施例中，各所述翼型走线同层设置。
在本申请的一些实施例中，部分所述翼型走线同层设置，另一部分所述翼型走线包括第一翼型走线和第二翼型走线，且所述第一翼型走线和所述第二翼型走线位于不同层；
其中，同层设置的各述翼型走线从所述绑定区延伸至所述扇出区，且包括依次连接的第一线段、第二线段、第三线段、第四线段和第五线段，其中，所述第一线段和所述第二线段位于所述绑定区，所述第三线段从所述绑定区延伸至所述扇出区，所述第四线段和所述第五线段位于所述扇出区；所述第一线段和所述扇出走线电连接，所述第五线段和所述输出端子电连接。
在本申请的一些实施例中，所述翼型走线包括第一翼型走线和第二翼型走线，所述第一翼型走线和所述第二翼型走线位于不同层；
所述第一翼型走线沿第一方向延伸，所述第二翼型走线包括沿第二方向延伸的第一线段；所述第一翼型走线分别与所述扇出走线和所述第一线段电连接；所述第一方向为所述显示区指向所述绑定区的方向，所述第二方向和所述第一方向平行；
其中，所述第一线段在所述显示面板的衬底上的正投影和与其电连接的所述第一翼型走线在所述衬底上的正投影交叠。
在本申请的一些实施例中，所述第二翼型走线还包括第二线段和第三线段，所述第二线段沿第三方向延伸，所述第一线段、所述第二线段和所述第三线段依次相连，所述第三线段和所述输出端子电连接；所述第三方向和所述第一方向相交；
其中，在所述第三方向上，各所述第一翼型走线、各所述第一线段和各所述第三线段的排布顺序相同。
在本申请的一些实施例中，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角为直角，所述第二线段的延伸线和所述第三线段的延伸线之间的夹角为直角；
或者，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角为钝角，所述第二线段的延伸线和所述第三线段的延伸线之间的夹角为钝角，且两个所述钝角的角度相同；
或者，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角以及所述第二线段的延伸线和所述第三线段的延伸线之间的夹角中的其中一个 为直角，另一个为钝角。
在本申请的一些实施例中，所述第一线段和所述第二线段之间设置有第一拐角，所述第二线段和所述第三线段之间设置有第二拐角；
各拐角中的至少部分为圆角。
在本申请的一些实施例中，相邻两个所述第一拐角之间设置有至少一个岛状图形，相邻两个所述第一拐角之间的各所述岛状图形互不连接；
和/或，相邻两个所述第二拐角之间设置有至少一个岛状图形，相邻两个所述第二拐角之间的各所述岛状图形互不连接。
在本申请的一些实施例中，部分所述第二翼型走线位于同一层，另一部分所述第二翼型走线位于同一层，且两部分所述第二翼型走线位于不同层；
在所述第三方向上，将每两条所述第一线段划分为一组，每组所述第一线段走线组包括沿所述第三方向排布的外侧第一线段和内侧第一线段；
其中，对于每组所述第一线段走线组，所述外侧第一线段电连接的所述第二线段在所述衬底上的正投影和所述内侧第一线段电连接的所述第二线段在所述衬底上的正投影交叠。
在本申请的一些实施例中，包括测试单元和多条测试连接走线；
所述测试单元位于各所述输出端子所在区域远离所述显示区的一侧；所述测试连接走线被配置为连接所述测试单元和所述输出端子；
其中，电连接所述翼型走线的所述输出端子还和所述测试连接走线直接电连接。
在本申请的一些实施例中，电连接同一所述输出端子的所述翼型走线在所述衬底上的正投影和所述测试连接走线在所述衬底上的正投影部分交叠。
在本申请的一些实施例中，包括测试单元，所述测试单元划分为显示测试单元和触控测试单元；
所述显示测试单元和所述触控测试单元中的至少一个位于所述显示区远离所述扇出区的一侧，剩余的一个位于所述扇出区或所述绑定区。
在本申请的一些实施例中，所述显示区远离所述扇出区的一侧的区域包括中央区和位于所述中央区两侧的两个转角区；所述显示测试单元和所述触控测试单元均包括多个测试子单元，所述测试子单元在所述衬底上的投影形状为矩形；
其中，所述转角区的各所述测试子单元围绕所述显示区的边缘设置；所述转角区的各所述矩形的长边平行，或所述转角区的相邻两个所述矩形的长边之间存在预设角度的夹角。
在本申请的一些实施例中，显示面板包括多条第一信号调节线，所述第一信号调节线位于所述扇出走线和所述翼型走线之间；
其中，在第三方向上，各所述扇出走线的排布顺序和各所述翼型走线的排布顺序不同；各所述第一信号调节线与所述扇出走线连接的一端的排布顺序和各所述扇出走线的排布顺序相同，各所述第一信号调节线与所述翼型走线连接的一端的排布顺序和各所述翼型走线的排布顺序相同；所述第三方向和所述第一方向相交。
在本申请的一些实施例中，显示面板包括多条第二信号调节线，对于通过所述第一侧边所在的区域与所述输出端子电连接的各所述扇出走线，所述扇出走线和所述输出端子之间还设置有所述第二信号调节线；
其中，在第三方向上，各所述扇出走线的排布顺序和各所述输出端子的排布顺序不同；各所述第二信号调节线与所述扇出走线连接的一端的排布顺序和各所述扇出走线的排布顺序相同，各所述第二信号调节线与所述输出端子连接的一端的排布顺序和各所述输出端子的排布顺序相同；所述第三方向和所述第一方向相交。
在本申请的一些实施例中，各所述第一翼型走线的至少部分线段为蛇形结构。
在本申请的一些实施例中，部分所述扇出走线的材料为第一导电材料，另一部分所述扇出走线的材料为第二导电材料，且所述第一导电材料的电阻大于所述第二导电材料的电阻；
材料为所述第一导电材料的各所述扇出走线中的一部分和所述第一翼型走线电连接，材料为所述第二导电材料的各所述扇出走线中的一部分和所述第一翼型走线电连接；
其中，材料为所述第一导电材料的所述扇出走线电连接的所述第一翼型走线为蛇形结构。
在本申请的一些实施例中，所述驱动芯片还包括多个输入端子，各所述输入端子沿所述第二侧边的延伸方向排布；
所述翼型走线在所述显示面板的衬底上的正投影和所述输入端子在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，所述扇出走线包括相连的第一扇出段和第二扇出段，所述第一扇出段和所述显示区的信号线电连接，所述第二扇出段和所述输出端子电连接；
其中，所述第二扇出段和所述显示区靠近所述扇出区的边缘之间存在预设夹角；
所述预设夹角的正弦值等于所有所述第二扇出段沿垂直于其延伸方向上所占区域的宽度和所述显示区沿平行于所述第一侧边方向上的宽度的一半比值。
第二方面，本申请的实施例提供了一种显示装置，包括如上所述的显示面板。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请的实施例提供的一种相关技术中的显示面板的结构示意图；
图2-图6、图10为本申请的实施例提供的六种不同的显示面板的 结构示意图；
图7为图6所示的显示面板的绑定区的结构示意图；
图8为图3所示的显示面板的绑定区的结构示意图；
图9为图10所示的显示面板的绑定区的结构示意图；
图11、图12分别为图10所示的显示面板的转角区的两种结构示意图；
图13为本申请的实施例提供的一种第一信号调节线/第二信号调节线的结构示意图；
图14为本申请的实施例提供的一种第一翼型走线的蛇形结构示意图；
图15为本申请的实施例提供的一种显示触控集成技术的显示面板的翼型走线结构示意图；
图16和图19为本申请的实施例提供的两种翼型走线从驱动芯片的第二侧边穿过的结构示意图；
图17为本申请的实施例提供的一种扇出走线的设置位置示意图；
图18为本申请的实施例提供的一种显示面板的绑定区和扇出区的结构示意图；
图20为本申请的实施例提供的又一种相关技术中的显示面板的结构示意图；
图21为本申请的实施例提供的又一种显示面板的结构示意图；
图22为图20中的接收端子的结构示意图；
图23为图22沿A1A2方向的截面示意图；
图24为图21中的接收端子的结构示意图；
图25为图24沿B1B2方向的截面示意图；
图26为图20所示的显示面板的一种设计尺寸示意图；
图27为图21所示的显示面板的一种设计尺寸示意图；
图28-图40为本申请的实施例又提供的十二种显示面板的结构示 意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行部分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在相关技术中，参考图1所示，显示面板的扇出区设置有非常密集的驱动信号线1(又称作扇出走线)，很大程度上降低了扇出区的设计空间，另外，由于驱动信号线1的线宽较窄，使得驱动信号线1自身的电阻较大，难以实现显示产品的高频充电。
基于此，本申请的实施例提供了一种显示面板，结合图2和图3所示，包括：
显示区AA；
位于显示区AA一侧的扇出区F；
位于扇出区F远离显示区AA一侧的绑定区B；绑定区B中设置有驱动芯片IC，驱动芯片IC包括与扇出区F相邻的第一侧边101、与第一侧边101相对的第二侧边102、连接第一侧边101和第二侧边102的两个第三侧边103；驱动芯片IC还包括多个输出端子4，输出端子靠 近第一侧边101设置；
显示面板包括：
位于扇出区F中的多条扇出走线2；
至少位于绑定区B中的多条翼型走线3；
其中，部分扇出走线2从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接；另一部分扇出走线2通过翼型走线3与输出端子4电连接，且翼型走线3从第一侧边101、两个第三侧边103和第二侧边102中的至少一个侧边所在的区域穿过。
需要说明的是，本申请的实施例中涉及的“部分扇出走线，另一部分扇出走线”的相关描述，指的是不同的两个部分的扇出走线，但本申请的实施例提供的扇出走线包括且不局限于这两部分，还可以包括其它部分的扇出走线。后文中其它地方涉及到的“部分，另一部分；一部分，另一部分”的相关描述与此处的含义类似，不再赘述。
在示例性的实施例中，通过翼型走线3将部分扇出走线2与输出端子4电连接，可以理解，翼型走线3位于扇出走线2和输出端子4之间的走线，且翼型走线3至少位于绑定区B。
其中，至少位于绑定区B中的多条翼型走线3的含义为：各翼型走线3均位于绑定区B；或者，部分翼型走线3位于绑定区B，另一部分翼型走线3可以从绑定区B延伸至扇出区F；或者，翼型走线3的部分线段位于绑定区B，翼型走线的另一部分线段位于扇出区F。
示例性的，参考图3所示，翼型走线3位于绑定区B中，通过翼型走线3从绑定区B绕线，将部分扇出走线2和对应的输出端子电连接。
示例性的，参考图18所示，翼型走线3的部分线段位于绑定区B，翼型走线3的另一部分线段位于扇出区F，可以理解，翼型走线3从绑定区B延伸至扇出区F，通过翼型走线3从绑定区B绕线至扇出区F，再从第一侧边101穿过将部分扇出走线2和对应的输出端子4电连接。
这里对于上述驱动芯片IC的具体类型不进行限定。示例性的，上述驱动芯片可以为显示驱动芯片；或者，上述驱动芯片还可以是TDDI芯片。
这里对于上述扇出走线2的具体类型不进行限定。示例性的，上述扇出走线2可以包括显示扇出走线(又称作显示驱动线或者源极驱动线)；或者，上述扇出走线2可以包括触控扇出走线；或者，上述扇出 走线2同时包括显示扇出走线和触控扇出走线。
当上述显示面板为触控和显示集成的显示面板(TDDI显示面板)时，上述扇出走线同时包括显示扇出走线和触控扇出走线。
在示例性的实施例中，可以设置部分显示扇出走线通过翼型走线3与输出端子4电连接，且翼型走线3从第一侧边101、两个第三侧边103和第二侧边102中的至少一个侧边所在的区域穿过，触控扇出走线和另一部分显示扇出走线从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接。
或者，可以设置部分触控扇出走线通过翼型走线3与输出端子4电连接，且翼型走线3从第一侧边101、两个第三侧边103和第二侧边102中的至少一个侧边所在的区域穿过，显示扇出走线和另一部分触控扇出走线从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接。
或者，可以设置部分触控扇出走线、部分显示扇出走线通过翼型走线3与输出端子4电连接，且翼型走线3从第一侧边101、两个第三侧边103和第二侧边102中的至少一个侧边所在的区域穿过，另一部分显示扇出走线和另一部分触控扇出走线从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接。
在示例性的实施例中，参考图5所示，显示面板包括用于实现触控功能的触控传感器Sensor，用于连接各触控传感器和各触控扇出走线的多条触控电极走线TX，用于连接各像素单元和各显示扇出走线的多条数据信号线Data。
当各触控电极走线TX均位于显示区AA的两侧、各数据信号线Data位于显示区AA时，可以将与数据信号线Data电连接的显示扇出走线(图5未绘制)设置在扇出区F的中间区域，将与各触控电极走线TX电连接的触控扇出走线设置在显示扇出走线的两侧，其中，图5所示的扇出区F中绘制的为触控扇出走线。此时，可以使得数据信号线Data电连接的显示扇出走线从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接，使得触控电极走线TX电连接的触控扇出走线通过翼型走线3与输出端子4电连接。
当各触控电极走线TX和各数据信号线Data均位于显示区AA时，触控电极走线TX和数据信号线Data的延伸方向和排布方向均相同， 触控电极走线TX和数据信号线Data交替排布。示例性的，可以是两条触控电极走线TX、一条数据信号线Data依次交替排布，或者，可以是以其它方式交替排布。此时，位于扇出区F中与触控电极走线TX电连接的触控扇出走线和与数据信号线Data电连接的显示扇出走线也可以交替排布。故而，可以设置部分显示扇出走线直接从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接，另一部分显示扇出走线通过翼型走线3与输出端子4电连接；设置部分触控扇出走线从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接，另一部分触控扇出走线通过翼型走线3与输出端子4电连接。
当然，参考图15所示，还可以设置所有触控扇出走线22均从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接；设置部分显示扇出走线21通过翼型走线3(第一翼型走线31和第二翼型走线32)与输出端子4电连接。
上述显示面板可以为LCD(Liquid Crystal Display，液晶显示器)显示面板、OLED(Organic Light Emitting Diode，有机发光二极管)显示面板、Mini LED显示面板或Micro LED显示面板中的任意一种。
上述显示面板的尺寸不做限定，其可以应用于大尺寸或者超大尺寸(例如：86英寸)的UHD(Ultra High Definition，超高清)显示装置或者HD(High Definition，高清)显示装置，或者，还可以应用小尺寸(例如：23.6英寸)的UHD显示装置或者HD显示装置。
上述显示面板可以为非TDDI(Touch and Display Driver Integration，触控与显示集成)技术的显示面板，或者，也可以为TDDI技术的显示面板。
示例性的，TDDI技术的显示面板可以分为ADS(Advanced Super Dimension Switch，高级超维场转换)型液晶触控显示屏或者HADS型液晶触控显示屏，这里对该显示面板的具体类型不做限定。
在实际应用中，对于非TDDI技术的显示面板，驱动芯片IC为显示驱动芯片，驱动信号线1为显示驱动线(Source线)，显示驱动线能够将显示驱动芯片中输出的显示驱动信号传输给显示面板中的数据信号线(Data线)，以控制显示区中各像素单元的显示。
而对于TDDI技术的显示面板，驱动芯片IC为TDDI芯片，驱动信号线1包括显示驱动线和触控驱动线，显示驱动线能够将TDDI芯片 中输出的显示驱动信号传输给显示面板中的数据信号线(Data线)，以控制显示区中各像素单元的显示；触控驱动线能够将TDDI芯片中输出的触控驱动信号传输给显示面板中的触控电极走线(TX线)，以控制触控传感器(Touch sensor)实现触控功能。
由于TDDI技术的显示面板的扇出区中不仅设置有显示驱动线，还设置有触控驱动线，故而对于TDDI技术的显示面板，其扇出区的设计空间更加局限，实现高频充电的难度更大。
然而，本申请的实施例中提供的显示面板中，在绑定区B中设置多条翼型走线3，通过翼型走线3绕线(包括从驱动芯片上侧、左右两侧和下侧的位置绕线)的方式，使得部分扇出走线2通过翼型走线3与驱动芯片的输出端子4电连接，从而利用了绑定区B中未设置驱动芯片的区域，缩短了翼型走线3电连接的扇出走线2的长度，大大减少了扇出走线2在扇出区B中占据的空间，在实际应用中，再通过增大扇出走线2的线宽和相邻两条扇出走线2之间的距离，可以很大程度上减小扇出走线2自身的电阻，从而可以实现对显示区AA中各像素单元的高频充电，提高显示面板的充电率，缩短充电时间，降低显示面板的功耗。
另外，在实际应用中，结合图1和图3所示，由于部分扇出走线2通过翼型走线3绕线的方式与驱动芯片的输出端子4电连接，利用了绑定区B中未设置驱动芯片的区域，缩短了翼型走线3电连接的扇出走线2的长度，进而减小了扇出区F沿显示区AA指向扇出区F方向上的尺寸d2，相较于相关技术中扇出区F沿显示区AA指向扇出区F方向上的尺寸d1，d2可以较d1小0.1mm-0.2mm，有利于制备窄边框的显示面板。
在示例性的实施例中，参考图18所示，翼型走线3从第一侧边101所在的区域穿过。
在实际应用中，在当通过翼型走线3进行绕线时，与翼型走线3电连接的扇出走线2和未与翼型走线3电连接的扇出走线2之间释放出一定的设计空间，翼型走线3可以从绑定区B延伸至扇出区F，从第一侧边101所在的区域绕线，使得这部分扇出走线2通过翼型走线3与输出端子4电连接。由于第一侧边101所在的区域的空间有限，可以根据情况设置少数的翼型走线3从所述第一侧边101所在的区域穿过并与输出端子4电连接，从而可以一定程度上减少扇出走线2在扇出区B中 占据的设计空间。
需要说明的是，图18中以部分翼型走线3从第一侧边101所在区域穿过，部分翼型走线3从第三侧边103所在区域穿过为例进行绘示。
在示例性的实施例中，参考图4所示，翼型走线3从驱动芯片IC的第二侧边102所在的区域穿过。
在实际应用中，驱动芯片IC的第二侧边102与显示面板的边缘之间还设置有电路板，翼型走线3可以经过第二侧边102与电路板之间的区域，再穿过第二侧边102所在的区域与驱动芯片的输出端子4电连接。
在示例性的实施例中，部分翼型走线3从驱动芯片IC的第二侧边102所在的区域穿过，另一部分翼型走线3从驱动芯片IC的两个第三侧边103中的至少一个侧边所在的区域穿过。
在示例性的实施例中，参考图3所示，翼型走线3从驱动芯片IC的两个第三侧边103中的至少一个侧边所在的区域穿过。
在实际应用中，由于绑定区B中驱动芯片IC两侧(103)和驱动芯片IC下侧的设计空间相对充足，可以设置翼型走线3从驱动芯片IC两侧(103)和下侧(102)的区域绕线。
示例性的，在翼型走线3从驱动芯片IC的两个第三侧边103中的至少一个侧边所在的区域穿过的情况下，翼型走线3的布线数量(即扇出走线2进行绕线的数量)与驱动芯片的输出端子4所在的区域到驱动芯片的输入端子5所在的区域之间的最小距离、翼型走线3的线宽、相邻两条翼型走线3之间的间隙相关。例如，翼型走线3的线宽与相邻两条翼型走线3之间的间隙之和(Pitch)为4.0μm，驱动芯片的输出端子4所在的区域到驱动芯片的输入端子5所在的区域之间的最小距离为400μm，可设置100条翼型走线3，即可对100条扇出走线2进行绕线。在实际应用中，可以根据情况确定各扇出走线2进行绕线的数量，这里不进行限定。
在示例性的实施例中，参考图18所示，部分翼型走线3从所述第一侧边101所在的区域穿过，另一部分翼型走线3从两个第三侧边103中的至少一个侧边所在的区域穿过。
在实际应用中，由于部分扇出走线2通过翼型走线3从绑定区B中绕线后与驱动芯片的输出端子4电连接，在扇出区F中，与翼型走线3 电连接的扇出走线2和未与翼型走线3电连接的扇出走线2之间存在可利用的空间F1，从而将翼型走线3从绑定区B延伸至如图18中标记F1的区域中，再经过驱动芯片的第一侧边101所在的区域穿过，并与输出端子4电连接。另外，再设置另一部分翼型走线3从两个第三侧边103中的至少一个侧边所在的区域穿过，可以很大程度上提高通过翼型走线3与输出端子4电连接的扇出走线2的数量，从而释放扇出区F的设计空间。在实际应用中，再通过增大扇出走线2的线宽和相邻两条扇出走线2之间的距离，可以很大程度上减小扇出走线2自身的电阻，从而可以实现对显示区AA中各像素单元的高频充电，提高显示面板的充电率，缩短充电时间，降低显示面板的功耗。
在本申请的一些实施例中，参考图21所示，显示面板还包括多个接收端子41，接收端子41被配置为与驱动芯片的输出端子4绑定在一起；接收端子41在显示面板的衬底上的正投影和输出端子4在衬底上的正投影交叠；部分接收端子41和穿过第一侧边101所在的区域的扇出走线2电连接，另一部分接收端子41和翼型走线3电连接；
其中，对于翼型走线3电连接的接收端子41，翼型走线3在衬底上的正投影与至少一个接收端子4在衬底上的正投影交叠。
在示例性的实施例中，接收端子41在显示面板的衬底上的正投影和输出端子4在衬底上的正投影交叠的含义为：接收端子41的外轮廓在显示面板的衬底上的正投影和输出端子4的外轮廓在衬底上的正投影存在交叠区；或者，接收端子41的外轮廓在显示面板的衬底上的正投影和输出端子4的外轮廓在衬底上的正投影完全重叠。
在本申请的实施例提供的附图中，以接收端子41的外轮廓在显示面板的衬底上的正投影和输出端子4的外轮廓在衬底上的正投影完全重叠为例进行绘制，故而在绘制设置有驱动芯片的输出端子4的相关附图中，只绘制出输出端子4的结构，显示面板上的接收端子41的结构并未体现，这里做出说明。
在示例性的实施例中，接收端子41和驱动芯片的输出端子4一一对应连接，且翼型走线3或者扇出走线2均先与接收端子41电连接，接收端子41再通过绑定(Bonding)与驱动芯片的输出端子4电连接。
在示例性的实施例中，对于翼型走线3电连接的接收端子41，翼型走线 3在衬底上的正投影与至少一个接收端子4在衬底上的正投影交叠的含义为：参考图21所示，以第一组接收端子S1为例进行说明，第一组接收端子S1中包括5个接收端子41；其中，对于第一个接收端子41，第一组接收端子S1中的5个接收端子41电连接的翼型走线3均在沿垂直于衬底的方向上与其存在交叠；对于第二个接收端子41，第一组接收端子S1中除第一个接收端子41电连接的翼型走线3之外的其它四条翼型走线3均在沿垂直于衬底的方向上与其存在交叠；对于第三个接收端子41，第一组接收端子S1中除第一个、第二个接收端子41电连接的翼型走线3之外的其它三条翼型走线3均在沿垂直于衬底的方向上与其存在交叠；对于第四个接收端子41，第一组接收端子S1中除第一个、第二个、第三个接收端子41电连接的翼型走线3之外的其它两条翼型走线3均在沿垂直于衬底的方向上与其存在交叠；对于第五个接收端子41，只有与第五个接收端子41电连接的翼型走线3在沿垂直于衬底的方向上与其存在交叠。
需要说明的是，本申请的实施例提供的附图21仅以第一组接收端子S1包括5个接收端子，第二组接收端子S2包括5个接收端子，绑定区B左侧区域包括10条翼型走线为例进行绘制，在实际应用中，其具体数量不做限定，可以根据设计需求确定。
另外，需要说明的是，本申请的实施例提供的附图21仅以多个接收端子41排布为两排为例进行绘示，在实际应用中，多个接收端子41还可以排布为三排，或者，多个接收端子41排布为四排，或者，按照其它方式进行排布，具体可以根据输出端子4的排布方式确定，这里不进行限制。
相对于如图20所示的相关技术中，设置扇出走线2在衬底上的正投影和接收端子41在衬底上的正投影互不交叠的设计而言，参考图21所示，在本申请的实施例中，通过设置翼型走线3绕线，对于翼型走线3电连接的接收端子41，使得翼型走线3在衬底上的正投影与至少一个接收端子4在衬底上的正投影交叠，一方面，节省了显示面板的扇出区F的设计空间；另一方面，节省了多各接收端子41之间的空间，可以更加灵活的设计接收端子41的排布位置，从而可以更加灵活的设置驱动芯片中输出端子4的排布位置，或者说，可以更加灵活的选取可以匹配的驱动芯片的类型。
另外，本申请的实施例提供的如图21所示的显示面板，其扇出区F和绑定区B的其中一种设计尺寸如图27所示。可以看出，其扇出区F的宽度 (显示区AA的边缘到驱动芯片IC的第一侧边之间的距离)为1.01mm；驱动芯片的第一侧边到第二侧边之间的距离为0.77mm，柔性电路板(FPC)的宽度为0.35mm，驱动芯片到柔性电路板之间的距离为0.3mm，柔性电路板(FPC)到显示面板的边缘(阵列基板的边缘)的距离为0.07mm，即绑定区的宽度为1.49mm；该显示面板的下边框的宽度为1.01mm+1.49mm＝2.5mm。而如图20所示的相关技术中的显示面板，其设计尺寸如图26所示，对比可知，本申请的实施例提供的如图21所示的显示面板，其扇出区F的宽度(显示区AA的边缘到驱动芯片IC的第一侧边之间的距离)较相关技术中的显示面板的扇出区F的宽度减小了0.1mm。其中，图26和图27中标记的数字的单位均为毫米(mm)。
在本申请的一些实施例中，参考图21所示，翼型走线3电连接的接收端子41划分为沿第一侧边101排布的第一组S1和沿第二侧边102排布的第二组S2；第一组接收端子S1电连接的各翼型走线3同层设置，第二组接收端子S2电连接的翼型走线3包括第一翼型走线31和第二翼型走线32，且第一翼型走线31和第二翼型走线32位于不同层；
其中，第一组接收端子S1电连接的翼型走线3和第二组接收端子S2电连接的翼型走线3中的各第二翼型走线32同层设置。
在示例性的实施例中，第一组接收端子S1电连接的翼型走线3和第二组接收端子S2电连接的翼型走线3中的各第二翼型走线32的材料相同，例如，其材料和显示区AA中源漏金属层(SD)的材料相同；或者，其材料和显示区AA中栅极(Gate)的材料相同。
在示例性的实施例中，当翼型走线3的材料和显示区AA中源漏金属层(SD)的材料相同时，翼型走线3可以和显示区AA中的源漏金属层(SD)同层制作；当翼型走线3的材料和显示区AA中栅极(Gate)的材料相同时，翼型走线3可以和显示区AA中的栅极(Gate)同层制作。
在本申请的一些实施例中，参考图25所示，翼型走线3电连接的接收端子41包括：
位于衬底401上的栅极层，包括相互独立且相对设置的两个导电垫404；
介质层405，覆盖栅极层并暴露出各导电垫404的部分区域；
源漏金属层406，覆盖介质层405并与导电垫404暴露出的部分区域直接接触；
电极层407，覆盖源漏金属层406，被配置为与驱动芯片的输出端子4直接接触。
上述栅极层和显示区AA中的栅极层材料相同，且同层设置，且在一次构图工艺中制备。
上述电极层407和显示区AA中的像素电极的材料相同，且同层设置，且在一次构图工艺中制备。
上述电极层407覆盖源漏金属层406的含义为：电极层407在衬底上的正投影覆盖源漏金属层406在衬底上的正投影，且电极层407在衬底上的正投影面积大于源漏金属层406在衬底上的正投影面积。这样，可以起到保护源漏金属层406的作用。
参考图25所示，接收端子41还包括位于衬底401上的缓冲层402、位于缓冲层402上的栅极绝缘层403，当然，栅绝缘层403还可以位于栅极层远离衬底401的一侧，具体可以根据实际产品的设计确定，这里不进行限制。
图24示出了本申请的实施例提供的一种接收端子41的俯视结构图，其中，图25为图24沿B1B2方向的截面图。
相对于如图22和图23的相关技术中，将接收端子41的导电垫404设置为一体化的块状结构，并占据接收端子41的中央区域而言，本申请的实施例中，参考图24和图25，通过设置相互独立且相对设置在接收端子41两端的区域的两个导电垫404，一方面，两个导电垫404中的一个可以作为备用导电垫，以在一个导电垫404出现异常时，可以进行修补和替换；另一方面，由于两个导电垫404相对设置在接收端子41两端的区域，从而预留出接收端子41的两个导电垫404之间区域，以便进行其它结构的设计，增加了设计空间。其中，图23为图22沿A1A2方向的截面图。
在本申请的一些实施例中，结合图21和图24所示，第一组接收端子S1电连接的翼型走线3和第二组接收端子S2电连接的翼型走线3中的各第二翼型走线32均位于栅极层，且均从接收端子41的两个导电垫404之间的区域穿过。
在本申请的实施例中，由于两个导电垫404相对设置在接收端子41两端的区域，从而预留出接收端子41的两个导电垫404之间区域，通过设置 翼型走线3位于栅极层，且翼型走线从各接收端子41的两个导电垫404之间的区域穿过；相对于相关技术中的走线从接收端子41之间的区域穿过而言，本申请的实施例中的设计方式在保证电信号正常稳定传输的情况下，很大程度上节省了显示面板的绑定区和扇出区的设计空间，这样，一方面，可以通过适当增加走线的线宽来实现高频充电，另一方面，有利于窄边框显示产品的制备。
在本申请的一些实施例中，参考图21所示，对于第一组接收端子S1中的其中一个接收端子41，一条翼型走线3与其导电垫404电连接、且第一组接收端子S1电连接的其它翼型走线3在衬底上的正投影与其导电垫404在衬底上的正投影互不交叠；
对于第二组接收端子S2中的其中一个接收端子41，一条第二翼型走线32与其导电垫404电连接、且第二组接收端子S2电连接的其它第二翼型走线32在衬底上的正投影与其导电垫404在衬底上的正投影互不交叠。
在本申请的实施例中，由于与接收端子41在沿垂直于衬底的方向上存在交叠的翼型走线位于栅极层，接收端子41的导电垫404也位于栅极层，为了确保接收端子41和各翼型走线3之间不存在信号传输错乱的问题，对于每一个和翼型走线3连接的接收端子41，通过设置一个接收端子41，只与其电连接的翼型走线3之间在沿垂直于衬底的方向上存在交叠，而与其他的翼型走线3之间在沿垂直于衬底的方向上不存在交叠。
在本申请的一些实施例中，参考图40所示，显示面板还包括多个备用接收端子42，备用接收端子42和接收端子41的结构相同；
与第一组接收端子S1同排设置的备用接收端子42为第一备用接收端子，与第二组接收端子S2同排设置的备用接收端子42为第二备用接收端子；
其中，与第一组接收端子电连接的翼型走线3中的至少部分从第一备用端子中的两个导电垫404之间的区域穿过，与第二组接收端子电连接的翼型走线3中的至少部分从第二备用端子中的两个导电垫404之间的区域穿过。
在示例性的实施例中，参考图40所示，备用接收端子42并未与翼型走线3电连接。
这里对于显示面板中备用接收端子(Dummy接收端子)42的具体数量不进行限定。示例性的，备用接收端子42的数量为5个，其中，第一备用 接收端子的数量为2个，第二备用接收端子的数量为3个。
在示例性的实施例中，备用接收端子42位于多个接收端子41的两端；或者，参考图40所示，备用接收端子42位于多个接收端子41的一侧(其中，第一备用接收端子位于第一组接收端子41的左侧，第二备用接收端子位于第二组接收端子41的左侧)；或者，备用接收端子42和接收端子41间隔设置。
在示例性的实施例中，参考图40所示，部分接收端子41中的两个导电垫404之间的区域并未设置翼型走线3；当然，也可以存在每个接收端子41中的两个导电垫404之间的区域至少有一条翼型走线3穿过。具体可以根据实际情况确定。
在本申请的一些实施例中，参考图15所示，扇出走线2包括显示扇出走线21和触控扇出走线22；
各触控扇出走线均22从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接；部分显示扇出走线21通过翼型走线3与输出端子电连接。
需要说明的是，在实际应用中，由于触控扇出走线22的数量小于显示扇出走线21的数量，可以设置显示扇出走线21通过翼型走线3绕线的方式与输出端子4电连接，从而可以方便扇出区F中各扇出走线2的排布。
当然，对于当前的主流显示产品，由于触控扇出走线22的数量小于显示扇出走线21的数量，设置显示扇出走线21通过翼型走线3绕线的方式与输出端子4电连接，若对于个别显示产品，由于设计需求，也可以设置触控扇出走线22通过翼型走线3绕线的方式与输出端子4电连接，这里仅以当前的实际需求为例进行说明。
另外，本申请的实施例提供的附图15仅以翼型走线3从第二侧边102所在的区域穿过为例进行绘示。
在示例性的实施例中，在如图18所示的结构中，当翼型走线3从第一侧边101所在的区域穿过时，对于这部分翼型走线3电连接的扇形走线2，与翼型走线3电连接的扇出走线2和未与翼型走线3电连接的扇出走线2之间释放出一定的设计空间，翼型走线3可以从绑定区B延伸至扇出区F，从第一侧边101所在的区域绕线，使得这部分扇出走线 2通过翼型走线3与输出端子4电连接。由于第一侧边101所在的区域的空间有限，可以设置与显示扇出走线21电连接的翼型走线3从所述第一侧边101所在的区域穿过并与输出端子4电连接。
在示例性的实施例中，对于如图4所示的结构中，当翼型走线3从驱动芯片IC的第二侧边102所在的区域穿过时，对于这部分翼型走线3电连接的扇形走线2，可以设置这部分扇出走线2均为显示扇出走线21，使得显示扇出走线21从驱动芯片IC的第二侧边102所在的区域穿过，再与输出端子4电连接，而使得另一部分显示扇出走线21和所有的触控扇出走线22从扇出区F延伸至绑定区B，从第一侧边所在的区域穿过后和输出端子4电连接。
在示例性的实施例中，参考图28所示，扇出走线2包括显示扇出走线21和触控扇出走线22，各触控扇出走线22均从扇出区F延伸至第一侧边101所在的区域，并与接收端子41电连接，接收端子41和输出端子4电连接(图28中未示意出驱动芯片的输出端子4的结构)；部分显示扇出走线21通过翼型走线3与接收端子41电连接，且翼型走线3均从驱动芯片两侧(第三侧边103)所在的区域穿过。
其中，通过翼型走线3与接收端子41电连接的显示扇出走线21可以分为两部分。
第一部分，显示扇出走线21电连接的各翼型走线3均位于栅极层，且这部分翼型走线3从接收端子41的两个导电垫404之间的区域穿过，并与对应的接收端子41的其中一个导电垫404电连接。
第二部分，显示扇出走线21电连接的各翼型走线3包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层，且对于每一条第一翼型走线31，均与其电连接的第二翼型走线32在沿垂直于衬底的方向上存在交叠，且其交叠区的延伸方向与第一翼型走线31和第二翼型走线32的延伸方向平行，第二部分显示扇出走线21电连接的各翼型走线3中的第二翼型走线32位于栅极层，且这部分第二翼型走线32从接收端子41的两个导电垫404之间的区域穿过，并与对应的接收端子41的其中一个导电垫404电连接。
示例性的，参考图28所示，可以将翼型走线3电连接的接收端子41划分为沿第一侧边101排布的第一组S1和沿第二侧边102排布的第二组S2；第一组接收端子S1电连接的各翼型走线3同层设置，第二组 接收端子S2电连接的翼型走线3包括第一翼型走线31和第二翼型走线32，且第一翼型走线31和第二翼型走线32位于不同层；
其中，第一组接收端子S1电连接的翼型走线3和第二组接收端子S2电连接的翼型走线3中的各第二翼型走线32同层设置。另外，第一组接收端子S1电连接的翼型走线3和第二组接收端子S2电连接的翼型走线3中的各第二翼型走线32均位于栅极层，且均从接收端子41的两个导电垫404之间的区域穿过。
在示例性的实施例中，参考图29所示，各触控扇出走线均22从扇出区F延伸至第一侧边101所在的区域，并与接收端子41电连接，接收端子41和输出端子4电连接(图29中未示意出驱动芯片的输出端子4的结构)；部分显示扇出走线21通过翼型走线3与接收端子41电连接，且翼型走线3均从驱动芯片两侧(第三侧边103)所在的区域穿过。通过翼型走线3与接收端子41电连接的显示扇出走线21可以分为三部分。
第一部分，显示扇出走线21通过翼型走线3与接收端子41电连接，翼型走线3从第一侧边101所在的区域穿过。
第二部分，显示扇出走线21电连接的各翼型走线3均位于栅极层，且这部分翼型走线3从接收端子41的两个导电垫404之间的区域穿过，并与对应的接收端子41的其中一个导电垫404电连接。
第三部分，显示扇出走线21电连接的各翼型走线3包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层，且对于每一条第一翼型走线31，均与其电连接的第二翼型走线32在沿垂直于衬底的方向上存在交叠，且其交叠区的延伸方向与第一翼型走线31的延伸方向平行，第二部分显示扇出走线21电连接的各翼型走线3中的第二翼型走线32位于栅极层，且这部分第二翼型走线32从接收端子41的两个导电垫404之间的区域穿过，并与对应的接收端子41的其中一个导电垫404电连接。
在示例性的实施例中，参考图30所示，对于下沉式驱动芯片，由于其输出端子4和输入端子5排布后占据的区域为三角形，输出端子4所在的区域和输入端子5所在的区域之间的设计空间有限，可以设置各触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接，部分显示扇出走线21通过 翼型走线3从驱动芯片的下侧(第二侧边102)所在的区域穿过、并穿过输入端子5所在的区域与输出端子4电连接。
在示例性的实施例中，参考图31所示，设置各触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与接收端子41电连接，部分显示扇出走线21通过翼型走线3与接收端子41电连接。
其中，通过翼型走线3与接收端子41电连接的显示扇出走线21分为两部分，第一部分显示扇出走线21通过翼型走线3从驱动芯片的下侧(第二侧边102)所在的区域穿过、并穿过输入端子5所在的区域与输出端子4(实际是先与接收端子41电连接，接收端子41与输出端子4电连接)电连接。第二部分显示扇出走线21连接的翼型走线3从驱动芯片两侧(第三侧边103)所在的区域穿过，并通过接收端子41的两个导电垫404之间的区域，再与对应的接收端子41的其中一个导电垫404电连接，其中，第二部分显示扇出走线21连接的翼型走线3位于栅极层，与导电垫404同层设置。
在示例性的实施例中，参考图32所示，设置各触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接，部分显示扇出走线21通过翼型走线3与输出端子4电连接。其中，通过翼型走线3与输出端子4电连接的显示扇出走线21分为两部分，第一部分显示扇出走线21通过翼型走线3从驱动芯片上侧(第一侧边101)所在的区域穿过并与输出端子4电连接，第二部分显示扇出走线21电连接的各翼型走线3包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层，且对于每一条第一翼型走线31，均与其电连接的第二翼型走线32在沿垂直于衬底的方向上存在交叠，且其交叠区的延伸方向与第一翼型走线31的延伸方向平行。
在示例性的实施例中，参考图37或图38所示，翼型走线3包括显示翼型走线和触控翼型走线；扇出走线2包括显示扇出走线21和触控扇出走线22；
部分显示扇出走线21通过显示翼型走线和输出端子4电连接，部分触控扇出走线22通过触控翼型走线和输出端子4电连接。
需要说明的是，在本申请的实施例提供的图37和图38中，并未区 分显示翼型走线和触控翼型走线的标记，其中，和显示扇出走线21电连接的翼型走线3为显示翼型走线，和触控扇出走线22电连接的翼型走线3为触控翼型走线。
在示例性的实施例中，参考图37所示，部分触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与接收端子41电连接，接收端子41和输出端子4电连接(图37中未示意出驱动芯片的输出端子4的结构)；另一部分显示扇出走线21通过显示翼型走线与接收端子41电连接，另一部分触控扇出走线22通过触控翼型走线接收端子41电连接。且翼型走线3(包括显示翼型走线和触控翼型走线)均从驱动芯片两侧(第三侧边103)所在的区域穿过。
在示例性的实施例中，参考图38所示，对于下沉式驱动芯片，由于其输出端子4和输入端子5排布后占据的区域为三角形，输出端子4所在的区域和输入端子5所在的区域之间的设计空间有限，可以设置部分触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接；另一部分显示扇出走线21通过显示翼型走线从驱动芯片的下侧(第二侧边102)所在的区域穿过、并穿过输入端子5所在的区域与输出端子4电连接，另一部分触控扇出走线22通过触控翼型走线从驱动芯片的下侧(第二侧边102)所在的区域穿过、并穿过输入端子5所在的区域与输出端子4电连接。
在示例性的实施例中，参考图39所示，设置部分触控扇出走线22和部分显示扇出走线21从扇出区F延伸至第一侧边101所在的区域，并与输出端子4电连接；另一部分显示扇出走线21通过显示翼型走线和输出端子4电连接，另一部分触控扇出走线22通过触控翼型走线和输出端子4电连接。
其中，通过显示翼型走线(与显示扇出走线21电连接的翼型走线3)与输出端子4电连接的显示扇出走线21分为两部分，第一部分显示扇出走线21通过显示翼型走线从驱动芯片上侧(第一侧边101)所在的区域穿过并与输出端子4电连接，第二部分显示扇出走线21电连接的各显示翼型走线包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层，且对于每一条第一翼型走线31，均与其电连接的第二翼型走线32在沿垂直于衬底的方向上存在交叠，且其交叠区的延伸方向与第一翼型走线31的延伸方向平行。
通过触控翼型走线(与触控扇出走线22电连接的翼型走线3)与输出端子4电连接的触控扇出走线22也分为两部分，第一部分触控扇出走线22通过触控翼型走线从驱动芯片上侧(第一侧边101)所在的区域穿过并与输出端子4电连接，第二部分触控扇出走线22电连接的各触控翼型走线也包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层，且对于每一条第一翼型走线31，均与其电连接的第二翼型走线32在沿垂直于衬底的方向上存在交叠，且其交叠区的延伸方向与第一翼型走线31的延伸方向平行。
在示例性的实施例中，参考图4、图6和图7所示，翼型走线3可以位于同一层中。
当翼型走线3的材料和显示区AA中源漏金属层(SD)的材料相同时，翼型走线3可以和显示区AA中的源漏金属层(SD)同层制作；当翼型走线3的材料和显示区AA中栅极(Gate)的材料相同时，翼型走线3可以和显示区AA中的栅极(Gate)同层制作。
示例性的，参考图4、图6和图7所示，各翼型走线3与扇出走线2连接的一端的排布顺序与各翼型走线3与输出端子4连接的一端的排布顺序相反，此时，为了避免因走线的位置顺序不一致导致的信号错乱的问题，可以通过驱动芯片调整输出端子4的输出信号的顺序。其中，图7为图6的局部区域放大示意图。
在本申请的一些实施例中，参考图18所示，部分翼型走线3同层设置，另一部分翼型走线3包括第一翼型走线31和第二翼型走线32，且第一翼型走线31和第二翼型走线32位于不同层；
其中，同层设置的各述翼型走线3包括依次连接的第一线段a、第二线段b、第三线段c、第四线段d和第五线段e，其中，第一线段a和第二线段b位于绑定区B，第三线段c从绑定区B延伸至扇出区F，第四线段d和第五线段e位于扇出区F；第一线段a和扇出走线2电连接，第五线段e和输出端子4电连接。
另外，与第一线段a电连接的扇出走线2的排布顺序、第一线段a的排布顺序、第五线段e的排布顺序和与第五线段e电连接的输出端子4的排布顺序均相同，从而确保各扇出走线2和信号对应的输出端子4电连接，从而避免了信号错乱的问题。
在实际应用中，由于部分扇出走线2通过翼型走线3从绑定区B中 绕线后与驱动芯片的输出端子4电连接，在扇出区F中，与翼型走线3电连接的扇出走线2和未与翼型走线3电连接的扇出走线2之间存在可利用的空间F1，从而将翼型走线3从绑定区B延伸至如图18中标记F1的区域中，再经过驱动芯片的第一侧边101所在的区域穿过，并与输出端子4电连接。这样，可以设置更多的扇出走线2通过翼型走线3绕线的方式和输出端子4电连接，从而可以减小扇出区F和绑定区B的设计空间。
在本申请的一些实施例中，参考图3和图8所示，每条翼型走线3包括第一翼型走线31和第二翼型走线32，第一翼型走线31和第二翼型走线32位于不同层。
示例性的，第一翼型走线31的材料和显示区AA中源漏金属层(SD)的材料相同时，第一翼型走线31可以和显示区AA中的源漏金属层(SD)同层制作；第二翼型走线32的材料和显示区AA中栅极(Gate)的材料相同时，第二翼型走线32可以和显示区AA中的栅极(Gate)同层制作。
或者，第一翼型走线31的材料和显示区AA中的栅极(Gate)的材料相同时，第一翼型走线31可以和显示区AA中的栅极(Gate)同层制作；第二翼型走线32的材料和显示区AA中的源漏金属层(SD)的材料相同时，第二翼型走线32可以和显示区AA中的源漏金属层(SD)同层制作。
其中，第一翼型走线31沿第一方向AF延伸，第二翼型走线32包括沿第二方向FA延伸的第一线段321；第一翼型走线31分别与扇出走线2和第一线段321电连接；第一方向AF为显示区AA指向绑定区B的方向，第二方向FA和第一方向AF平行；
其中，第一线段321在显示面板的衬底上的正投影和与其电连接的第一翼型走线31在衬底上的正投影交叠。
在示例性的实施例中，当第一线段321的线宽小于或者等于第一翼型走线31的线宽时，第一线段321在显示面板的衬底上的正投影位于与其电连接的第一翼型走线31在衬底上的正投影以内。
在本申请的实施例中，参考图3所示，由于扇出区F中的部分扇出走线2通过翼型走线3绕线的方式与驱动芯片的输出端子4电连接，相较于未与翼型走线3电连接的扇出走线2的位于扇出区F的部分线段 的长度d3，翼型走线3电连接的扇出走线2位于扇出区F的部分线段的长度d4很大程度上缩短，使得未与翼型走线3电连接的扇出走线2的电阻远大于与翼型走线3电连接的扇出走线2的电阻，造成显示面板中走线的电阻匹配性降低，造成信号传输不稳定。
在本申请的实施例中，通过设置第一线段321，使得第一线段321在显示面板的衬底上的正投影和与其电连接的第一翼型走线31在衬底上的正投影交叠，延长了与翼型走线3电连接的扇出走线2到输出端子4之间的走线的距离，从而可以一定程度上抵消与翼型走线3电连接的扇出走线2缩短的长度，提高了不同走线之间的电阻匹配性，从而提高了信号传输的稳定性。
在本申请的一些实施例中，参考图8所示，第二翼型走线32还包括第二线段322和第三线段323，第二线段322沿第三方向MN延伸，第一线段321、第二线段322和第三线段323依次相连，第三线段323和输出端子4电连接；第三方向MN和第一方向AF相交；
其中，在第三方向MN上，各第一翼型走线31、各第一线段321和各第三线段323的排布顺序相同。
具体的，参考图8所示，第一条第一翼型走线31、第二条第一翼型走线31、第三条第一翼型走线31、第四条第一翼型走线31和第五条第一翼型走线31沿第三方向MN依次排布；第一条第一线段321、第二条第一线段321、第三条第一线段321、第四条第一线段321和第五条第一线段321沿第三方向MN依次排布；第一条第三线段323、第二条第三线段323、第三条第三线段323、第四条第三线段323和第五条第三线段323沿第三方向MN依次排布。
在示例性的实施例中，第三方向和第一方向的相交之后的夹角可以是直角，或者，第三方向和第一方向的相交之后的夹角可以为钝角。需要说明的是，本申请的实施例提供的附图中标记的第三方向MN以第三方向MN和第一方向AF的相交之后的夹角为直角为例进绘制。
在本申请的实施例中，通过采用跳线设计，实现翼型走线3与输出端子4之间顺序的调整，使得扇出走线2与其对应的输出端子4电连接，无需驱动芯片在各输出端子4中做输出信号顺序的调整。
需要说明的是，在翼型走线3从驱动芯片的第二侧边102绕线时，也可以采用图8所示的跳线设计，图8中仅以翼型走线3从驱动芯片的 左侧(第三侧边)绕线为例进行绘示。
在本申请的一些实施例中，参考图8所示，第一线段321的延伸线和第二线段322的延伸线之间的夹角为直角，第二线段322的延伸线和第三线段323的延伸线之间的夹角为直角；
或者，参考图33所示，第一线段321的延伸线和第二线段322的延伸线之间的夹角为钝角，第二线段322的延伸线和第三线段323的延伸线之间的夹角为钝角，且两个钝角的角度相同；
或者，第一线段的延伸线和第二线段的延伸线之间的夹角以及第二线段的延伸线和第三线段的延伸线之间的夹角中的其中一个为直角，另一个为钝角。
在示例性的实施例中，由于第二翼型走线32的第一线段321在衬底上的正投影与其相连的第一翼型走线在衬底上的正投影部分交叠，这样，第一线段321能够延长与翼型走线3电连接的扇出走线2到输出端子4之间的走线的距离，从而可以一定程度上抵消与翼型走线3电连接的扇出走线2缩短的长度，提高了不同走线之间的电阻匹配性，从而提高了信号传输的稳定性。在实际应用中，需要抵消的走线的长度不同，可以根据实际产品需求通过设置第一线段321和第二线段322垂直，或者设置第一线段321和第二线段322的夹角为钝角来控制实际第二线段322的长度，从而提高走线之间的电阻匹配性。另外，为了优化不同显示产品的绑定区B中的走线的排布，提高空间利用率，也可以通过调整第一线段321和第二线段322的夹角的角度来实现。
在示例性的实施例中，参考图34所示，各翼型走线3同层设置；
其中，同层设置的各述翼型走线3包括依次连接的第一线段a、第二线段b、第三线段c、第四线段d和第五线段e，其中，第一线段a和第二线段b位于绑定区B，第三线段c从绑定区B延伸至扇出区F，第四线段d和第五线段e位于扇出区F；第一线段a和扇出走线2电连接，第五线段e和输出端子4电连接，且第二线段b的延长线和第三线段c的延长线之间的夹角为直角，第三线段c的延长线和第四线段d的延长线之间的夹角为直角；或者，第二线段b的延长线和第三线段c的延长线之间的夹角为钝角，第三线段c的延长线和第四线段d的延长线之间的夹角为钝角，且两个钝角的角度相同。
这里对于上述钝角的具体角度不进行限制，具体可以根据实际情况确定。
在示例性的实施例中，各触控扇出走线均22从扇出区F延伸至第一侧边101所在的区域，并与接收端子41电连接，接收端子41和输出端子4电连接；部分显示扇出走线21通过翼型走线3与接收端子41电连接，且翼型走线3均从驱动芯片两侧(第三侧边103)所在的区域穿过。通过翼型走线3与接收端子41电连接的显示扇出走线21可以分为三部分。其中，第一部分显示扇出走线21通过翼型走线3与接收端子41电连接，翼型走线3从第一侧边101所在的区域穿过，参考图35所示，对于从第一侧边101所在的区域穿过的翼型走线3，可以分为三段，其中，第一段和第二段之间的夹角角度等于第二段和第三段之间的夹角角度。
在本申请的一些实施例中，结合图8和图36所示，第二翼型走线32包括依次连接的第一线段321、第二线段322和第三线段323；
其中，第一线段321和第二线段322之间设置有第一拐角G，第二线段322和第三线段323之间设置有第二拐角(图36中未绘制)；
各拐角(包括第一拐角和第二拐角)中的至少部分为圆角。
需要说明的是，图36是图8中第一线段321和第二线段322所在区域的局部放大图，图36中提供了第一拐角的结构示意图，第二拐角的结构和第一拐角类似，不再赘述。
在示例性的实施例中，各拐角中的至少部分为圆角的含义为：各第一拐角中的部分为圆角；或者，各第一拐角均为圆角；或者，各第二拐角中的部分为圆角；或者，各第二拐角均为圆角；或者，各第一拐角和第二拐角均为圆角。
当然，各拐角中的部分还可以是直角，具体可以根据实际情况确定。
在本申请的一些实施例中，参考图36所示，相邻两个第一拐角G之间设置有至少一个岛状图形D，相邻两个第一拐角G之间的各岛状图形D互不连接；
和/或，相邻两个第二拐角之间设置有至少一个岛状图形，相邻两个第二拐角之间的各岛状图形互不连接。
在示例性的实施例中，岛状图形的含义为：该图形与其所在区域周边的其它结构均不连接，该图形独立设置。在实际应用中，由于该岛状图形采用和源漏金属层相同的材料同层制备，或者采用和栅极层相同的材料同层制备， 故而该岛状图形可以具备导电性，但并未与其它任何走线或者信号线电连接。
在示例性的实施例中，相邻两个第一拐角之间设置有至少一个岛状图形，相邻两个第一拐角之间的各岛状图形互不连接；或者，相邻两个第二拐角之间设置有至少一个岛状图形，相邻两个第二拐角之间的各岛状图形互不连接；或者，相邻两个第一拐角之间设置有至少一个岛状图形，相邻两个第一拐角之间的各岛状图形互不连接，且相邻两个第二拐角之间设置有至少一个岛状图形，相邻两个第二拐角之间的各岛状图形互不连接。
这里对于相邻两个第一拐角之间的岛状图形D的数量不进行限制。
示例性的，相邻两个第一拐角之间的岛状图形D的数量不完全相同，或者，相邻两个第一拐角之间的岛状图形D的数量完全相同。其中，图36中以相邻两个第一拐角之间的岛状图形D的数量不完全相同为例进行绘制。需要说明的是，相邻两个第一拐角之间的岛状图形D的数量不完全相同的含义为：对于部分第一拐角，相邻两个第一拐角之间的岛状图形D的数量相同；对于另一部分第一拐角，相邻两个第一拐角之间的岛状图形D的数量不同。
这里对于相邻两个第二拐角之间的岛状图形D的数量不进行限制。示例性的，相邻两个第一拐角之间的岛状图形D的数量不完全相同，或者，相邻两个第一拐角之间的岛状图形D的数量完全相同。
另外，相邻两个第一拐角之间的岛状图形D的数量可以和相邻两个第二拐角之间的岛状图形D的数量相同，或者，相邻两个第一拐角之间的岛状图形D的数量可以和相邻两个第二拐角之间的岛状图形D的数量不同。
这里对于相邻两个第一拐角之间的岛状图形D的具体形状和尺寸不进行限定。这里对于相邻两个第二拐角之间的岛状图形D的具体形状和尺寸不进行限定。
在实际应用中，为了简化设计，可以设置相邻两个第一拐角之间的岛状图形D的形状和相邻两个第而拐角之间的岛状图形D的形状相同。
示例性的，相邻两个第一拐角之间的岛状图形D在衬底上的投影形状为弧形、多边形，或者由弧形和多边形组合形成的形状。
其中，弧形可以包括扇形、半圆形、半椭圆形、圆形和椭圆形。多边形可以包括三角形、四边形、五边形或六边形。
示例性的，相邻两个第二拐角之间的岛状图形D在衬底上的投影形状与相邻两个第一拐角之间的岛状图形D在衬底上的投影形状相同。
在示例性的实施例中，参考图36所示，相邻两个第一拐角之间的岛状图形D可以和第二翼型走线32(包括第一线段321、第二线段322和第三线段323)同层设置，且第二翼型走线32和第一翼型走线31位于不同层。
在示例性的实施例中，岛状图形可以和栅极层位于同一层；或者，岛状图形可以和源漏金属层位于同一层。具体可以根据数据情况确定，这里不进行限制。
在实际应用中，可以使得岛状图形D和第二翼型走线32断开设置。
在示例性的实施例中，参考图36所示，相邻两个第一拐角之间的各岛状图形D在延垂直于衬底的方向上不完全与第一翼型走线31存在交叠区。
示例性的，参考图36所示，第一线段321在衬底上的正投影轮廓位于第一翼型走线31在衬底上的正投影轮廓以内。此时，相邻两个第一拐角之间的至少部分岛状图形D在衬底上的正投影可以和第一翼型走线31在衬底上的正投影部分交叠。
示例性的，第一线段321在衬底上的正投影轮廓与第一翼型走线31在衬底上的正投影轮廓重叠。此时，相邻两个第一拐角之间的至少部分岛状图形D在衬底上的正投影和第一翼型走线31在衬底上的正投影互不交叠。
在实际应用中，通过在相邻的第一拐角之间设置岛状图形，和/或，在相邻的第二拐角之间设置岛状图形，能够提高制备工艺的稳定性，提高第一拐角和第二拐角附近的走线的线宽均一性。
在本申请的一些实施例中，参考图9所示，部分第二翼型走线32位于同一层，另一部分第二翼型走线32位于同一层，且两部分第二翼型走线32位于不同层。
示例性的，参考图9所示，在第三方向MN上，将每两条第一线段321划分为一组，每组第一线段走线组(G1、G2、G3、G4或G5)包括沿第三方向MN排布的外侧第一线段W和内侧第一线段N；其中，对于每组第一线段走线组，外侧第一线段W电连接的第二线段322在衬底上的正投影和内侧第一线段N电连接的第二线段322在衬底上的正投影交叠。
在示例性的实施例中，翼型走线3分别设置在三层导电膜层上，具体的，参考图9所示，第一翼型走线31和第二翼型走线32位于不同 层，每组第一线段走线组中的外侧第一线段W和内侧第一线段N分别对应的第二翼型走线32位于不同层。
在示例性的实施例中，在使用过孔将位于不同层的走线导通时，需要兼顾搭接金属之间的接触电阻和所占用的设计空间。过孔数量越多，两层搭接金属之间的接触电阻越小，但所占用的空间越多。综合考虑电阻和空间的需求，通常搭接过孔的数量为两个，接触电阻在1.5Ω左右。
示例性的，第一翼型走线31采用和显示区AA中的栅极(Gate)相同的材料，即第一翼型走线31和栅极层同层设置；一部分第二翼型走线32采用和显示区AA中的源漏金属层(SD)相同的材料，另一部分第二翼型走线32采用和显示区AA中的遮光层(LS)相同的材料，即一部分第二翼型走线32和源漏金属层同层设置，另一部分第二翼型走线32和遮光层同层设置。
在示例性的实施例中，可以设置单层结构的钼(Mo)、叠层结构的钼/铝/钼(Mo/Al/Mo)、叠层结构的钛/铝/钛(Ti/Al/Ti)、双层结构的钼铌/铜(MoNb/Cu)、双层结构的钼铌钛/铜(MoNiTi/Cu)或者双层结构的钛/铜(Ti/Cu)作为栅极层。
在示例性的实施例中，栅极层沿垂直于衬底方向的厚度范围可以为
Figure PCTCN2022071014-appb-000001
例如：叠层结构的钼/铝/钼(Mo/Al/Mo)的各子层的厚度为200A/3000A/200A；叠层结构的钛/铝/钛(Ti/Al/Ti)的各子层的厚度为150/4000/200A；双层结构的钼铌钛/铜(MoNiTi/Cu)的两个子层的厚度为200A/4000A。
在示例性的实施例中，可以设置单层结构的钼(Mo)、叠层结构的钼/铝/钼(Mo/Al/Mo)、叠层结构的钛/铝/钛(Ti/Al/Ti)、双层结构的钼铌/铜(MoNb/Cu)、双层结构的钼铌钛/铜(MoNiTi/Cu)或者双层结构的钛/铜(Ti/Cu)中的任意一种作为源漏金属层(SD)。其中，源漏金属层(SD)沿垂直于衬底方向上的厚度范围可以为
Figure PCTCN2022071014-appb-000002
在示例性的实施例中，遮光层可以采用双层结构的铝/钼金属层(Al/Mo)、单层结构的钼金属层(Mo)、单层结构的钼铌金属层(MoNb)或单层结构的钛金属层金属制备，其厚度范围可以为
Figure PCTCN2022071014-appb-000003
需要说明的是，在翼型走线3从驱动芯片的右侧(另一个第三侧边103)和下侧(第二侧边102)绕线时，也可以设置外侧第一线段W电 连接的第二线段322在衬底上的正投影和内侧第一线段N电连接的第二线段322在衬底上的正投影交叠，本申请的附图仅以翼型走线3从驱动芯片的左侧绕线为例进行绘示说明。
在本申请的实施例中，对于每组第一线段走线组，通过设置外侧第一线段W电连接的第二线段322在衬底上的正投影和内侧第一线段N电连接的第二线段322在衬底上的正投影交叠，可以很大程度上减小各第二翼型走线32在沿第一方向AF上所占的区域的高度H，从而可以很大程度上增大设计空间。在实际应用中，再通过第二翼型走线32的线宽和相邻两条第二翼型走线32之间的距离，可以很大程度上减小第二翼型走线32自身的电阻，从而可以实现对显示区AA中各像素单元的高频充电，提高显示面板的充电率，缩短充电时间，降低显示面板的功耗。
另外，由于第二翼型走线32在沿第一方向AF上所占的区域的高度H较小，可以设置更多的扇出走线2通过翼型走线3绕线的方式与输出端子4电连接，从而缩短了翼型走线3电连接的各扇出走线2的长度，从而进一步减小了扇出走线2在扇出区B中占据的空间。进一步的，随着通过翼型走线3绕线的方式与输出端子4电连接的扇出走线2的数量的增加，还能够进一步减小了扇出区F沿显示区AA指向扇出区F方向上的尺寸，更有利于制备窄边框的显示面板。
在本申请的一些实施例中，参考图3或图6所示，显示面板包括测试单元CT和多条测试连接走线6；
测试单元CT位于各输出端子4所在区域远离显示区AA的一侧；测试连接走线6被配置为连接测试单元CT和输出端子4；
其中，电连接翼型走线3的输出端子4和测试连接走线6直接电连接。
示例性的，上述测试单元CT包括显示测试单元Data CT和触控测试单元VCOM CT中的至少一个。具体的，上述测试单元CT可以包括显示测试单元Data CT；或者，上述测试单元CT可以包括触控测试单元VCOM CT；或者，上述测试单元CT同时包括显示测试单元Data CT和触控测试单元VCOM CT。
在本申请的一些实施例中，对于部分输出端子4，其既连接一条翼型走线3，还连接一条测试连接走线6，且电连接同一输出端子4的翼 型走线3在衬底上的正投影和测试连接走线6在衬底上的正投影部分交叠。
这样，可以设置测试连接走线6和翼型走线3位于不同层，从而可以节省输出端子4所在区域和测试单元CT所在区域之间的设计空间。
在本申请的一些实施例中，参考图10所示，显示面板包括测试单元CT，测试单元CT划分为显示测试单元Data CT和触控测试单元VCOM CT；显示测试单元Data CT和触控测试单元VCOM CT中的至少一个位于显示区AA远离扇出区F的一侧，剩余的一个位于扇出区F或绑定区B。
示例性的，可以将显示测试单元Data CT和触控测试单元VCOM CT均设置在显示区AA远离扇出区F的一侧。
示例性的，可以将显示测试单元Data CT和触控测试单元VCOM CT其中的一个设置在显示区AA远离扇出区F的一侧，另一个设置在扇出区F或绑定区B。
具体的，参考图10所示，当显示测试单元Data CT或触控测试单元VCOM CT位于扇出区F时，显示测试单元Data CT或触控测试单元VCOM CT可以位于驱动芯片IC和MUX电路之间的区域，需要说明的是，MUX电路用于将显示区AA中的信号线与扇出区F中的扇出走线2电连接，MUX电路相关的具体内容可以参考相关技术，这里不再赘述。
当显示测试单元Data CT或触控测试单元VCOM CT位于绑定区B时，显示测试单元Data CT或触控测试单元VCOM CT可以位于驱动芯片IC所在的区域，且测试单元在衬底上的正投影与驱动芯片IC在衬底上的正投影交叠；或者，显示测试单元Data CT或触控测试单元VCOM CT可以位于绑定区B中除驱动芯片IC所在的区域之外的任意区域。
其中，图10以显示测试单元Data CT位于扇出区F，触控测试单元VCOM CT位于显示区AA远离扇出区F的一侧为例进行绘示。
本申请的实施例中，通过设置显示测试单元Data CT和触控测试单元VCOM CT中的至少一个位于显示区AA远离扇出区F的一侧，可以很大程度上释放绑定区B或扇出区F的设计空间，从而可以提供空间以增加绑定区B或扇出区F中的走线的线宽、增加相邻两条走线之间的距离，进而可以降低走线自身的电阻，有利于实现显示面板的高频充 电，提高充电效率，缩短充电时间，降低功耗。
在本申请的一些实施例中，显示区AA远离扇出区F的一侧的区域包括中央区和位于中央区两侧的两个转角区R；显示测试单元Data CT和触控测试单元VCOM CT均包括多个测试子单元T，测试子单元T在衬底上的投影形状为矩形；
其中，转角区R的各测试子单元T围绕显示区AA的边缘设置；参考图11所示，转角区R的各矩形的长边平行；或，参考图12所示，转角区R的每相邻两个矩形的长边之间存在预设角度的夹角。
示例性的，上述预设角度可以为锐角。
示例性的，每相邻两个矩形的长边之间存在的夹角的角度相同。
示例性的，上述测试子单元T可以为测试垫(PAD)；或者，上述测试子单元T可以为开关晶体管(STFT)；或者，部分测试子单元T为测试垫，另一部分测试子单元T为开关晶体管。
需要说明的是，上述测试子单元T在衬底上的投影形状为矩形，其中矩形可以理解为标准的矩形；或者，也可以是圆角矩形。
本申请的实施例中，通过设置转角区R中各测试子单元T在衬底上的投影的长边平行，能够降低设计难度、降低制作难度，缩减成本。
在本申请的一些实施例中，结合图6和图13所示，显示面板包括多条第一信号调节线11，第一信号调节线11位于扇出走线2和翼型走线3之间；
其中，在第三方向MN上，各扇出走线2的排布顺序和各翼型走线3的排布顺序不同；各第一信号调节线11与扇出走线2连接的一端END1的排布顺序和各扇出走线2的排布顺序相同，各第一信号调节线11与翼型走线3连接的一端END2的排布顺序和各翼型走线3的排布顺序相同；第三方向MN和第一方向AF相交。
在实际应用中，对于与翼型走线3电连接的扇出走线2，位于扇出区F中的与翼型走线3电连接的多条扇出走线2的排布顺序和位于绑定区B中的多条翼型走线3的排布顺序不一致，为了避免由于走线设置位置不一致导致的信号传输错乱的情况，在扇出走线2和翼型走线3之间设置第一信号调节线11，通过第一信号调节线11的跳线设计，使得扇出走线2与其将要传输的信号一致的翼型走线3电连接。
当显示面板为TDDI技术的显示面板时，由于部分扇出走线2为显 示扇出走线，部分扇出走线2为触控扇出走线，位于扇出区F中的与翼型走线3电连接的扇出走线2的排布顺序和位于绑定区B中的翼型走线3的排布顺序错乱的情况更显著，为了使得位置顺序不一致的扇出走线2和翼型走线3传输的信号的顺序一致，通过设置多条第一信号调节线11，使得扇出走线2与其将要传输的信号一致的翼型走线3电连接。
具体的，参考图13所示，与翼型走线3电连接的多条扇出走线2的排布顺序依次为：第2条扇出走线2、第3条扇出走线2、第1条扇出走线2、第5条扇出走线2、第6条扇出走线2、第4条扇出走线2、第9条扇出走线2……翼型走线3与扇出走线2电连接的一端的排列顺序依次为：第1条翼型走线3、第2条翼型走线3、第3条翼型走线3….显然，扇出走线2和翼型走线3的位置排列顺序不一致，通过在两者之间设置第一信号调节线11，使得第一信号调节线11与扇出走线2电连接的一端END1的排列顺序和扇出走线2的排布顺序相同，第一信号调节线11与翼型走线3连接的一端END2的排布顺序和翼型走线3的排布顺序相同，从而实现了走线位置顺序不一致，但将要传输的信号的顺序一致。需要说明的是，图13中并未绘制翼型走线3和扇出走线2，仅在第一信号调节线11两端标记了表示翼型走线3和扇出走线2的排布顺序的数字标记。
在本申请的一些实施例中，结合图6和图13所示，对于通过第一侧边101所在的区域与输出端子4电连接的各扇出走线2，扇出走线2和输出端子4之间还设置有第二信号调节线12；
其中，在第三方向MN上，各扇出走线2的排布顺序和各输出端子4的排布顺序不同；各第二信号调节线12与扇出走线2连接的一端END1的排布顺序和各扇出走线2的排布顺序相同，各第二信号调节线12与输出端子4连接的一端END2的排布顺序和各输出端子4的排布顺序相同；第三方向MN和第一方向AF相交。
在实际应用中，对于与输出端子4电连接的扇出走线2(未与翼型走线3电连接的部分扇出走线2)，位于扇出区F中的与输出端子4电连接的扇出走线2的排布顺序和位于绑定区B中的输出端子4的排布顺序不一致，为了避免由于走线和输出端子4设置位置不一致导致的信号传输错乱的情况，在扇出走线2和输出端子4之间设置多条第二信号调节线12，通过多条第二信号调节线12的跳线设计，使得扇出走线2 与其将要传输的信号一致的输出端子4电连接。
具体的，参考图13所示，与输出端子4电连接的多条扇出走线2的排布顺序依次为：第2条扇出走线2、第3条扇出走线2、第1条扇出走线2、第5条扇出走线2、第6条扇出走线2、第4条扇出走线2、第9条扇出走线2……输出端子4的排列顺序依次为：第1个输出端子4、第2个输出端子4、第3个输出端子4….显然，扇出走线2和个输出端子4的位置排列顺序不一致，通过在两者之间设置第二信号调节线12，使得第二信号调节线12与扇出走线2电连接的一端END1的排列顺序和扇出走线2的排布顺序相同，第二信号调节线12与输出端子4连接的一端END2的排布顺序和输出端子4的排布顺序相同，从而实现了扇出走线2与输出端子4位置顺序不一致，但将要传输的信号的顺序一致。需要说明的是，图13中并未绘制输出端子4和扇出走线2，仅在第二信号调节线12的两端标记了表示输出端子4和扇出走线2的排布顺序的数字标记。
在本申请的一些实施例中，参考图14所示，各第一翼型走线31的至少部分线段为蛇形结构。
上述至少部分线段的含义为：对于每一条第一翼型走线31，可以是第一翼型走线31的部分线段为蛇形结构；或者，可以是一整条第一翼型走线31为蛇形结构。
在示例性的实施例中，上述蛇形结构可以由多条曲线线段连接构成；或者，上述蛇形结构可以由多条折线线段连接构成。
在本申请的实施例中，参考图3所示，由于扇出区F中的部分扇出走线2通过翼型走线3绕线的方式与驱动芯片的输出端子4电连接，相较于未与翼型走线3电连接的扇出走线2的位于扇出区F的部分线段的长度d3，翼型走线3电连接的扇出走线2位于扇出区F的部分线段的长度d4很大程度上缩短，使得未与翼型走线3电连接的扇出走线2的电阻远大于与翼型走线3电连接的扇出走线2的电阻，造成显示面板中走线的电阻匹配性降低，造成信号传输不稳定，甚至造成显示面板的亮度不均一。
在本申请的实施例中，通过设置各第一翼型走线31的至少部分线段为蛇形结构，延长了与翼型走线3电连接的扇出走线2到输出端子4之间的走线的距离，从而可以一定程度上抵消与翼型走线3电连接的扇 出走线2缩短的长度，提高了不同走线之间的电阻匹配性，从而提高了信号传输的稳定性，提高了显示面板的亮度均一性。
需要说明的是，图14中仅以其中一条第一翼型走线31的部分线段为蛇形结构为例进行绘示。
在本申请的一些实施例中，部分扇出走线2的材料为第一导电材料，另一部分扇出走线2的材料为第二导电材料，且第一导电材料的电阻大于第二导电材料的电阻；
材料为第一导电材料的各扇出走线2中的一部分和第一翼型走线3电连接，材料为第二导电材料的各扇出走线2中的一部分和第一翼型走线3电连接；其中，材料为第一导电材料的扇出走线2电连接的第一翼型走线3为蛇形结构。
在示例性的实施例中，一部分扇出走线2和显示区AA中的源漏金属层同层制备，且材料相同，例如，其材料均为铝(Al)；另一部分扇出走线2和显示区AA中的栅线同层制备，且材料相同，例如，其材料均为钼(Mo)。
在实际应用中，综合考虑金属材料本身的电阻和走线的线宽、厚度因素对电阻的影响，与显示区AA中的栅线同层制备的部分扇出走线2的电阻较大。
其中，与显示区AA中的栅线同层制备的部分扇出走线2中，存在通过翼型走线3电连接输出端子4的扇出走线2；与显示区AA中的源漏金属层同层制备的部分扇出走线2中，也存在通过翼型走线3电连接输出端子4的扇出走线2。由于与显示区AA中的栅线同层制备的部分扇出走线2的电阻较大，再叠加上走线长度差异对电阻的影响，导致这部分扇出走线2与其它的扇出走线2的电阻差异更大，故而，将与高电阻的扇出走线2电连接的第一翼型走线3的至少部分线段设置为蛇形结构，一方面，提高不同走线之间的电阻匹配性，从而提高了信号传输的稳定性，提高了显示面板的亮度均一性；另一方面，避免将所有第一翼型走线3的至少部分线段设置为蛇形结构造成的制备工艺难度增加的问题。
在本申请的一些实施例中，参考图16和图19所示，驱动芯片IC还包括多个输入端子5，各输入端子5沿第二侧边102的延伸方向排布；
翼型走线3在显示面板的衬底上的正投影和输入端子5在衬底上 的正投影互不交叠。
在示例性的实施例中，各输出端子4沿平行于第三侧边103的延伸方向到第二侧边102之间的距离不完全相同。
示例性的，结合图4和图16所示，靠近驱动芯片两侧的各输出端子4沿平行于第三侧边103的延伸方向到输出端子5之间的距离大于位于中间位置的各输出端子4沿平行于第三侧边103的延伸方向到输出端子5之间的距离。
需要说明的是，对于如图16所示的驱动芯片，由于输出端子4所在区域和输入端子5所在区域之间的空间有限，通常设置翼型走线3从驱动芯片的第二侧边102所在的区域穿过，进而再与输出端子4电连接。
在本申请的一些实施例中，结合图3和图17所示，扇出走线2包括相连的第一扇出段201和第二扇出段202，第一扇出段201和显示区AA的信号线电连接，第二扇出段202和输出端子4电连接；
其中，第二扇出段202和显示区AA靠近扇出区F的边缘之间存在预设夹角；
预设夹角的正弦值等于所有第二扇出段202沿垂直于其延伸方向上所占区域的宽度d5和显示区AA沿平行于第一侧边101方向上的宽度的一半d6的比值。
在实际应用中，第二扇出段202沿垂直于其延伸方向上所占区域的宽度d5＝第二扇出段202的数量*(第二扇出段202的线宽+相邻两个第二扇出段202的间隙宽度)，即sina＝d5/d6，a＝arcsin(d5/d6)。
在本申请的一些实施例中，参考图3所示，各扇出走线2均存在一个第一拐点和一个第二拐点，所有扇出走线2的第一拐点的连线为第一线段L1，与翼型走线3电连接的各扇出走线2的第二拐点的连线为第二线段L2，未翼型走线3电连接的各扇出走线2的第二拐点的连线为第三线段L3，其中，第一线段L1平行于第二线段L2，且第二线段L2平行于第三线段L3。这样，可以提高扇出区F中各扇出走线2的规整度，降低设计难度、降低显示面板的制备工艺难度。
本申请的实施例提供了一种显示装置，包括如上的显示面板。
该显示装置可以是触控显示面板，以及包括这些触控显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
本申请的实施例提供的显示装置，在绑定区B中设置多条翼型走线3，通过翼型走线3从绑定区B(包括驱动芯片左右两侧和下侧的位置)中绕线的方式，使得部分扇出走线2通过翼型走线3与驱动芯片的输出端子4电连接，从而利用了绑定区B中未设置驱动芯片的区域，缩短了翼型走线3电连接的扇出走线2的长度，大大减少了扇出走线2在扇出区B中占据的空间，在实际应用中，再通过增大扇出走线2的线宽和相邻两条扇出走线2之间的距离，可以很大程度上减小扇出走线2自身的电阻，从而可以实现对显示区AA中各像素单元的高频充电，提高显示面板的充电率，缩短充电时间，降低显示面板的功耗。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种显示面板，其中，包括：
    显示区；
    位于所述显示区一侧的扇出区；
    位于所述扇出区远离所述显示区一侧的绑定区；所述绑定区中设置有驱动芯片，所述驱动芯片包括与所述扇出区相邻的第一侧边、与所述第一侧边相对的第二侧边、连接所述第一侧边和所述第二侧边的两个第三侧边；所述驱动芯片还包括多个输出端子，所述输出端子靠近所述第一侧边设置；
    所述显示面板包括：
    位于所述扇出区的多条扇出走线；
    至少位于所述绑定区的多条翼型走线；
    其中，部分所述扇出走线从所述扇出区延伸至所述第一侧边所在的区域，并与所述输出端子电连接；另一部分所述扇出走线通过所述翼型走线与所述输出端子电连接，且所述翼型走线从所述第一侧边、两个所述第三侧边和所述第二侧边中的至少一个侧边所在的区域穿过。
  2. 根据权利要求1所述的显示面板，其中，所述翼型走线从所述第一侧边所在的区域穿过。
  3. 根据权利要求1所述的显示面板，其中，所述翼型走线从所述第二侧边所在的区域穿过。
  4. 根据权利要求1所述的显示面板，其中，部分所述翼型走线从所述第二侧边所在的区域穿过，另一部分所述翼型走线从两个所述第三侧边中的至少一个侧边所在的区域穿过。
  5. 根据权利要求1所述的显示面板，其中，部分所述翼型走线从所述第一侧边所在的区域穿过，另一部分所述翼型走线从两个所述第三侧边中的至少一个侧边所在的区域穿过。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个接收端子，所述接收端子被配置为与所述驱动芯片的所述输出端子绑定在一起；所述接收端子在所述显示面板的衬底上的正投影和所述输出端子在所述衬底上的正投影交叠；部分所述接收端子和穿过所述第一侧边所在的区域的所述扇出走线电连接，另一部分所述接收端子和所述翼型走线电连接；
    其中，对于所述翼型走线电连接的所述接收端子，所述翼型走线在所述衬底上的正投影与至少一个所述接收端子在所述衬底上的正投影交叠。
  7. 根据权利要求6所述的显示面板，其中，所述翼型走线电连接的所述接收端子划分为沿所述第一侧边排布的第一组和沿所述第二侧边排布的第二组；第一组所述接收端子电连接的各所述翼型走线同层设置，第二组所述接收端子电连接的所述翼型走线包括第一翼型走线和第二翼型走线，且所述第一翼型走线和所述第二翼型走线位于不同层；
    其中，第一组所述接收端子电连接的所述翼型走线和第二组所述接收端子电连接的所述翼型走线中的各所述第二翼型走线同层设置。
  8. 根据权利要求7所述的显示面板，其中，所述翼型走线电连接的所述接收端子包括：
    位于所述衬底上的栅极层，包括相互独立且相对设置的两个导电垫；
    介质层，覆盖所述栅极层并暴露出所述导电垫的部分区域；
    源漏金属层，覆盖所述介质层并与所述导电垫暴露出的部分区域直接接触；
    电极层，覆盖所述源漏金属层，被配置为与所述驱动芯片的所述输出端子直接接触。
  9. 根据权利要求8所述的显示面板，其中，第一组所述接收端子电连接的所述翼型走线和第二组所述接收端子电连接的所述翼型走线中的各所述第二翼型走线均位于所述栅极层，且均从所述接收端子的两个所述导电垫之间的区域穿过。
  10. 根据权利要求9所述的显示面板，其中，对于第一组所述接收端子中的其中一个所述接收端子，一条所述翼型走线与其所述导电垫电连接、且第一组所述接收端子电连接的其它所述翼型走线在所述衬底上的正投影与其所述导电垫在所述衬底上的正投影互不交叠；
    对于第二组所述接收端子中的其中一个所述接收端子，一条所述第二翼型走线与其所述导电垫电连接、且第二组所述接收端子电连接的其它所述第二翼型走线在所述衬底上的正投影与其所述导电垫在所述衬底上的正投影互不交叠。
  11. 根据权利要求9或10所述的显示面板，其中，所述显示面板还包括多个备用接收端子，所述备用接收端子和所述接收端子的结构相同；
    与第一组所述接收端子同排设置的所述备用接收端子为第一备用接收端子，与第二组所述接收端子同排设置的所述备用接收端子为第二备用接收端子；
    其中，与第一组所述接收端子电连接的所述翼型走线中的至少部分从所述第一备用端子中的两个导电垫之间的区域穿过，与第二组所述接收端子电连接的所述翼型走线中的至少部分从所述第二备用端子中的两个导电垫之间的区域穿过。
  12. 根据权利要求1-10中任一项所述的显示面板，其中，所述扇出走线包括显示扇出走线和触控扇出走线；
    各所述触控扇出走线均从所述扇出区延伸至所述第一侧边所在的区域，并与所述输出端子电连接；部分所述显示扇出走线通过所述翼型走线与所述输出端子电连接。
  13. 根据权利要求1-10中任一项所述的显示面板，其中，所述翼型走线包括显示翼型走线和触控翼型走线；所述扇出走线包括显示扇出走线和触控扇出走线；
    部分所述显示扇出走线通过所述显示翼型走线和所述输出端子电连接，部分所述触控扇出走线通过所述触控翼型走线和所述输出端子电连接。
  14. 根据权利要求2-5中任一项所述的显示面板，其中，各所述翼型走线同层设置。
  15. 根据权利要求2-5中任一项所述的显示面板，其中，部分所述翼型走线同层设置，另一部分所述翼型走线包括第一翼型走线和第二翼型走线，且所述第一翼型走线和所述第二翼型走线位于不同层；
    其中，同层设置的各述翼型走线从所述绑定区延伸至所述扇出区，且包括依次连接的第一线段、第二线段、第三线段、第四线段和第五线段，其中，所述第一线段和所述第二线段位于所述绑定区，所述第三线段从所述绑定区延伸至所述扇出区，所述第四线段和所述第五线段位于所述扇出区；所述第一线段和所述扇出走线电连接，所述第五线段和所述输出端子电连接。
  16. 根据权利要求2-5中任一项所述的显示面板，其中，所述翼型走线包括第一翼型走线和第二翼型走线，所述第一翼型走线和所述第二翼型走线位于不同层；
    所述第一翼型走线沿第一方向延伸，所述第二翼型走线包括沿第二方向延伸的第一线段；所述第一翼型走线分别与所述扇出走线和所述第一线段电连接；所述第一方向为所述显示区指向所述绑定区的方向，所述第二方向和所述第一方向平行；
    其中，所述第一线段在所述显示面板的衬底上的正投影和与其电连接的所述第一翼型走线在所述衬底上的正投影交叠。
  17. 根据权利要求16所述的显示面板，其中，所述第二翼型走线还包括第二线段和第三线段，所述第二线段沿第三方向延伸，所述第一线段、所述第二线段和所述第三线段依次相连，所述第三线段和所述输出端子电连接；所述第三方向和所述第一方向相交；
    其中，在所述第三方向上，各所述第一翼型走线、各所述第一线段和各所述第三线段的排布顺序相同。
  18. 根据权利要求17所述的显示面板，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角为直角，所述第二线段的延伸线和所述第三线段的延伸线之间的夹角为直角；
    或者，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角为钝角，所述第二线段的延伸线和所述第三线段的延伸线之间的夹角为钝角，且两个所述钝角的角度相同；
    或者，所述第一线段的延伸线和所述第二线段的延伸线之间的夹角以及所述第二线段的延伸线和所述第三线段的延伸线之间的夹角中的其中一个为直角，另一个为钝角。
  19. 根据权利要求17所述的显示面板，所述第一线段和所述第二线段之间设置有第一拐角，所述第二线段和所述第三线段之间设置有第二拐角；
    各拐角中的至少部分为圆角。
  20. 根据权利要求19所述的显示面板，相邻两个所述第一拐角之间设置有至少一个岛状图形，相邻两个所述第一拐角之间的各所述岛状图形互不连接；
    和/或，相邻两个所述第二拐角之间设置有至少一个岛状图形，相邻两个所述第二拐角之间的各所述岛状图形互不连接。
  21. 根据权利要求17所述的显示面板，其中，部分所述第二翼型走线位于同一层，另一部分所述第二翼型走线位于同一层，且两部分所述第二翼型走线位于不同层；
    在所述第三方向上，将每两条所述第一线段划分为一组，每组所述第一线段走线组包括沿所述第三方向排布的外侧第一线段和内侧第一线段；
    其中，对于每组所述第一线段走线组，所述外侧第一线段电连接的所述第二线段在所述衬底上的正投影和所述内侧第一线段电连接的所述第二线 段在所述衬底上的正投影交叠。
  22. 根据权利要求17所述的显示面板，其中，包括测试单元和多条测试连接走线；
    所述测试单元位于各所述输出端子所在区域远离所述显示区的一侧；所述测试连接走线被配置为连接所述测试单元和所述输出端子；
    其中，电连接所述翼型走线的所述输出端子还和所述测试连接走线直接电连接。
  23. 根据权利要求22所述的显示面板，其中，电连接同一所述输出端子的所述翼型走线在所述衬底上的正投影和所述测试连接走线在所述衬底上的正投影部分交叠。
  24. 根据权利要求17所述的显示面板，其中，包括测试单元，所述测试单元划分为显示测试单元和触控测试单元；
    所述显示测试单元和所述触控测试单元中的至少一个位于所述显示区远离所述扇出区的一侧，剩余的一个位于所述扇出区或所述绑定区。
  25. 根据权利要求24所述的显示面板，其中，所述显示区远离所述扇出区的一侧的区域包括中央区和位于所述中央区两侧的两个转角区；所述显示测试单元和所述触控测试单元均包括多个测试子单元，所述测试子单元在所述衬底上的投影形状为矩形；
    其中，所述转角区的各所述测试子单元围绕所述显示区的边缘设置；所述转角区的各所述矩形的长边平行，或所述转角区的相邻两个所述矩形的长边之间存在预设角度的夹角。
  26. 根据权利要求16所述的显示面板，其中，包括多条第一信号调节线，所述第一信号调节线位于所述扇出走线和所述翼型走线之间；
    其中，在第三方向上，各所述扇出走线的排布顺序和各所述翼型走线的排布顺序不同；各所述第一信号调节线与所述扇出走线连接的一端的排布顺序和各所述扇出走线的排布顺序相同，各所述第一信号调节线与所述翼型走线连接的一端的排布顺序和各所述翼型走线的排布顺序相同；所述第三方向和所述第一方向相交。
  27. 根据权利要求16所述的显示面板，其中，包括多条第二信号调节线，对于通过所述第一侧边所在的区域与所述输出端子电连接的各所述扇出走线，所述扇出走线和所述输出端子之间还设置有所述第二信号调节线；
    其中，在第三方向上，各所述扇出走线的排布顺序和各所述输出端子的 排布顺序不同；各所述第二信号调节线与所述扇出走线连接的一端的排布顺序和各所述扇出走线的排布顺序相同，各所述第二信号调节线与所述输出端子连接的一端的排布顺序和各所述输出端子的排布顺序相同；所述第三方向和所述第一方向相交。
  28. 根据权利要求16所述的显示面板，其中，各所述第一翼型走线的至少部分线段为蛇形结构。
  29. 根据权利要求16所述的显示面板，其中，部分所述扇出走线的材料为第一导电材料，另一部分所述扇出走线的材料为第二导电材料，且所述第一导电材料的电阻大于所述第二导电材料的电阻；
    材料为所述第一导电材料的各所述扇出走线中的一部分和所述第一翼型走线电连接，材料为所述第二导电材料的各所述扇出走线中的一部分和所述第一翼型走线电连接；
    其中，材料为所述第一导电材料的所述扇出走线电连接的所述第一翼型走线为蛇形结构。
  30. 根据权利要求3或4所述的显示面板，其中，所述驱动芯片还包括多个输入端子，各所述输入端子沿所述第二侧边的延伸方向排布；
    所述翼型走线在所述显示面板的衬底上的正投影和所述输入端子在所述衬底上的正投影互不交叠。
  31. 根据权利要求1所述的显示面板，其中，所述扇出走线包括相连的第一扇出段和第二扇出段，所述第一扇出段和所述显示区的信号线电连接，所述第二扇出段和所述输出端子电连接；
    其中，所述第二扇出段和所述显示区靠近所述扇出区的边缘之间存在预设夹角；
    所述预设夹角的正弦值等于所有所述第二扇出段沿垂直于其延伸方向上所占区域的宽度和所述显示区沿平行于所述第一侧边方向上的宽度的一半比值。
  32. 一种显示装置，其中，包括如权利要求1-30中任一项所述的显示面板
PCT/CN2022/071014 2021-12-17 2022-01-10 显示面板及显示装置 WO2023108847A1 (zh)

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