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WO2022228072A1 - 电路板组件及其制作方法、终端及电子设备 - Google Patents

电路板组件及其制作方法、终端及电子设备 Download PDF

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Publication number
WO2022228072A1
WO2022228072A1 PCT/CN2022/085583 CN2022085583W WO2022228072A1 WO 2022228072 A1 WO2022228072 A1 WO 2022228072A1 CN 2022085583 W CN2022085583 W CN 2022085583W WO 2022228072 A1 WO2022228072 A1 WO 2022228072A1
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WO
WIPO (PCT)
Prior art keywords
conductor
substrate
circuit board
board assembly
package
Prior art date
Application number
PCT/CN2022/085583
Other languages
English (en)
French (fr)
Inventor
贺礼贤
胡丰田
姬忠礼
黄进辉
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2022228072A1 publication Critical patent/WO2022228072A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a circuit board assembly and a manufacturing method thereof, a terminal and an electronic device.
  • Embodiments of the present application provide a circuit board assembly, a manufacturing method thereof, a terminal, and an electronic device, which can improve the layout density of a multi-layer device stack structure and adapt to the miniaturization development trend of electronic devices.
  • the frame board includes upper-layer pads, lower-layer pads, and through holes penetrating the frame board and connecting the upper and lower-layer pads, the upper-layer pads are connected to the pads of the elevated board, and the lower-layer pads are connected to the pads of the main board , and then form the electrical interconnection from the main board to the elevated board through the through hole.
  • the height of the frame board is usually determined by the height of the taller device due to the difference in device height, which results in wasted space above the shorter device. Due to the limitation of the whole product space and the insufficient utilization of space in the vertical direction, the layout density of the multi-layer device stack structure gradually develops to a bottleneck.
  • a first aspect of the present application provides a circuit board assembly, the circuit board assembly comprising:
  • the package body is provided on the upper surface of the substrate, the package body includes a first package device area and a second package device area, and the first package device area and the second package device area have heights Difference.
  • the first packaged device area and the second packaged device area can be understood as two components constituting a package body, which can encapsulate or encapsulate electronic devices and interconnect structures.
  • the first packaged device region and the second packaged device region are disposed adjacent to each other, that is, the first packaged device region and the second packaged device region are connected to each other and together form a package body.
  • the height of the first packaged device region can be understood as the length from one end to the other end of the first packaged device region connected to the substrate. That is, the size of the first packaged device region in the direction perpendicular to the substrate, specifically, the size refers to the vertical distance from the surface of the first packaged device region facing away from the substrate to the upper surface of the substrate.
  • the height of the second package device area can be understood as the length from one end of the second package device area connected to the substrate to the other end. That is, the size of the second packaged device region in the direction perpendicular to the substrate, specifically, the size refers to the vertical distance from the surface of the second packaged device region away from the substrate to the upper surface of the substrate.
  • the first packaged device region and the second packaged device region have a height difference, that is, when both the first packaged device region and the second packaged device region are laid out on the upper surface of the substrate, the first packaged device region is far away from the surface of the substrate.
  • the vertical distance from the upper surface of the substrate and the vertical distance between the surface of the second package device region remote from the substrate and the upper surface of the substrate are not the same. In other words, when the package body is disposed on the substrate, a rugged visual effect can be formed.
  • the technical solution of the present application does not limit the number of the first packaged device area and the second packaged device area, which can be configured into one or more as required.
  • the first packaged device area and the second packaged device area are arranged on the substrate, and the first packaged device area and the second packaged device area have a height difference, the first packaged device area and the second packaged device area.
  • the height can show uneven appearance. That is, it is possible to make the entire package have a undulating appearance.
  • the heights of the various parts of the package can assume a layout arrangement with stepped heights.
  • a package body with a suitable height can be arranged in a targeted manner, which effectively avoids the problem of material waste caused by setting the whole package body to a uniform height, which is conducive to reducing materials. and production costs.
  • using the height difference of each part of the package body to realize the mismatched packaging of the internal high and low devices can minimize the height of the high device as a reference to make the entire package set to a uniform height, which is caused by the upper part of the short device. of space wasted. It is beneficial to rationally utilize the space perpendicular to the substrate direction, solve the problem of stacking space waste caused by the large difference in device height, and maximize the space utilization when applied to the multi-layer stack structure, improving the device layout of multi-layer device stacking density.
  • a package body with a step height enables more differentiated and diversified device configurations than a planar structure when devices are reassembled thereon. That is, a relatively taller device can be assembled where the vertical distance between the package body and the substrate is smaller, and a relatively shorter device can be assembled where the vertical distance between the package body and the substrate is larger, so that devices of different heights are assembled thereon. , which can present a relatively flat layout setting, which is beneficial to compress the overall thickness of the circuit board assembly in a limited space layout, and makes it possible to lay out more layers of devices in the same space.
  • a frame plate is arranged on the substrate to realize interconnection, and more non-functional pins for enhancing reliability and realizing electromagnetic shielding performance are arranged on the frame plate. Disposing a highly reliable package on the substrate enables the package itself to serve as electromagnetic shielding performance, thereby minimizing the number of non-functional pins used for electrical shielding and reliability enhancement. That is, it is beneficial to minimize the non-functional pins of the circuit board assembly, so as to reduce the waste of board area.
  • the first packaged device region is covered with a first device, the first device is provided on the upper surface of the substrate, and the second packaged device region is covered with a second device.
  • a device, the second device is provided on the upper surface of the substrate, and the first device and the second device have a height difference.
  • the height of the first device can be understood as the size of the first device in the direction perpendicular to the substrate. Specifically, the size refers to: on the first device body, the point farthest from the substrate to The vertical distance of the substrate.
  • the height of the second device can be understood as the dimension of the second device in the direction perpendicular to the substrate. Specifically, the dimension refers to the vertical distance from the point farthest from the substrate on the body of the second device to the substrate.
  • the first device and the second device are arranged on the upper surface of the substrate and have a height difference between them. That is, the first device and the second device have height differences, so that when the first device and the second device are both arranged on the surface of the substrate, the vertical distance between the surface of the first device away from the substrate and the substrate and the distance between the surface of the first device away from the substrate and the substrate and the distance between the second device away from the substrate.
  • the vertical distance between the surface and the substrate is not the same. In other words, when the first device and the second device are laid out on the substrate, different visual effects can be formed.
  • the height of the first device is less than the height of the second device. That is, the first device is a relatively short device, and the second device is a relatively tall device.
  • the first device may be, but not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, or a power management chip.
  • the second device may be, but not limited to, a capacitor, an inductor, a crystal oscillator, an NFC (Near Field Communication, near field communication) control chip, a SOC or a UFS (Universal Flash Storage, universal flash storage) chip, and the like.
  • the number of the first devices may be one or more.
  • the multiple first devices may be devices of the same type, or may be devices of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device can be selected according to the actual situation, which is not strictly limited.
  • the number of the second devices may also be one or more.
  • the multiple second devices may be of the same type or of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the second device can be selected according to the actual situation, which is not strictly limited.
  • the circuit board assembly further includes a first conductor and a second conductor, the first conductor is located in the first package device area, and one end of the first conductor is connected to the substrate, The other end is connected to the outer surface of the first package device area, the second conductor is located in the second package device area, one end of the second conductor is connected to the substrate, and the other end is connected to the second package
  • the outer surfaces of the device regions are connected, and the first conductor and the second conductor have a height difference.
  • the first conductor is located in the area where the first device is located on the upper surface of the substrate, one end is connected to the substrate, and the other end extends away from the substrate, wherein the first conductor can be an electrical device that can independently realize the interconnection function.
  • the connection structure, or the first conductor can also be an electrical connection structure assembled with other conductive structures to realize the interconnection function.
  • the height of the first conductor can be understood as the length from one end of the first conductor connected to the substrate to the other end, that is, the dimension of the first conductor in the direction perpendicular to the substrate.
  • the second conductor is located in the area where the second device is located on the upper surface of the substrate, one end is connected to the substrate, and the other end extends away from the substrate, wherein the second conductor may be an electrical connection structure capable of independently realizing the interconnection function, or, The second conductor may also be an electrical connection structure assembled with other conductive structures to achieve an interconnection function.
  • the height of the second conductor can be understood as the length from one end of the second conductor connected to the substrate to the other end, that is, the dimension of the second conductor in the direction perpendicular to the substrate.
  • the first conductor and the second conductor have a height difference, wherein the height can be understood as a dimension perpendicular to the direction of the substrate. That is, the first conductors and the second conductors have height differences, so that when the first conductors and the second conductors are simultaneously arranged on the surface of the substrate, visual effects of different heights can be formed.
  • the length from one end to the other end of the first conductor connected to the substrate is not the same as the length from one end to the other end of the second conductor connected to the substrate.
  • the first conductors and the second conductors arranged in the corresponding regions also have corresponding height differences.
  • an electrical connection structure with a higher height is arranged in the region where the tall device is arranged, and an electrical connection structure with a lower height is arranged in the region where the short device is arranged.
  • the heights of the first conductor and the second conductor can be flexibly adjusted according to devices of different heights, so as to fully adapt to the layout differences of tall and short devices, and avoid short devices caused by setting the first conductor and the second conductor to the same height
  • the waste of space above is also beneficial to reduce processing, production and material management costs, and has good reliability.
  • the height of the first conductor is less than the height of the second conductor. That is, the first conductor is an electrical connection structure with a relatively high height, and the second conductor is an electrical connection structure with a relatively low height.
  • the number of the first conductors may be multiple, the multiple first conductors are arranged at intervals in the region where the first device is located, and the heights of the multiple first conductors are the same.
  • the number of the second conductors may be multiple, the multiple second conductors are arranged at intervals in the area where the second device is located, and the heights of the multiple second conductors are the same.
  • the first conductors of the same height are uniformly arranged in the area where the short device is located, and the second conductors of the same height are uniformly arranged in the area where the tall device is located, which can avoid the manufacturing difficulty and complexity caused by the different heights of the conductors in the same area.
  • the degree of increase makes the processing easier and faster.
  • the first encapsulated device region encapsulates the first device and encapsulates the first device on the substrate and surrounds the first conductor. That is, the first conductor is located in the first packaging device area, and one end is connected to the substrate, and the other end is connected to the outer surface of the first packaging device area, wherein the other end of the first conductor is connected to the outer surface of the first packaging device area.
  • the connection includes the direct connection of the two or the indirect connection of the two through an intermediary.
  • the second encapsulated device region encapsulates the second device to encapsulate the second device on the substrate and surrounds the second conductor. That is, the second conductor is located in the second packaging device area, and one end is connected to the substrate, and the other end is connected to the outer surface of the second packaging device area, wherein the other end of the second conductor is connected to the outer surface of the second packaging device area.
  • the connection includes the direct connection of the two or the indirect connection of the two through an intermediary.
  • the outer surface of the package body can be understood as the surface of the package body facing away from the substrate, which includes the outer surface of the first packaged device region and the outer surface of the second packaged device region.
  • the outer surface of the first packaged device region can be understood as the surface of the first packaged device region facing away from the substrate.
  • the outer surface of the second packaged device region can be understood as the surface of the second packaged device region facing away from the substrate.
  • the height of the first conductor and the second conductor will vary with the height of the first device and the second device in the region.
  • the height of the first conductor will be smaller than that of the second device. The height of the second conductor and vice versa.
  • the first device and the second device with different heights on the substrate, and arranging the first conductor in the area where the first device is located, and arranging the second conductor in the area where the second device is located, it is possible to make the package no.
  • the height of the first packaged device region of one device is adapted to the height of the first conductor
  • the height of the second packaged device region of the second device is adapted to the height of the second conductor. Since the first conductor and the second conductor are different in height, the heights of the first packaged device region and the second packaged device region can take the height difference of the first conductor and the second conductor as a reference to present uneven appearance. That is, it is possible to make the entire package have a undulating appearance.
  • the height of each part of the package body can exactly correspond to the height of the packaged device, so that the package body can adapt to the height difference of tall and short devices and also present a layout arrangement with stepped heights.
  • conductors and packages with suitable heights can be arranged in a targeted manner according to the height difference of the devices, which effectively avoids the problem of material waste caused by setting the package and conductors to a uniform height as a whole, which is beneficial to reduce material and cost. Cost of production.
  • the circuit board assembly further includes a first via hole and a second via hole, and the first conductor and the outer surface of the first package device area pass through the first via hole connection, the second conductor is connected with the outer surface of the second package device region through the second via hole. That is, the first via is connected between the first conductor and the outer surface of the first package device area, and the second via is connected between the second conductor and the second package between the outer surfaces of the device area.
  • the first via hole is filled with a first electroplating metal, and the first electroplating metal connects the first conductor and the outer surface of the first package device area;
  • the second via hole is filled with a second electroplating metal A metal, the second plated metal connects the second conductor and the outer surface of the second package device area.
  • the electrical connection between the surface of the package body and the internal device can be realized, and the interconnection structure passing through the package body can be compared with the existing one. It is technically possible to pass through thicker packages.
  • the first conductor may be a gold wire or a needle
  • the second conductor may be a gold wire or a needle.
  • the filling of the first filling metal in the first via hole can be understood as an electrical connection structure formed by filling conductive metal in the hole-like structure
  • the filling of the second filling metal in the second via hole can also be understood An electrical connection structure with conductive properties formed for filling conductive metal in a hole-like structure.
  • the heights of the first via hole and the second via hole are the same, so that both processing and manufacturing are easier.
  • the heights of the first via hole and the second via hole are different, so that the height of the metal via hole can be adjusted correspondingly according to the height of each conductor, which is highly flexible.
  • the height of the first via hole can be understood as the length from one end of the first via hole connected to the first conductor to the other end, that is, the dimension of the first via hole in a direction perpendicular to the substrate.
  • the height of the second via can be understood as the length from one end of the second via connected to the second conductor to the other end, that is, the dimension of the second via in the direction perpendicular to the substrate.
  • the layout positions of the first via hole and the second via hole are not affected, and can be arranged at any position in the package according to application requirements.
  • the board area and space occupied by the frame board can be saved, the overall outlet area can be increased, and the layout area of the device can be increased.
  • the devices arranged inside the package can be routed to the nearest location, which is beneficial to simplify the complexity of the wiring and realize the shortest connection of the wiring.
  • the first via hole, the first plated metal and the first conductor are connected to form a first conductive structure
  • the second via hole, the second plated metal and the The second conductor is connected to form a second conductive structure
  • the aspect ratio of the first conductive structure is in the range of 5:1 to 15:1
  • the aspect ratio of the second conductive structure is 5:1 ⁇ 15:1 range.
  • the aspect ratio of the first conductive structure can be understood as the ratio of the depth of the first conductive structure to the width of the first conductive structure, specifically the value obtained by dividing the depth of the first conductive structure by the width of the first conductive structure.
  • the depth of the first conductive structure can be understood as the length from one end of the first conductive structure connected to the substrate to the other end (which can be equal to the height of the first conductive structure), and the width of the first conductive structure can be understood as a length parallel to the substrate
  • the first conductive structure is cut from the reference plane, and the cut-out diameter (width) dimension of the cross-section.
  • the specific value of the aspect ratio of the first conductive structure can be either an integer value or a decimal value, as long as it falls within the range of 5:1 to 15:1 (including the endpoint value) That is, there is no strict restriction on this.
  • the aspect ratio of the second conductive structure can be understood as the ratio of the depth of the second conductive structure to the width of the second conductive structure, specifically the value obtained by dividing the depth of the second conductive structure by the width of the second conductive structure.
  • the depth of the second conductive structure can be understood as the length from one end of the second conductive structure connected to the substrate to the other end (which can be equal to the height of the second conductive structure), and the width of the second conductive structure can be understood as a length parallel to the substrate
  • the second conductive structure is cut from the reference plane, and the diameter (width) dimension of the cut-out cross section.
  • the specific value of the aspect ratio of the second conductive structure can be either an integer value or a decimal value, as long as it falls within the range of 5:1 to 15:1 (including the endpoint value) That is, there is no strict restriction on this.
  • the position of the outgoing wires is limited by the outer circumference of the board surface, and the non-outgoing wire area occupies a larger area of the board surface, which is caused by arranging the frame plate on the substrate to realize the interconnection of the upper and lower layers.
  • the first conductive structure and the second conductive structure that can realize double-sided interconnection are arranged inside the package body, so that the layout position of the I/O (Input/Output, input/output) outgoing line is not affected, and can be adjusted according to the application requirements.
  • the board area and space occupied by the frame board can be saved, the overall outlet area can be increased, and the layout area of the device can be increased.
  • the devices arranged inside the package can be routed to the nearest location, which is beneficial to simplify the complexity of the wiring and realize the shortest connection of the wiring.
  • the arrangement of the first conductive structure and the second conductive structure can also break through the layout in which the interconnection structures in the prior art cannot be further densely arranged, so that the distance between the two adjacent interconnection structures can be reduced. It can be shortened to the maximum extent, which is conducive to the realization of high-density arrangement.
  • the center-to-center distance between two adjacent conductive structures is less than or equal to 0.4 mm.
  • the conductive structure formed by the conductor and the metal via can achieve a higher aspect ratio, and make the interconnect structure through the package body compared with the prior art. In terms of being able to pass through a thicker package, it is beneficial to adapt to the application requirements of multiple scenarios.
  • the first conductor extends from the substrate in a direction perpendicular to the substrate
  • the second conductor extends from the substrate in a direction perpendicular to the substrate
  • the height difference between the first conductor and the second conductor is greater than or equal to 0.2 mm.
  • the height of the first conductor can be understood as the length from one end of the first conductor connected to the substrate to the other end, that is, the dimension of the first conductor perpendicular to the direction of the substrate.
  • the height of the second conductor can be understood as the length from one end of the second conductor connected to the substrate to the other end, that is, the dimension of the second conductor perpendicular to the direction of the substrate.
  • the height difference between the first conductor and the second conductor can be understood as a value obtained by subtracting the heights of the two. That is, the difference between the distance from one end of the first conductor connected to the substrate to the other end and the distance from one end of the second conductor connected to the substrate to the other end.
  • the first conductor and the second conductor whose height difference satisfies this range can fully adapt to the layout difference of tall and short devices, which is beneficial to solve the problem of wasting stacking space caused by the large height difference of devices, and improve the device stacking of multi-layer devices. layout density.
  • the circuit board assembly further includes a circuit structure provided on the outer surface of the package body, the circuit structure includes a first pad and a second pad, the first pad is provided On the outer surface of the first package device area and electrically connected with the first conductor, the second pad is provided on the outer surface of the second package device area and electrically connected with the second conductor, so The vertical distance between the first pad and the substrate is different from the vertical distance between the second pad and the substrate.
  • the outer surface of the package body can be understood as the surface of the package body facing away from the substrate, which includes the outer surface of the first packaged device region and the outer surface of the second packaged device region.
  • the outer surface of the first packaged device region can be understood as the surface of the first packaged device region facing away from the substrate.
  • the outer surface of the second packaged device region can be understood as the surface of the second packaged device region facing away from the substrate.
  • first pad and the second pad are both functional pads, which can play the roles of electrical connection, mechanical fixation, and the like. That is to say, if a plurality of components (such as circuit boards and electronic components) are connected through the functional pads, electrical signals between the plurality of components can be transmitted through the functional pads.
  • electronic devices can be arranged on both the first pad and the second pad, so that not only the package body has electronic devices inside, but also devices can be continuously stacked outside the package body to form a multi-layer stack structure, which is beneficial to achieve high density of devices Arrange.
  • the devices of different heights can be arranged on planes with different distances from the substrate, so that the vertical distance between the pads on the different planes can be utilized to offset the devices to the greatest extent.
  • the pads in the prior art that can only set the devices on the same plane, it can effectively avoid the increase in the number of device stacks under the constraints of the same space size and the number of devices, which is beneficial to the high density of the devices. Arrangement.
  • the circuit board assembly further includes a third device and a fourth device;
  • the height of the first device is smaller than the height of the second device, and the height of the third device is smaller than the height of the fourth device;
  • the third device is connected to one of the first pad and the second pad
  • the fourth device is connected to the other of the first pad and the second pad.
  • the first device and the second device constitute the first layer device of the circuit board assembly
  • the circuit board assembly further includes a second layer device
  • the second layer device is arranged on the surface of the package body away from the substrate, so as to realize two layers.
  • Device stacking architecture Therefore, the secondary assembly of the device on the package body is equivalent to increasing the layout area of the package body away from the surface of the substrate, which can add one layer of devices to the circuit board assembly as a whole, effectively improving the arrangement density of devices under the multi-layer structure.
  • the second-layer device may be an electronic device of the same height, or may be an electronic device with a height difference.
  • the following will take the second-layer device as an electronic device with a height difference as an example, but it should be understood that, Not limited to this.
  • the second-layer device includes a third device and a fourth device
  • the height of the third device can be understood as the dimension of the third device in the direction perpendicular to the substrate.
  • the dimension refers to: on the body of the third device , the vertical distance from the point farthest from the substrate to the point closest to the substrate.
  • the height of the fourth device can be understood as the size of the fourth device in the direction perpendicular to the substrate.
  • the size refers to: the vertical distance from the point farthest from the substrate to the point closest to the substrate on the body of the fourth device .
  • the third device and the fourth device have a height difference, that is, the third device and the fourth device have a height difference, and in comparison, one is a tall device and the other is a short device.
  • the third device may be, but not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, a power management chip, or the like.
  • the fourth device may be, but is not limited to, a capacitor, an inductor, a crystal oscillator, an NFC control chip, a SOC or a UFS chip, and the like.
  • the number of the third devices may be one or more.
  • the multiple third devices may be of the same type, or may be of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device can be selected according to the actual situation, which is not strictly limited.
  • the number of the fourth device may also be one or more.
  • the plurality of fourth devices may be devices of the same type, or may be devices of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the fourth device can be selected according to the actual situation, which is not strictly limited.
  • the terminal or electronic device to which the circuit board assembly is applied needs to have more diversified functions, more and more electronic components are arranged.
  • the space of the circuit board assembly can be laid out in a targeted manner according to the height difference between the third device and the fourth device, which is beneficial to reduce the space occupied by the circuit board assembly 100 . space, to meet the development trend of thinning and high-density circuit board components.
  • the height of the first device is smaller than the height of the second device, and the height of the third device is smaller than the height of the fourth device as an example, but it should be understood that it is not limited thereto.
  • the third device is arranged on the first pad, and the fourth device is arranged on the second pad.
  • a device layout is formed in which the first device and the fourth device are arranged correspondingly, and the second device and the third device are arranged correspondingly. That is to say, it is possible to realize the height distribution of the short devices inside the package body and the high devices outside the package body, and the high devices inside the package body and the short devices outside the package body.
  • the device can be assembled on the surface of the package body in a relatively flat layout, which is beneficial to compress the overall thickness of the circuit board assembly in the limited spatial layout.
  • it can make full use of the vertical space to maximize the space utilization rate, so as to break through the stacking space waste problem caused by the large difference in device height under the multi-layer device stacking structure, so that more layers of devices can be laid out in the same space.
  • the possibility of increasing the device layout density of multi-layer device stacking architectures becomes a reality.
  • the third device is arranged on the first pad, and the fourth device is arranged on the second pad. Therefore, the height difference between the first packaged device area and the second packaged device area can be used to offset the height difference between the devices to the greatest extent.
  • the devices can only be arranged on the same plane. Under the constraints of the same space size and the number of devices, the increase in the number of device stacks is effectively avoided, which is beneficial to the high-density arrangement of the devices.
  • the circuit structure further includes a connection pad, the connection pad covers the connection between the first packaged device region and the second packaged device region, and the connection pad is connected to the The first conductive structure or the second conductive structure is electrically connected.
  • connection pads are functional pads, which can perform functions such as electrical connection and mechanical fixation. That is to say, if a plurality of components (such as circuit boards and electronic components) are connected through the functional pads, electrical signals between the plurality of components can be transmitted through the functional pads.
  • electronic devices can be arranged on the connection pads, so that not only electronic devices are provided inside the package body, but devices can also be continuously stacked outside the package body to form a multi-layer stack structure, which is conducive to realizing high-density arrangement of devices.
  • connection pads covering the connection between the first packaged device region and the second packaged device region are also stepped.
  • the connection pads can be distinguished from the planar pads and present a three-dimensional shape, that is, the connection pads can be arranged at the steps to adapt to the step change at the transition of the package body, thereby effectively avoiding the package body. Waste of layoutable device area and increased pad count.
  • the increase in the number of pads can be equivalent to an increase in the number of devices that can be arranged, which is equivalent to improving the layout density of the device, which is beneficial to meet the high-density layout requirements of the device.
  • the line structure further includes a sub-line structure.
  • the circuit structure further includes a plurality of sub-circuit structures and an insulating layer disposed between two adjacent sub-circuit structures, the insulating layer includes a connecting structure, and two adjacent sub-circuit structures pass through the insulating layer.
  • the connection structure is electrically connected.
  • the circuit structure has a plurality of sub-circuit structures arranged in layers, there is an insulating layer between two adjacent sub-circuit structures, and two adjacent sub-circuit structures pass through the The connection structures of the insulating layers are electrically connected to each other.
  • composition of the circuit structure can be flexibly adjusted according to the wiring requirements of the circuit board components, which is beneficial to adapt to the application requirements in multiple scenarios.
  • one or more stepped structures are formed on the outer surface of the package body.
  • the outer surface of the package body can be understood as the surface of the package body facing away from the substrate.
  • the surface of the package body facing away from the substrate may form one or more components. a step structure.
  • the stepped structure with the stepped height can provide more differentiated and diversified device configurations than the planar structure when the device is reassembled thereon. That is, a relatively taller device can be assembled where the vertical distance between the stepped structure and the substrate is smaller, and a relatively shorter device can be assembled where the vertical distance between the stepped structure and the substrate is larger, so that devices of different heights are assembled thereon. , which can present a relatively flat layout setting, which is beneficial to compress the overall thickness of the circuit board assembly in a limited space layout, and makes it possible to lay out more layers of devices in the same space.
  • the present application further provides a method for manufacturing a circuit board assembly, and the method for manufacturing the circuit board assembly includes:
  • a package body is formed on the upper surface of the substrate, wherein the package body includes a first package device region and a second package device region, and the first package device region and the second package device region have a height difference.
  • the method further includes:
  • a first device and a second device are mounted on the upper surface of the substrate, wherein the first device and the second device have a height difference.
  • the method further includes:
  • a first conductor is formed in the region where the first device is located, and a second conductor is formed in the region where the second device is located, wherein one end of the first conductor is connected to the substrate, and the other end faces away from the substrate extending, one end of the second conductor is connected to the substrate, the other end extends away from the substrate, and the first conductor and the second conductor have a height difference.
  • a first conductor may be formed in the region where the first device is located, and a second conductor may be formed in the region where the second device is located. conductor.
  • the first packaged device region covers the first device, and the outer surface of the first packaged device region is connected to the first conductor, the second packaged device region covers the second device, and the second packaged device region covers the second device. An outer surface of the packaged device region is connected to the second conductor.
  • the method further includes:
  • a first via hole exposing the first conductor and a second via hole exposing the second conductor are formed on the outer surface of the first package device region and the outer surface of the second package device region, respectively;
  • a first conductive structure is formed, and the second via hole, the second electroplating metal and the second conductor are connected to form a second conductive structure.
  • the method further includes:
  • a circuit structure electrically connected to the first conductive structure and the second conductive structure is formed on the outer surface of the package body.
  • the method further includes:
  • a second-layer device is mounted on the circuit structure, wherein the first device and the second device constitute a first-layer device of the circuit board assembly.
  • the extension direction of the first conductor is perpendicular to the substrate, and the extension direction of the second conductor is perpendicular to the substrate.
  • the height difference between the first conductor and the second conductor is greater than or equal to 0.2 mm.
  • the number of the first conductive structures is multiple, and the aspect ratio of one or more of the multiple first conductive structures is in the range of 5:1 ⁇ 15:1
  • the number of the second conductive structures is multiple, and the aspect ratio of one or more of the multiple second conductive structures is in the range of 5:1 ⁇ 15:1.
  • the present application further provides a terminal, the terminal includes a display screen, an antenna module and the circuit board assembly as claimed in the claims, wherein the display screen and the antenna module are both electrically connected to the circuit board components.
  • the present application further provides an electronic device, the electronic device includes a housing and the above-mentioned circuit board assembly, and the circuit board assembly is provided in the housing.
  • FIG. 1 is a schematic structural diagram of a terminal provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 4 is another schematic structural diagram of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a package body of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 6 is another schematic structural diagram of the package body of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of the package body of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a connection surface of a package body of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of the connection surface of the package body of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 10 is another structural schematic diagram of the connection surface of the package body of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a circuit structure of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of the circuit board assembly provided by the first embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of the circuit board assembly provided by the second embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of the circuit board assembly provided by the third embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of the circuit board assembly provided by the fourth embodiment of the present application.
  • FIG. 18 is a schematic flowchart of a method for manufacturing a circuit board assembly provided by an embodiment of the present application.
  • Fig. 19 is a state schematic diagram of the manufacturing method of the circuit board assembly shown in Fig. 18;
  • FIG. 20 is a schematic diagram of a step of a package body of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 21 is another schematic flowchart of the manufacturing method of the circuit board assembly provided by the embodiment of the present application.
  • FIG. 22 is a schematic flowchart of a circuit structure of a circuit board assembly provided by an embodiment of the present application.
  • Fig. 23 is a schematic diagram of a step of the circuit structure of the circuit board assembly shown in Fig. 22;
  • FIG. 24 is another schematic flowchart of the circuit structure of the circuit board assembly provided by the embodiment of the present application.
  • Fig. 25 is another schematic diagram of steps of the circuit structure of the circuit board assembly shown in Fig. 24;
  • FIG. 26 is another schematic flowchart of a method for manufacturing a circuit board assembly provided by an embodiment of the present application.
  • FIG. 27 is another schematic flowchart of the method for fabricating the circuit board assembly provided by the embodiment of the present application.
  • Plural means two or more than two.
  • connection It should be understood in a broad sense. For example, when A is connected to B, it can be directly connected to A and B, or it can be indirectly connected to A and B through an intermediary.
  • the embodiments of the present application provide a terminal 200 and an electronic device 300 , which can improve the layout density of the multi-layer device stack structure and adapt to the miniaturization development trend of electronic products.
  • the terminal 200 may be, but not limited to, a mobile phone, a tablet computer, and a notebook computer.
  • the electronic device 300 can be, but is not limited to, a power module, a smart bracelet, a smart watch, a server, a router, a switch, a supercomputer, an AI device, and a data center.
  • the terminal 200 with a wide range of users and rich application scenarios, such as a mobile phone, is used as an example for description, but it is not limited thereto.
  • the terminal 200 may include a middle frame 210 , a display screen (not shown), a front cover 230 , a rear cover 240 , an antenna module 250 and a circuit board assembly 100 .
  • the front cover 230 and the rear cover 240 are respectively connected to opposite sides of the middle frame 210 to cooperate with the middle frame 210 to form an accommodating space for the terminal 200 , and the accommodating space can install various components of the terminal 200 , such as circuits Board assembly 100 .
  • the display screen is fixed to the front cover 230 and electrically connected to the circuit board assembly 100 , and can display visual information such as images, colors, and text.
  • the antenna module 250 may be fixed to the middle frame 210 or to the accommodating space of the terminal 200 , and is electrically connected to the circuit board assembly 100 .
  • the circuit board assembly 100 can send and receive electromagnetic signals to the antenna module 250 , and the antenna module 250 can radiate electromagnetic waves according to the received electromagnetic signals or send electromagnetic signals to the circuit board assembly 100 according to the received electromagnetic waves, so as to realize the sending and receiving of electromagnetic signals.
  • the terminal 200 can transmit and receive electromagnetic signals under the action of the antenna module 250, thereby achieving high gain and wide coverage of the electromagnetic signals.
  • FIG. 1 is only to schematically describe the connection relationship between the middle frame 210 , the display screen, the front cover 230 , the rear cover 240 , the antenna module 250 and the circuit board assembly 100 , not the connection position of each device ,
  • the specific structure and quantity are specifically limited.
  • the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the terminal 200 .
  • the terminal 200 may include more or less components than those shown in the drawings, or combine some components, or separate some components, or arrange different components.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the front cover 230 is a cover facing the user's face when the user holds the mobile phone, and a display screen can be provided to present visual information such as images, colors, and text.
  • the back cover 240 is a cover that faces away from the user's face when the user holds the mobile phone, and can capture still images or dynamic videos behind the mobile phone by setting a camera module as a rear camera.
  • the circuit board assembly 100 is an assembly structure formed by assembling a circuit board and various electronic components, and can be electrically interconnected with various electronic components in the terminal 200 to achieve corresponding functions.
  • the reduction of the lateral dimension of the circuit board assembly 100 makes the layout area of the single-layer board structure unable to meet the layout requirements of all devices, so that the vertically stacked multi-layer board structure emerges as the times require.
  • the layout density of the multi-layer device stack structure gradually develops to a bottleneck.
  • the circuit board assembly 100 provided in the embodiment of the present application can not only realize the vertical stacking of multi-layer devices, but also can maximize the layout area of the devices under the trend of miniaturization of the overall space inside the terminal 200, so as to realize the use of space In exchange for area, the purpose of increasing the layout density of the device.
  • the electronic device 300 may include a housing 310 and a circuit board assembly 100 .
  • the housing 310 is the appearance structure of the electronic device 300 , and can accommodate and encapsulate various components of the electronic device 300 , so that the various components of the electronic device 300 are protected from external dust, water vapor, etc., and have a good protection function.
  • the circuit board assembly 100 is disposed inside the housing 310 , and is an assembly structure formed by assembling the circuit board and various electronic components, and can be electrically interconnected with various electronic devices in the electronic device 300 to achieve corresponding functions.
  • FIG. 2 is only to schematically describe the connection relationship between the housing 310 and the circuit board assembly 100 , and not to specifically limit the connection position, specific structure and quantity of each device.
  • the structures illustrated in the embodiments of the present application do not constitute a specific limitation of the electronic device 300 .
  • the electronic device 300 may include more or less components than shown, or combine some components, or separate some components, or arrange different components.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the electronic device 300 is gradually developing towards the trend of miniaturization and ultra-thinning, which promotes the continuous reduction of the thickness of the circuit board assembly 100 .
  • the space in the vertical direction of the multi-layer board structure is not fully utilized, and the vertical connection structure connecting the adjacent two-layer boards will also occupy the board layout area, which easily leads to the inability to obtain the board-level layout area.
  • further improvement That is, the conventional multi-layer board structure has been difficult to meet the development requirements of the high-density arrangement of devices and the thinning of the multi-layer board structure at the same time.
  • the circuit board assembly 100 provided by the embodiment of the present application can not only realize the vertical stacking of multi-layer devices, but also can maximize the use of the vertical direction under the trend of miniaturization and ultra-thinning of the internal space of the electronic device 300 In order to increase the layout area of the device and improve the layout density of the device.
  • circuit board assembly 100 provided by the embodiments of the present application is applied to the terminal 200 or the electronic device 300, it is beneficial to realize the vertical stacking of multilayer devices, and can eliminate the problem of wasting space due to insufficient utilization of stacking space The possibility of occurrence is reduced to a minimum, and the layout density of the device under the multi-layer device stack structure is effectively improved, which will be described in detail below.
  • the circuit board assembly 100 includes a substrate 10 , a first device 21 , a second device 22 , a first conductor 31 , a second conductor 32 , a package body 40 and a circuit structure 50 .
  • the substrate 10 includes an upper surface 101 and a lower surface 102 disposed opposite to each other, which can be used to carry electronic components or other printed circuit boards (PCBs).
  • the substrate 10 may be, but is not limited to, a printed circuit board, a flexible circuit board, or a rigid-flex circuit board.
  • the substrate 10 when the substrate 10 is only used to carry electronic components, it can be configured as a single-sided board, that is, a circuit board capable of carrying electronic components on one side, according to the number of electronic components carried on the substrate 10 , thereby
  • the circuit board assembly 100 is made to appear as a whole as a single-layer circuit board structure with a single-layer device.
  • it can also be configured as a double-sided board, that is, a circuit board capable of carrying electronic components on both sides, so that the circuit board assembly 100 as a whole presents a double-layered circuit board structure with double-layered devices.
  • the substrate 10 can be used as a stand-alone structure to present a single-layer or two-layer device structure by itself, or it can also be assembled to other circuit boards to present a multi-layer device stack structure.
  • the substrate 10 When the substrate 10 is used to carry other circuit boards, it can be used as a main circuit board and carry one or more circuit boards thereon, thereby realizing the stacking of multi-layer circuit boards. Alternatively, it can also be used as a transition circuit board to carry one or more circuit boards and be connected with the main circuit board, thereby realizing the stacking of multi-layer circuit boards.
  • the substrate 10 may be, but not limited to, a motherboard, a radio frequency (RF) board, and an application processor (AP) board.
  • the radio frequency board can be used to carry a radio frequency integrated circuit (RF IC), a radio frequency power amplifier (RF PA), a wireless fidelity (wireless fidelity, WIFI) chip, and the like.
  • the application processor board can be used to carry system on chip (SOC) components, double data rate (DDR) memory, main power management unit (PMU), auxiliary PMU, etc.
  • SOC system on chip
  • DDR double data rate
  • PMU main power management unit
  • auxiliary PMU auxiliary PMU
  • the first device 21 and the second device 22 are disposed on the upper surface 101 of the substrate 10 and have a height difference between them, wherein the height of the first device 21 can be understood as the dimension of the first device 21 in the direction perpendicular to the substrate 10 , Specifically, the size refers to the vertical distance from the point farthest from the substrate 10 on the body of the first device 21 to the substrate 10 .
  • the height of the second device 22 can be understood as the size of the second device 22 in the direction perpendicular to the substrate 10 . Specifically, the size refers to: on the body of the second device 22 , the point farthest from the substrate 10 to the height of the substrate 10 vertical distance.
  • the first device 21 and the second device 22 have height differences, so that when the first device 21 and the second device 22 are laid out on the surface of the substrate 10 at the same time, the surface of the first device 21 away from the substrate 10 is perpendicular to the substrate 10 .
  • the distance and the vertical distance between the surface of the second device 22 remote from the substrate 10 and the substrate 10 are not the same. In other words, when the first device 21 and the second device 22 are laid out on the substrate 10, visual effects of different heights can be formed.
  • the terminal 200 or the electronic device 300 to which the circuit board assembly 100 is applied needs to have more diversified functions, more and more electronic components are arranged on the substrate 10 .
  • the space of the circuit board assembly 100 can be laid out in a targeted manner according to the height difference between the first device 21 and the second device 22 , which is beneficial to reduce the space occupied by the circuit board assembly 100 and meet the development trend of thinning and high density of the circuit board assembly 100 .
  • the height of the first device 21 is smaller than the height of the second device 22 . That is, the first device 21 is a relatively short device, and the second device 22 is a relatively tall device.
  • the first device 21 may be, but is not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, a power management chip, or the like.
  • the second device 22 can be, but not limited to, a capacitor, an inductor, a crystal oscillator, an NFC (Near Field Communication, near field communication) control chip, a SOC or a UFS (Universal Flash Storage, universal flash storage) chip, and the like.
  • the number of the first devices 21 may be one or more.
  • the multiple first devices 21 may be of the same type, or may be of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device 21 can be selected according to the actual situation, which is not strictly limited.
  • the number of the second devices 22 may also be one or more. When the number of the second devices 22 is multiple, the plurality of second devices 22 may be of the same type, or may be of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the second device 22 can be selected according to the actual situation, which is not strictly limited.
  • the number of the first devices 21 is multiple
  • the average height of the multiple first devices 21 is denoted as H1
  • the number of the second devices 22 is multiple
  • the average height of the multiple second devices 22 Denoted as H2
  • the height difference between the average height H1 and the average height H2 is greater than or equal to 0.2mm.
  • the average height H1 can be understood as the ratio of the sum of the heights of all the first devices 21 to the total number of the first devices 21
  • the average height H2 can be understood as the sum of the heights of all the second devices 22 and the total number of the second devices 22 . ratio of quantities.
  • the average height of the first device 21 is 1.05 mm
  • the average height of the second device 22 is 1.49 mm
  • the height difference between the average heights of the two is 0.44 mm.
  • the first device 21 and the second device 22 whose height difference satisfies this range enables the circuit board assembly 100 to lay out the space above the two types of devices in a targeted manner, which is beneficial to solve the problem caused by the large height difference of the devices.
  • the problem of wasting stacking space increases the device layout density of multi-layer device stacking.
  • the first conductor 31 is located on the upper surface 101 of the substrate 10 in the area where the first device 21 is located, one end is connected to the substrate 10 , and the other end extends away from the substrate 10 , wherein the first conductor 31 31 may be an electrical connection structure capable of independently realizing the interconnection function, or the first conductor 31 may also be an electrical connection structure assembled with other conductive structures to realize the interconnection function.
  • the second conductor 32 is located in the area where the second device 22 is located on the upper surface 101 of the substrate 10 , one end is connected to the substrate 10 , and the other end extends away from the substrate 10 , wherein the second conductor 32 may be capable of independently realizing the interconnection function Alternatively, the second conductor 32 may also be an electrical connection structure assembled with other conductive structures to realize the interconnection function.
  • setting the first conductor 31 and the second conductor 32 can realize the double-sided interconnection of the first device 21 and the second device 22 respectively, which is beneficial to shorten the wiring distance, realize the short-distance transmission path to the maximum extent, and can effectively use the A smaller area or volume carries better power, which can improve the overall power density, arrangement density and integration degree of the circuit board assembly 100 .
  • the first conductor 31 extends from the substrate 10 in a direction perpendicular to the substrate 10 . That is, the extending direction of the first conductor 31 is perpendicular to the substrate 10 .
  • the second conductors 32 extend from the substrate 10 in a direction perpendicular to the substrate 10 . That is, the extending direction of the second conductor 32 is perpendicular to the substrate 10 .
  • processing and manufacturing are relatively simple, and it is beneficial to rationally utilize the board space of the substrate 10 , thereby further reducing the difficulty of layout of the interconnect structure.
  • the height of the first conductor 31 arranged in the region where the first device 21 is located is higher than the height of the first device 21
  • the height of the second conductor 32 arranged in the region where the second device 22 is located is higher than the height of the second conductor 32 arranged in the region where the second device 22 is located.
  • the height of the device 22, and the first conductor 31 and the second conductor 32 have a height difference, wherein the height of the first conductor 31 can be understood as the length from one end of the first conductor 31 connected to the substrate 10 to the other end, that is, the first The dimension of a conductor 31 in the direction perpendicular to the substrate 10, the height of the second conductor 32 can be understood as the length from one end of the second conductor 32 connected to the substrate 10 to the other end, that is, the second conductor 32 in the direction perpendicular to the substrate 10 size of.
  • the first conductors 31 and the second conductors 32 have height differences, so that when the first conductors 31 and the second conductors 32 are simultaneously laid out on the surface of the substrate 10 , a different height visual effect can be formed.
  • the length from one end to the other end of the first conductor 31 connected to the substrate 10 is different from the length from one end to the other end of the second conductor 32 connected to the substrate 10 .
  • the relative heights of the first conductors 31 and the second conductors 32 will change with the relative heights of the first device 21 and the second device 22 in the region.
  • the height of the first device 21 is smaller than that of the second device
  • the height of the first conductor 31 will be smaller than the height of the second conductor 32, and vice versa.
  • the first conductors 31 and the second conductors 32 arranged in the corresponding regions also have corresponding height differences.
  • the area where the tall device is arranged will be arranged with a higher electrical connection structure, and the area where the short component is arranged will be arranged with the lower electrical connection structure.
  • the heights of the first conductors 31 and the second conductors 32 can be flexibly adjusted according to devices of different heights, so as to fully adapt to the layout differences of tall and short devices, and to avoid the need for the first conductors 31 and the second conductors 32 to be set to the same height. This results in a waste of space above the shorter devices, and is also conducive to reducing processing, production and material management costs, and has good reliability.
  • the height of the first conductor 31 is smaller than the height of the second conductor 32 . That is, the first conductor 31 is an electrical connection structure with a relatively high height, and the second conductor 32 is an electrical connection structure with a relatively low height.
  • the number of the first conductors 31 may be multiple, the multiple first conductors 31 are arranged at intervals in the area where the first device 21 is located, and the heights of the multiple first conductors 31 are the same.
  • the number of the second conductors 32 may be multiple, the multiple second conductors 32 are arranged at intervals in the region where the second device 22 is located, and the multiple second conductors 32 have the same height.
  • the first conductors 31 of the same height are uniformly arranged in the area where the short device is located, and the second conductors 32 of the same height are uniformly arranged in the area where the tall device is located, which can avoid the manufacturing difficulty caused by the different heights of the conductors in the same area. And the complexity increases, making the processing easier and faster.
  • the height difference between the first conductor 31 and the second conductor 32 is greater than or equal to 0.2 mm.
  • the first conductor 31 and the second conductor 32 whose height difference satisfies this range can fully adapt to the layout difference of tall and short devices, which is beneficial to solve the problem of wasting stacking space caused by the large height difference of devices, and improve the stacking of multi-layer devices. device layout density.
  • the package body 40 is connected to the side of the substrate 10 where the first device 21 and the second device 22 are provided, and can package the first device 21 and the second device 22 . It should be understood that the package body 40 also contacts the first conductor 31 and the second conductor 32 while encapsulating the first device 21 and the second device 22 . Therefore, the first device 21 and the second device 22 can be protected from being disturbed by external environmental factors, and good electromagnetic shielding performance can be provided for the first device 21 and the second device 22, and the first conductor 31 and the second conductor can pass through the first conductor 31 and the second conductor.
  • the electrical connection function of 32 provides a good foundation for realizing short-distance double-sided interconnection of the first device 21 and the second device 22 .
  • the package body 40 may be made of an insulating resin material, and the resin material may be phenolic resin, epoxy resin, bismaleimide triazine resin, epoxy acrylate, and polypropylene glycol (PPG). ), epoxy resin containing glass fiber or epoxy acrylate containing glass fiber, etc.
  • the resin material may be phenolic resin, epoxy resin, bismaleimide triazine resin, epoxy acrylate, and polypropylene glycol (PPG).
  • PPG polypropylene glycol
  • the package body 40 includes a first package device region 41 and a second package device region 42 , wherein the first package device region 41 and the second package device region 42 can be understood as constituting the package body 40 .
  • the first packaged device region 41 and the second packaged device region 42 are disposed adjacent to each other, that is, the first packaged device region 41 and the second packaged device region 42 are connected to each other and form the package body 40 together.
  • the outer surface of the package body 40 can be understood as the surface of the package body 40 facing away from the substrate 10 , which includes the outer surface of the first packaged device region 41 and the outer surface of the second packaged device region 42 .
  • the outer surface of the first packaged device region 41 can be understood as the surface of the first packaged device region 41 facing away from the substrate 10 .
  • the outer surface of the second packaged device region 42 can be understood as the surface of the second packaged device region 42 facing away from the substrate 10 .
  • the first encapsulated device region 41 encapsulates the first device 21 to encapsulate the first device 21 on the substrate 10 and surrounds the first conductor 31 . That is, the first conductor 31 is located in the first package device region 41, and one end is connected to the substrate 10, and the other end is connected to the surface of the first package device region 41 facing away from the substrate 10, wherein the other end of the first conductor 31 is connected to the first package device region 41.
  • the surface connection of a packaged device region 41 away from the substrate 10 includes direct connection of the two or indirect connection of the two through an intermediate medium.
  • the second package device region 42 encapsulates the second device 22 to encapsulate the second device 22 on the substrate 10 and surrounds the second conductor 32 . That is, the second conductor 32 is located in the second package device region 42 , and one end is connected to the substrate 10 , and the other end is connected to the surface of the second package device region 42 facing away from the substrate 10 , wherein the other end of the second conductor 32 is connected to the substrate 10 .
  • the surface connection of the two packaged device regions 42 away from the substrate 10 includes direct connection of the two or indirect connection of the two through an intermediate medium.
  • the conductor 32 can make the height of the first package device area 41 encapsulating the first device 21 adapt to the height of the first conductor 31 , and the height of the second package device area 42 encapsulating the second device 22 to adapt to the height of the second conductor 32 .
  • the heights of the first packaged device regions 41 and the second packaged device regions 42 can be heightened with reference to the height differences of the first conductors 31 and the second conductors 32 . Uneven appearance. That is, the package body 40 can be made to have a undulating appearance as a whole.
  • the height of each part of the package body 40 can exactly correspond to the height of the packaged device, so that the package body 40 can adapt to the height difference of tall and short devices and also present a layout arrangement with stepped heights.
  • the conductors and the package body 40 with suitable heights can be arranged in a targeted manner according to the height difference of the devices, which effectively avoids the problem of material waste caused by setting the package body 40 and the conductors at the same height as a whole, which is beneficial to reduce the Material and production costs.
  • a frame plate is arranged on the substrate 10 to realize interconnection, and more non-functional pins for enhancing reliability and realizing electromagnetic shielding performance are arranged on the frame plate. Disposing a highly reliable package body 40 on the substrate 10 enables the package body 40 itself to serve as electromagnetic shielding performance, thereby minimizing the number of non-functional pins used for electrical shielding and reliability enhancement. That is, it is beneficial to minimize the non-functional pins of the circuit board assembly 100 to reduce the waste of board area.
  • the first packaged device region 41 and the second packaged device region 42 have a height difference, wherein the height of the first packaged device region 41 can be understood as one end of the first packaged device region 41 connected to the substrate 10 to the length of the other end. That is, the size of the first packaged device region 41 in the direction perpendicular to the substrate 10 , specifically, the size refers to the vertical distance from the surface of the first packaged device region 41 facing away from the substrate 10 to the upper surface 101 of the substrate 10 .
  • the height of the second package device region 42 can be understood as the length from one end of the second package device region 42 connected to the substrate 10 to the other end. That is, the size of the second packaged device region 42 in the direction perpendicular to the substrate 10 , specifically, the size refers to the vertical distance from the surface of the second packaged device region 42 facing away from the substrate 10 to the upper surface 101 of the substrate 42 .
  • the vertical distance between the surface of the first packaged device region 41 away from the substrate 10 and the substrate 10 and the distance from the second packaged device region 42 The vertical distance between the surface of the substrate 10 and the substrate 10 is not the same. In other words, when the package body 40 is disposed on the substrate 10 , an uneven visual effect can be formed.
  • the relative heights of the first packaged device area 41 and the second packaged device area 42 will vary with the first conductors 31 and the second conductors 32 arranged inside and the first and second devices 21 and 22 packaged inside.
  • the relative height changes.
  • the height of the first device 21 is smaller than the height of the second device 22
  • the height of the first conductor 31 will be smaller than the height of the second conductor 32
  • the height of the first package device area 41 will also be smaller than the height of the second conductor 32.
  • the height difference between the first packaged device region 41 and the second packaged device region 42 is greater than or equal to 0.2 mm.
  • the first package device area 41 and the second package device area 42 whose height difference satisfies this range can fully adapt to the layout difference of tall and short devices, which is beneficial to solve the problem of wasting stacking space caused by the large difference in device height, and improves the Device layout density for a multi-layer device stack.
  • the package body 40 faces away from the substrate 10.
  • the surface may form one or more stepped structures 404 .
  • the stepped structure 404 with the stepped height enables more differentiated and diversified device configurations than a planar structure when devices are reassembled thereon. That is, a relatively taller device can be assembled where the vertical distance between the stepped structure 404 and the substrate 10 is smaller, and a relatively shorter device can be assembled where the vertical distance between the stepped structure 404 and the substrate 10 is larger, so that devices of different heights can be assembled.
  • a relatively flat layout can be presented, which is beneficial to compress the overall thickness of the circuit board assembly 100 in a limited space layout, and makes it possible to lay out more layers of devices in the same size of space. .
  • the height of the first device 21 is smaller than the height of the second device 22, and the height of the first package device area 41 encapsulating the first device 21 is smaller than the height of the second package device area 42 encapsulating the second device 22.
  • the difference in the number of the first packaged device regions 41 and the second packaged device regions 42 can be understood as the difference in the number of regions in which the first device 21 and the second device 22 are laid out.
  • the number of the first package device region 41 is one, and the number of the second package device region 42 is one, so the surface of the package body 40 facing away from the substrate 10 can form a stepped structure as shown in FIG. 4 . 404.
  • the number of the first packaged device regions 41 is one, and the number of the second packaged device regions 42 is two, so the surface of the package body 40 facing away from the substrate 10 can be formed into two parts as shown in FIG. 5 .
  • a step structure 404 is a step structure 404 .
  • the number of the first packaged device regions 41 is two, and the number of the second packaged device regions 42 is one, so the surface of the package body 40 facing away from the substrate 10 can be formed into two regions as shown in FIG. 6 .
  • a step structure 404 is a step structure 404 .
  • the number of the first packaged device regions 41 is multiple, the number of the second packaged device regions 42 is multiple, and the first packaged device regions 41 and the second packaged device regions 42 are alternately arranged, Therefore, the surface of the package body 40 facing away from the substrate 10 can present a plurality of stepped structures 404 as shown in FIG. 7 . That is, there is one second package device region 42 between every two adjacent first package device regions 41, and one first package device region 41 between every two adjacent second package device regions 42.
  • the package body 40 presents one or more stepped layouts as a whole, so that the package body 40 with the height difference can adapt to the different heights of the electronic devices in the package body 40 . It is beneficial to make full use of the space perpendicular to the direction of the substrate 10 , reduce the thickness of the circuit board assembly 100 , and make the equipment applying the circuit board assembly 100 more suitable for the development trend of miniaturization and ultra-thinning.
  • the surface of the package body 40 facing away from the substrate 10 includes a first top surface 401 , a second top surface 402 and a connecting surface 403 , wherein the first top surface 401 , the second top surface 402 and the connecting surface 403 can be understood as the outer surface of the package body 40 .
  • the first top surface 401 is the surface of the first package device region 41 facing away from the substrate 10
  • the second top surface 402 is the surface of the second package device region 42 facing away from the substrate 10
  • the connection surface 403 is connected to the first top surface 401 and the second top surface
  • the first top surface 401 , the connecting surface 403 and the second top surface 402 are sequentially bent and connected to form a stepped structure 404 . That is, the first top surface 401 , the connection surface 403 and the second top surface 402 are connected in sequence to form the surface of the package body 40 facing away from the substrate 10 .
  • connection surface 403 may be a plane perpendicular to the substrate 10 , so that a right-angle transition can be formed between the first top surface 401 and the second top surface 402 .
  • the connecting surface 403 may be a plane disposed at an angle with the substrate 10 , that is, a plane disposed obliquely, so that an oblique transition can be formed between the first top surface 401 and the second top surface 402 .
  • the connecting surface 403 may also be an arc surface, so that a circular arc transition can be formed between the first top surface 401 and the second top surface 402 .
  • the stepped structure 404 can be made to have various shapes, so that different transition forms can be set correspondingly according to different scenarios, which is beneficial to the application requirements of multi-scenarios.
  • first top surface 401 is the surface of the first package device region 41 facing away from the substrate 10
  • second top surface 402 is the surface of the second package device region 42 facing away from the substrate 10
  • the other end of the first conductor 31 It can be connected to the first top surface 401
  • the other end of the second conductor 32 can be connected to the second top surface 402 .
  • the other end of the first conductor 31 and the first top surface 401 are indirectly connected through an intermediate medium
  • the other end of the second conductor 32 and the second top surface 402 are indirectly connected through an intermediate medium for example, but it should be understood that , not limited to this.
  • the circuit board assembly 100 further includes a first via hole 33 , a second via hole 34 , a first plated metal 35 and a second plated metal 36 .
  • the first via hole 33 is disposed corresponding to the first conductor 31 , and the first via hole 33 connects one end of the first conductor 31 away from the substrate 10 and the first top surface 401 (ie, the outer surface of the first package device area 41 ). That is, the first via hole 33 is connected between the first conductor 31 and the first top surface 401 . In other words, the first conductor 31 is connected to the outer surface of the first package device region 41 through the first via hole 33 .
  • the second vias 34 are disposed corresponding to the second conductors 32 , and the second vias 34 connect an end of the second conductors 32 away from the substrate 10 and the second top surface 402 (ie, the outer surface of the second package device area 42 ). That is, the second via 34 is connected between the second conductor 32 and the second top surface 402 . In other words, the second conductor 32 is connected to the outer surface of the second package device region 42 through the second via hole 34 .
  • the first via hole 33 is filled with a first plated metal 35, and the first plated metal 35 connects the end of the first conductor 31 away from the substrate 10 and the first top surface 401 (ie, the outer surface of the first package device area 41);
  • the two vias 34 are filled with a second plated metal 36 , and the second plated metal 36 connects the end of the second conductor 32 away from the substrate 10 and the second top surface 402 (ie, the outer surface of the second package device area 42 ).
  • the electrical connection between the outer surface of the package body 40 and the internal device can be realized, and the interconnection structure penetrating the package body 40 can be realized.
  • a thicker package body 40 can be passed through compared to the prior art.
  • the first conductor 31 may be a gold wire or a needle
  • the second conductor 32 may be a gold wire or a needle.
  • the filling of the first filling metal 35 in the first via hole 33 can be understood as an electrical connection structure formed by filling a conductive metal in the hole-like structure, and the second filling metal 36 filling the second via hole 34 It can also be understood as an electrical connection structure with conductive properties formed by filling conductive metal in the hole-like structure.
  • the heights of the first via hole 33 and the second via hole 34 are the same, so that both processing and manufacturing are easier.
  • the heights of the first via hole 33 and the second via hole 34 are different, so that the height of the metal via hole can be adjusted correspondingly according to the height of each conductor, which is highly flexible.
  • the height of the first via hole 33 can be understood as the length from one end of the first via hole 33 connected to the first conductor 31 to the other end, that is, the dimension of the first via hole 33 in the direction perpendicular to the substrate 10 .
  • the height of the second via hole 34 can be understood as the length from one end of the second via hole 34 connected to the second conductor 32 to the other end, that is, the dimension of the second via hole 34 in the direction perpendicular to the substrate 10 .
  • the first via hole 33 , the first plated metal 35 and the first conductor 31 are connected to form the first conductive structure 37 , and the first conductive structure 37 penetrates through the first package device region 41 .
  • the second via hole 34 , the second plated metal 36 and the second conductor 32 are connected to form a second conductive structure 38 , and the second conductive structure 38 penetrates through the second package device region 42 .
  • the position of the outgoing wires is limited by the outer circumference of the board surface, and the non-outgoing wire area occupies a larger area of the board surface, which is caused by arranging the frame plate on the substrate 10 to realize the interconnection of the upper and lower layers.
  • the first conductive structure 37 and the second conductive structure 38 that can realize double-sided interconnection are arranged inside the package body 40, so that the layout position of the I/O (Input/Output, input/output) outgoing line is not affected, and can be used according to the application. They are arranged at any position in the package body 40 accordingly.
  • the board area and space occupied by the frame board can be saved, the overall outlet area can be increased, and the layout area of the device can be increased.
  • the devices disposed inside the package body 40 can be routed to the nearest location, which is beneficial to simplify the complexity of the wiring and realize the shortest connection of the wiring.
  • the provision of the first conductive structure 37 and the second conductive structure 38 can also break through the layout in which the interconnection structures in the prior art cannot be further densely arranged, so that the space between two adjacent interconnection structures The distance can be shortened to the maximum extent, which is conducive to the realization of high-density arrangement.
  • the center-to-center distance between two adjacent conductive structures is less than or equal to 0.4 mm.
  • the number of the first conductive structures 37 is multiple, the aspect ratio of one or more of the multiple first conductive structures 37 is in the range of 5:1 ⁇ 15:1, and /or, the number of the second conductive structures 38 is multiple, and the aspect ratio of one or more of the multiple second conductive structures 38 is in the range of 5:1 ⁇ 15:1.
  • the aspect ratio of the first conductive structure 37 can be understood as the ratio of the depth of the first conductive structure 37 to the width of the first conductive structure 37 , specifically, the depth of the first conductive structure 37 divided by the width of the first conductive structure 37 the obtained value.
  • the depth of the first conductive structure 37 can be understood as the length from one end of the first conductive structure 37 connected to the substrate 10 to the other end (which can be equivalent to the height of the first conductive structure 37 ), and the width of the first conductive structure 37 can be understood as The first conductive structure 37 is cut parallel to the reference plane of the substrate 10 , and the diameter (width) dimension of the cut cross section is measured.
  • the specific value of the aspect ratio of the first conductive structure 37 can be either an integer value or a decimal value, as long as it is within the range of 5:1 to 15:1 (including the endpoint value) That is, there is no strict restriction on this.
  • the aspect ratio of the second conductive structure 38 can be understood as the ratio of the depth of the second conductive structure 38 to the width of the second conductive structure 38 , which is obtained by dividing the depth of the second conductive structure 38 by the width of the second conductive structure 38 . value of .
  • the depth of the second conductive structure 38 can be understood as the length from one end of the second conductive structure 38 connected to the substrate 10 to the other end (which can be equivalent to the height of the second conductive structure 38 ), and the width of the second conductive structure 38 can be understood as The second conductive structure 38 is cut parallel to the reference plane of the substrate 10, and the diameter (width) dimension of the cut cross-section is measured.
  • the specific value of the aspect ratio of the second conductive structure 38 can be either an integer value or a decimal value, as long as it is within the range of 5:1 to 15:1 (including the endpoint value) That is, there is no strict restriction on this.
  • the conductive structure formed by the conductors and the metal vias can achieve a higher aspect ratio, and the interconnect structure penetrating the package body 40 is relatively higher than the existing one.
  • the thicker package body 40 can be passed through, which is beneficial to meet the application requirements of multiple scenarios.
  • the circuit structure 50 is disposed on the surface of the package body 40 away from the substrate 10 and is electrically connected to the first conductor 31 and the second conductor 32 . That is, the circuit structure 50 can extend from the first package device region 41 to the second package device region 42 and conduct the first conductor 31 and the second conductor 32 . It should be understood that since the circuit structure 50 is disposed on the surface of the package body 40 facing away from the substrate 10 , the shape of the circuit structure 50 changes with the shape of the surface of the package body 40 facing away from the substrate 10 . That is, the surface of the package body 40 facing away from the substrate 10 is stepped, and the circuit structure 50 is correspondingly stepped. Therefore, replacing the flat circuit board in the prior art with the stepped circuit on the surface of the package body 40 is helpful to realize the height mismatch of the multi-layer device layout, which can maximize the space utilization rate and reduce the circuit board assembly 100. overall thickness.
  • the surface of the package body 40 facing away from the substrate 10 can have a circuit layer for electrical connection, which can realize the double-sidedness of the first device 21 and the second device 22 packaged in the package body 40 .
  • the interconnection provides a good foundation, which is beneficial to realize the shortest interconnection path and realize the thin package of the circuit board assembly 100 in a limited space layout, and has strong practicability and good reliability.
  • the circuit structure 50 includes a first pad 51 , a second pad 52 and a connection pad 53 , and the first pad 51 is disposed in the first package device region 41 away from the substrate 10 . and electrically connected to the first conductive structure 37, the second pad 52 is disposed on the surface of the second package device area 42 away from the substrate 10 and is electrically connected to the second conductive structure 38, and the connection pad 53 covers the first package device area 41 and the second package device region 42 and are electrically connected to the first conductive structure 37 or the second conductive structure 38 .
  • first pad 51 is arranged on the first top surface 401
  • second pad 52 is arranged on the second top surface 402
  • connection pad 53 is arranged on the connection surface 403, and can be extended to the first top surface as required. face 401 and/or second top face 402.
  • the first pad 51 , the second pad 52 and the connection pad 53 are all functional pads, which can play the roles of electrical connection and mechanical fixation. That is to say, if a plurality of components (such as circuit boards and electronic components) are connected through the functional pads, electrical signals between the plurality of components can be transmitted through the functional pads.
  • electronic devices can be arranged on the first pad 51 , the second pad 52 and the connection pad 53 , so that not only the package body 40 has electronic devices inside, but also the outside of the package body 40 can continue to stack devices to form a multi-layer stack
  • the structure is conducive to the realization of high-density arrangement of devices.
  • the embodiments of the present application do not limit the number of the first pads 51 , the second pads 52 and the connection pads 53 , which can be selected according to the actual situation, as long as they can be connected to electronic devices. .
  • one or more step structures 404 can be formed on the surface of the package body 40 away from the substrate 10 , and the step structures 404 are formed by the height difference between the first package device region 41 and the second package device region 42 . Therefore, the vertical distance between the first pad 51 arranged on the first package device area 41 and the substrate 10 and the vertical distance between the second pad 52 arranged on the second package device area 42 and the substrate 10 Are not the same.
  • the devices of different heights can be arranged on planes with different distances from the substrate 10, so that the vertical distance between the pads on the different planes can be utilized, and the maximum Compensating the height difference between devices, compared with the pads in the prior art that can only set the devices on the same plane, it can effectively avoid the increase in the number of device stacks under the constraints of the same space size and the number of devices, which is beneficial to the device high-density arrangement.
  • connection pad 53 covering the connection between the first packaged device region 41 and the second packaged device region 42 is also stepped.
  • the connection pads 53 can be distinguished from the planar pads and present a three-dimensional shape, that is, the connection pads 53 can be arranged at the steps to adapt to the step change at the transition of the package body 40 , thereby effectively avoiding Therefore, the composition of the circuit structure 50 can be flexibly adjusted according to the wiring requirements of the circuit board assembly 100 , which is beneficial to adapt to application requirements in multiple scenarios.
  • the waste of the layout device area on the package body 40 is avoided, and the number of pads is increased.
  • the increase in the number of pads can be equivalent to an increase in the number of devices that can be arranged, which is equivalent to improving the layout density of the device, which is beneficial to meet the high-density layout requirements of the device.
  • the circuit structure 50 may include one or more sub-circuit structures 54 arranged in layers.
  • the line structure 50 when the line structure 50 includes one sub-line structure 54 , it is equivalent to a single-layer line that constitutes the line structure 50 . That is, the first pads 51 , the second pads 52 and the connection pads 53 are also of a single-layer structure accordingly.
  • the circuit structure 50 when the circuit structure 50 includes a plurality of sub-circuit structures 54 , the plurality of sub-circuit structures 54 are stacked and disposed, and an insulating layer 57 is provided between two adjacent sub-circuit structures 54 .
  • the insulating layer 57 includes a connection structure 58 , and two adjacent sub-circuit structures 54 are electrically connected to each other through the connection structure 58 penetrating the insulating layer 57 .
  • the first pads 51 , the second pads 52 and the connection pads 53 are correspondingly also multi-layered structures.
  • each pad is a multi-layer structure, and the gap between the two adjacent pads can avoid the problem of bridging by the insulating layer 57, which is beneficial to long-term protection of the formed circuit pattern.
  • the multi-layer sub-circuit structure 54 formed on the package body 40 can also constitute a certain interconnection system, so that the number of the first conductors 31 and the second conductors 32 provided in the package body 40 for interconnection can be correspondingly increased. reduce.
  • the lines and substrates that need to be soldered on the surface of the package body 40 away from the substrate 10 can be exposed to form the first pad 51 , the second pad 52 and the connection pad 53 accordingly, instead of The lines and substrates that need to be soldered can be shielded by forming a solder mask (not shown in the figure).
  • solder resist layer has good insulation properties, it is beneficial to prevent the occurrence of problems such as insulation deterioration and corrosion caused by external environmental factors such as dust and water vapor, and can make it possible to increase the density of the circuit.
  • the device assembled with the substrate 10 can be plastic-encapsulated to form a stepped package body 40 , and the device can be assembled on the surface of the package body 40 again and/or the substrate 10 is used as an upper layer to form a multi-layer board. Assembled, can realize the stacking of multi-layer devices.
  • the stacking possibilities of the multi-layer devices in the embodiments of the present application will be described below through four specific embodiments, wherein the first device 21 and the second device 22 on the substrate 10 constitute the first layer device of the circuit board assembly 100 20.
  • the circuit board assembly 100 further includes a second-layer device 61 , and the second-layer device 61 is disposed on the surface of the package body 40 away from the substrate 10 to realize a two-layer device stacking structure. Therefore, the secondary assembly of the devices on the package body 40 is equivalent to increasing the layout area of the package body 40 away from the surface of the substrate 10 , which can add a layer of devices to the circuit board assembly 100 as a whole, effectively improving the arrangement of devices under the multi-layer structure. density.
  • the second-layer device 61 may be an electronic device with the same height, or may be an electronic device with a height difference.
  • the following will take the second-layer device 61 as an electronic device with a height difference as an example for description, but it should be understand, not limited to this.
  • the second layer device 61 includes a third device 611 and a fourth device 612.
  • the height of the third device 611 can be understood as the dimension of the third device 611 in the direction perpendicular to the substrate 10. Specifically, the dimension refers to: On the body of the third device 611 , the vertical distance from the point farthest from the substrate 10 to the point closest to the substrate 10 .
  • the height of the fourth device 612 can be understood as the size of the fourth device 612 in the direction perpendicular to the substrate 10 . Specifically, the size refers to: on the body of the fourth device 612 , the point farthest from the substrate 10 to the distance from the substrate 10 The vertical distance of the closest point.
  • the third device 611 and the fourth device 612 have a height difference, wherein the height can be understood as a dimension perpendicular to the direction of the substrate 10 . That is, the third device 611 and the fourth device 612 have a difference in height, and in comparison, one is a tall device and the other is a short device.
  • the third device 611 may be, but is not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, a power management chip, or the like.
  • the fourth device 612 may be, but is not limited to, a capacitor, an inductor, a crystal oscillator, an NFC control chip, a SOC or a UFS chip, and the like.
  • the number of the third devices 611 may be one or more.
  • the multiple third devices 611 may be of the same type, or may be of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device 21 can be selected according to the actual situation, which is not strictly limited.
  • the number of the fourth device 612 may also be one or more. When the number of the fourth devices 612 is multiple, the multiple fourth devices 612 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the fourth device 612 can be selected according to the actual situation, which is not strictly limited.
  • the terminal 200 or the electronic device 300 to which the circuit board assembly 100 is applied needs to have more diversified functions, more and more electronic components are arranged.
  • the space of the circuit board assembly 100 can be laid out in a targeted manner according to the height difference between the third device 611 and the fourth device 612 , which is conducive to reducing the size of the circuit board.
  • the space occupied by the assembly 100 satisfies the development trend of thinning and high density of the circuit board assembly 100 .
  • the height of the first device 21 is smaller than that of the second device 22 and the height of the third device 611 is smaller than that of the fourth device 612 , but it should be understood that this is not a limitation.
  • the third device 611 is provided on the second top surface 402
  • the fourth device 612 is provided on the first top surface 401 .
  • a device layout is formed in which the first device 21 and the fourth device 612 are arranged correspondingly, and the second device 22 and the third device 611 are arranged correspondingly. That is to say, it is possible to realize the height distribution of the short devices inside the package body 40 and the high devices outside the package body 40 , and the tall devices inside the package body 40 and the short devices outside the package body 40 .
  • a relatively flat layout arrangement can be presented, which is beneficial to compress the overall thickness of the circuit board assembly 100 in a limited spatial layout.
  • it can make full use of the vertical space to maximize the space utilization rate, so as to break through the stacking space waste problem caused by the large difference in device height under the multi-layer device stacking structure, so that more layers of devices can be laid out in the same space.
  • the possibility of increasing the device layout density of multi-layer device stacking architectures becomes a reality.
  • the third device 611 is provided on the first top surface 401
  • the fourth device 612 is provided on the second top surface 402 . Therefore, by utilizing the height difference between the first packaged device region 41 and the second packaged device region 42, the height difference between the devices can be offset to the greatest extent. Compared with the prior art, the devices can only be arranged on the same plane. Under the constraints of the same space size and the number of devices, the increase in the number of device stacks can be effectively avoided, which is beneficial to the high-density arrangement of the devices.
  • the circuit board assembly 100 may further include a shielding frame 91 , the shielding frame 91 is covered on the surface of the package body 40 away from the substrate 10 and surrounds the second layer device 61 , so that the circuit board assembly 100 is integrated Has good electromagnetic shielding performance.
  • the shielding frame 91 can be made of a metal material or a non-metal material and a conductive coating layer is added on the surface of the non-metal material.
  • the same content as in the first embodiment will not be repeated.
  • the substrate 10 is a double-sided board, which can carry electronic components on both sides to realize a three-layer device stacking structure.
  • the circuit board assembly 100 further includes a third-layer device 62 .
  • the third-layer device 62 is disposed on the surface of the substrate 10 facing away from the package body 40 , that is, the lower surface 102 of the substrate 10 . Therefore, optimizing the substrate 10 from a single panel to a double panel is equivalent to increasing the layout area of one side of the substrate 10 , which can add a layer of devices to the circuit board assembly 100 as a whole, improve space utilization, and effectively improve the multi-layer structure. device density.
  • the number of the third-layer devices 62 may be one or more.
  • the plurality of third-layer devices 62 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the third-layer devices 62 can be selected according to the actual situation, which is not strictly limited.
  • the circuit board assembly 100 further includes an encapsulation structure 70 , and the encapsulation structure 70 encapsulates the third-layer device 62 on the substrate 10 .
  • the package structure 70 may have a stepped appearance with reference to the package body 40 of the first embodiment, or the package structure 70 may have a highly consistent appearance as a whole, which is not strictly limited.
  • both sides of the substrate 10 can be plastic-sealed, and the warpage of the double-sided plastic-sealing of the substrate 10 is smaller than that of the single-side plastic-sealing of the substrate 10 , which is beneficial to improve the flatness of the packaging.
  • the same content as the second embodiment will not be repeated.
  • the difference from the second embodiment is that the entire substrate 10 is used as an upper board and assembled with other boards to realize a four-layer device stacking structure.
  • the circuit board assembly 100 further includes a circuit board 80 , an elevated board 90 and a fourth-layer device 63 .
  • the circuit board 80 is stacked with the base plate 10 at intervals, and the elevated board 90 is connected between the base plate 10 and the circuit board 80 .
  • the substrate 10, the circuit board 80 and the elevated board 90 enclose a cavity A, the fourth layer circuit board 80 is arranged on the surface of the circuit board 80 facing the substrate 10, and the third layer devices 62 and the fourth layer devices 63 are located in the cavity A in body A.
  • the use of the multi-layer board stacking technology is equivalent to increasing the layout area of one side of the circuit board 80 , which can add a layer of devices to the circuit board assembly 100 as a whole. Arrangement density.
  • the third-layer device 62 includes a fifth device 621 and a sixth device 622 .
  • the height of the fifth device 621 can be understood as the size of the fifth device 621 in the direction perpendicular to the substrate 10 .
  • the size refers to: on the body of the fifth device 621 , the point farthest from the substrate 10 to the distance from the substrate 10 The vertical distance of the closest point.
  • the height of the sixth device 622 can be understood as the size of the sixth device 622 in the direction perpendicular to the substrate 10 .
  • the size refers to: on the body of the sixth device 622 , from the point farthest from the substrate 10 to the distance from the substrate 10 The vertical distance of the closest point.
  • the fifth device 621 and the sixth device 622 have a height difference, wherein the height can be understood as a dimension perpendicular to the direction of the substrate 10 . That is, the fifth device 621 and the sixth device 622 are different in height and height, and in comparison, one is a tall device and the other is a short device.
  • the fifth device 621 may be, but is not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, a power management chip, or the like.
  • the sixth device 622 may be, but not limited to, a capacitor, an inductor, a crystal oscillator, an NFC control chip, a SOC or a UFS chip, and the like.
  • the number of the fifth devices 621 may be one or more.
  • the multiple fifth devices 621 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device 21 can be selected according to the actual situation, which is not strictly limited.
  • the number of the sixth device 622 may also be one or more. When the number of the sixth devices 622 is multiple, the multiple sixth devices 622 may be of the same type, or may be of different types, and may have the same height or different heights. That is, the number, type, height, etc. of the sixth device 622 can be selected according to the actual situation, which is not strictly limited.
  • the fourth layer device 63 includes a seventh device 631 and an eighth device 632 .
  • the height of the seventh device 631 can be understood as the size of the seventh device 631 in the direction perpendicular to the substrate 10 . Specifically, the size refers to: on the body of the seventh device 631 , from the point farthest from the substrate 10 to the distance from the substrate 10 The vertical distance of the closest point.
  • the height of the eighth device 632 can be understood as the size of the eighth device 632 in the direction perpendicular to the substrate 10 . Specifically, the size refers to: on the body of the eighth device 632 , the point farthest from the substrate 10 to the distance from the substrate 10 The vertical distance of the closest point.
  • the seventh device 631 and the eighth device 632 have a height difference, wherein the height can be understood as a dimension perpendicular to the direction of the substrate 10 . That is, the seventh device 631 and the eighth device 632 have a difference in height, and in comparison, one is a tall device and the other is a short device.
  • the seventh device 631 may be, but is not limited to, a resistor, a capacitor, a WIFI chip, a baseband chip, a radio frequency chip, a power management chip, or the like.
  • the eighth device 632 may be, but is not limited to, a capacitor, an inductor, a crystal oscillator, an NFC control chip, a SOC or a UFS chip, and the like.
  • the number of the seventh devices 631 may be one or more.
  • the multiple seventh devices 631 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the first device 21 can be selected according to the actual situation, which is not strictly limited.
  • the number of the eighth devices 632 may also be one or more. When the number of the eighth devices 632 is multiple, the multiple eighth devices 632 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the eighth device 632 can be selected according to the actual situation, which is not strictly limited.
  • the third-layer device 62 is classified into the third device 611 and the fourth device 612, and the fourth-layer device 63 is classified into the fifth device 621 and the sixth device 622, which can be targeted according to the height difference of each device.
  • the layout of the space of the circuit board assembly 100 is beneficial to reduce the space occupied by the circuit board assembly 100 and meet the development trend of thinning and high density of the circuit board assembly 100 .
  • the height of the fifth device 621 is smaller than that of the sixth device 622 and the height of the seventh device 631 is smaller than that of the eighth device 632 as an example, but it should be understood that it is not limited thereto.
  • the fifth device 621 is arranged corresponding to the eighth device 632
  • the sixth device 622 is arranged corresponding to the seventh device 631 . That is, it is possible to realize the distribution of the height and the height of the short device and the tall device, and the tall device and the short device in the cavity A.
  • the fifth device 621 is provided corresponding to the seventh device 631
  • the sixth device 622 is provided corresponding to the eighth device 632 .
  • the same content as the third embodiment will not be repeated.
  • the circuit board 80 is a double-sided board, capable of carrying electronic components on both sides, so as to realize a five-layer device stacking structure.
  • the circuit board assembly 100 further includes a fifth-layer device 64 , and the fifth-layer device 64 is disposed on the surface of the circuit board 80 away from the fourth-layer device 63 . Therefore, optimizing the circuit board 80 from a single-sided board to a double-sided board is equivalent to increasing the layout area of one side of the circuit board 80, which can add a layer of devices to the circuit board assembly 100 as a whole. The arrangement density of the device under the layer structure.
  • the height of the device layout is mismatched, and the stacking thickness of the five-layer device is equivalent to the stacking thickness of the four-layer device in the prior art, which is equivalent to the same three-dimensional space condition.
  • One-layer device layout maximizes space utilization, which is conducive to high-density device layout requirements.
  • the number of the fifth layer devices 64 may be one or more.
  • the multiple fifth-layer devices 64 may be of the same type or different types, and may have the same height or different heights. That is, the number, type, height, etc. of the fifth-layer devices 64 can be selected according to the actual situation, which is not strictly limited.
  • Embodiments of the present application further provide a method for fabricating a circuit board assembly 100 .
  • the manufacturing method of the circuit board assembly 100 may at least include S100 , S200 and S300 , which are described in detail as follows.
  • the substrate 10 is provided.
  • S200 Mount the first device 21 and the second device 22 on the substrate 10, and form the first conductor 31 in the region where the first device 21 is located, and form the second conductor 32 in the region where the second device 22 is located, wherein the first device 21 and the second device 22 have a height difference, one end of the first conductor 31 is connected to the substrate 10 and the other end extends away from the substrate 10 , one end of the second conductor 32 is connected to the substrate 10 and the other end is directed away from the substrate 10 Extending, the first conductor 31 and the second conductor 32 have a height difference.
  • S300 forming a package body 40 on the upper surface 101 of the substrate 10 , wherein the package body 40 includes a first package device region 41 and a second package device region 42 , and the first package device region 41 and the second package device region 42 have a height difference .
  • step S100 will be described below with reference to FIG. 3 and FIG. 4 .
  • the substrate 10 is provided.
  • the substrate 10 may be formed by processes such as lamination, drilling, electroplating, patterning, solder resist and surface treatment.
  • the substrate 10 may be a circuit board 80 carrying electronic components on one side.
  • the substrate 10 may be a circuit board 80 that can carry electronic components on both sides.
  • step S200 will be described below with reference to FIG. 15 , FIG. 18 and FIG. 19 .
  • S200 Mount the first device 21 and the second device 22 on the substrate 10, and form the first conductor 31 in the region where the first device 21 is located, and form the second conductor 32 in the region where the second device 22 is located, wherein the first device 21 and the second device 22 have a height difference, one end of the first conductor 31 is connected to the substrate 10 and the other end extends away from the substrate 10 , one end of the second conductor 32 is connected to the substrate 10 and the other end is directed away from the substrate 10 Extending, the first conductor 31 and the second conductor 32 have a height difference.
  • the first conductor 31 may be formed in the region where the first device 21 is located, and the second conductor may be formed in the region where the second device 22 is located 32.
  • the first conductor 31 and the second conductor 32 are vertically punched on the substrate 10 along the direction perpendicular to the substrate 10 , forming a vertical direction from the substrate 10 . on the conductive body.
  • the relative height of the first conductor 31 and the second conductor 32 will vary with the relative height of the first device 21 and the second device 22 in the region.
  • the height of the first conductor 31 will be smaller than the height of the second conductor 32 , and vice versa.
  • the height difference between the first device 21 and the second device 22 may be equal to the height difference between the first conductor 31 and the second conductor 32 .
  • the first device 21 and the second device 22 are mounted on one of the two surfaces of the substrate 10 opposite to each other. While the device constitutes the first layer device), the third layer device 62 can also be mounted on the other surface.
  • the third-layer device 62 may be a device with a uniform height, or the third-layer device 62 may also be a device with a height difference.
  • step S300 will be described below with reference to FIG. 11 , FIG. 18 , FIG. 19 and FIG. 20 .
  • S300 forming a package body 40 on the substrate 10 , wherein the package body 40 includes a first package device region 41 and a second package device region 42 , and the first package device region 41 and the second package device region 42 have a height difference.
  • the first packaged device area 41 covers the first device 21 , and the outer surface of the first packaged device area 41 is connected to the first conductor 31 , the second packaged device area 42 covers the second device 22 , and the second packaged device The outer surface of the region 42 is connected to the second conductor 32 .
  • first conductor 31 and the second conductor 32 can be directly connected to the outer surface of the package body 40 or indirectly connected through an intermediate medium.
  • the following will only take the connection through an indirect medium as an example for description, but it should be understood that, Not limited to this.
  • the package body 40 for encapsulating the first device 21 and the second device 22 is formed on one of the two surfaces of the substrate 10 that are opposite to each other.
  • a package structure 70 for encapsulating the third-layer device 62 is formed on the other surface.
  • the package structure 70 may have a stepped appearance with reference to the package body 40 , or the package structure 70 may have a highly consistent appearance.
  • the manufacturing method of the circuit board assembly 100 further includes at least S310 , S320 , S330 and S340 , which are described in detail as follows:
  • small holes may be formed on the surface of the package body 40 by laser ablation at the corresponding positions of the first conductors 31 and the second conductors 32 to expose the first conductors 31 and the second conductors 32 .
  • S320 Fill the first via hole 33 with the first plated metal 35 and fill the second via hole 34 with the second plated metal 36 , so that the first via hole 33 , the first plated metal 35 and the first conductor 31 are electrically connected A first conductive structure 37 is formed, and the second via hole 34 , the second electroplating metal 36 and the second conductor 32 are electrically connected to form a second conductive structure 38 .
  • the small holes may be filled by electroplating to form I/O interconnects with large aspect ratios extending through the package body 40 from the substrate 10 to the surface of the package body 40 facing away from the substrate 10 . .
  • the circuit structure 50 includes a sub-circuit structure 54 , that is, the circuit structure 50 is a single-layer circuit structure 50 .
  • the formation of the single-layer circuit structure 50 at least includes the following steps:
  • the copper layer 55 can extend from the first packaged device region 41 to the second packaged device region 42 . That is, the copper layer 55 can cover the first top surface 401 , the connection surface 403 and the second top surface 402 uniformly.
  • the dry film 56 can be closely attached to the copper layer 55 without generation of air bubbles.
  • the copper layer 55 can be etched to remove the non-circuit area to leave the circuit, and then the circuit is surface treated to complete the stepped single-layer circuit structure 50 on the surface of the package body 40 .
  • the circuit structure 50 includes a plurality of sub-circuit structures 54 , that is, the circuit structure 50 is a multilayer circuit structure 50 .
  • the formation of the multi-layer circuit structure 50 at least includes the following steps:
  • connection structure 58 on the insulating layer 57 that penetrates the insulating layer 57 and is connected to the sub-circuit structure 54 .
  • S337 Repeat steps S331 to S334 to obtain a two-layer sub-circuit structure 54 .
  • S331 to S336 are repeated multiple times to obtain the multi-layered sub-wiring structure 54 .
  • the mounting of the second-layer device 61 on the circuit structure 50 includes at least the following steps:
  • the embodiment of the present application also provides another method for manufacturing the circuit board assembly 100 , and the same content as the first manufacturing method will not be repeated here.
  • the manufacturing method of the circuit board assembly 100 may include at least S400, S500, S600, S700 and S800 in addition to S100, S200 and S300, which are described in detail below.
  • composition and arrangement of the second-layer device 61 can be referred to the relevant description in the embodiment of the circuit board assembly 100 , which is not repeated here.
  • the specific structure and arrangement of the third-layer device 62 can be referred to the relevant description in the embodiment of the circuit board assembly 100 , which will not be repeated here.
  • S700 Mount the fourth-layer device 63 and the elevated board 90 by using the circuit board 80 as a single panel, so that the elevated board 90 surrounds the fourth-layer device 63 .
  • the circuit board 80 is used as a double-sided board, and the fourth-layer device 63 and the elevated board 90 are mounted on one side, so that the elevated board 90 surrounds the fourth-layer device 63, and the fifth-layer device is mounted on the other side 64.
  • the specific composition and arrangement of the fourth-layer device 63 , the fifth-layer device 64 and the frame board can be referred to the relevant description in the embodiment of the circuit board assembly 100 , which will not be repeated here.
  • circuit board 80 is used as the upper board to be assembled with the elevated board 90 , so that the substrate 10 and the circuit board 80 can be interconnected through the elevated board 90 to obtain a five-layer device stacking structure.

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Abstract

本申请提供一种电路板组件及其制作方法、终端及电子设备。电路板组件包括基板和封装体；所述封装体设于所述基板的上表面，所述封装体包括第一封装器件区和第二封装器件区，所述第一封装器件区和所述第二封装器件区具有高度差。本申请的技术方案能够提高多层器件堆叠结构的布局密度，适应电子设备的小型化发展趋势。

Description

电路板组件及其制作方法、终端及电子设备
本申请要求于2021年04月26日提交中国专利局、申请号为202110453793.2、申请名称为“电路板组件及其制作方法、终端及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种电路板组件及其制作方法、终端及电子设备。
背景技术
随着如手机、笔记本电脑、平板电脑等电子设备日益深入人们的生活，其性能要求也越来越高，而电子设备的整机内空间有限，传统的单层电路板组装技术难以兼顾电子设备高性能、小型化和超薄化发展趋势，故而使得多层器件堆叠结构应运而生。如何能在电子设备的小型化发展的趋势下，提高多层器件堆叠结构的布局密度，为业界持续探索的课题。
发明内容
本申请的实施例提供一种电路板组件及其制作方法、终端及电子设备，能够提高多层器件堆叠结构的布局密度，适应电子设备的小型化发展趋势。
现有的多层板级组装技术中，往往通过框架板(Frame Board，FB)实现立体空间的架高和上下两层的互连。具体而言，框架板包括上层焊盘、下层焊盘以及贯穿框架板且连接上、下层焊盘的通孔，上层焊盘与架高板的焊盘连接，下层焊盘与主板的焊盘连接，再通过通孔形成了主板到架高板的电气互连。此设置下，由于器件有高矮差异，而框架板的高度通常取决于较高器件的高度，这就造成了较矮器件上方的空间浪费。受到产品整机空间的限制以及垂直方向上的空间利用不充分的影响，使得多层器件堆叠结构的布局密度逐渐发展到瓶颈。
而本申请所提供的技术方案能够有效解决上述问题，具体将在下文进一步说明。
本申请第一方面，提供一种电路板组件，所述电路板组件包括：
基板；及
封装体，所述封装体设于所述基板的上表面，所述封装体包括第一封装器件区和第二封装器件区，所述第一封装器件区和所述第二封装器件区具有高度差。
其中，第一封装器件区和第二封装器件区可理解为构成封装体的两个组成部分，能够对电子器件和互连结构等进行封装或包覆。示例性地，第一封装器件区和第二封装器件区邻接设置，也即为，第一封装器件区和第二封装器件区相互连接并共同构成封装体。
第一封装器件区的高度可理解为第一封装器件区连接至基板的一端到另一端的长 度。也即，第一封装器件区垂直于基板方向上的尺寸，具体而言，尺寸是指，第一封装器件区背离基板的表面到基板的上表面的垂直距离。
第二封装器件区的高度可理解为第二封装器件区连接至基板的一端到另一端的长度。也即，第二封装器件区垂直于基板方向上的尺寸，具体而言，尺寸是指，第二封装器件区背离基板的表面到基板的上表面的垂直距离。
而第一封装器件区和第二封装器件区具有高度差，也即为，当第一封装器件区和第二封装器件区都布局于基板的上表面时，第一封装器件区远离基板的表面与基板的上表面的垂直距离和第二封装器件区远离基板的表面与基板的上表面的垂直距离不相同。换言之，封装体设置在基板上时，能够形成高低不平的视觉效果。
需说明的是，本申请的技术方案对于第一封装器件区和第二封装器件区的数量不做限制，其可根据需要被配置成为一个或多个。
可以理解的是，通过在基板上设置第一封装器件区和第二封装器件区，且第一封装器件区和第二封装器件区具有高度差异，故而第一封装器件区和第二封装器件区的高度能够呈现高低不平的外观形态。也即为，能够使封装体整体呈现高低起伏的外观形态。
由此，封装体的各个部分的高度能够呈现具有阶梯化高度的布局设置。一方面，能够根据各部分所封装的器件的高矮差异而有针对性的布局适宜高度的封装体，有效避免了使封装体整体设置为统一高度所造成的材料浪费的问题，有利于减小物料和生产成本。另一方面，利用封装体各部分的高度差异实现内部高矮器件的错配封装，能够最大限度的减少因以高器件的高度作为参照而使封装体整体设置为统一高度，而造成的矮器件上方的空间虚耗。有利于合理利用垂直于基板方向上的空间，解决因器件高矮差异大所造成的堆叠空间浪费问题，并可在应用至多层堆叠结构时使得空间利用率最大化，提升多层器件堆叠的器件布局密度。
并且，由于第一封装器件区和第二封装器件区具有高度差值，故而封装体背离基板的表面可形成阶梯布局。由此，具有阶梯高度的封装体使得在其上再次组装器件时，相对于平面结构更能够提供差异化和多元化的器件配置。也即为，能够在封装体距离基板垂直距离较小处组装相对更高的器件，在封装体距离基板垂直距离较大处组装相对更矮的器件，使得不同高度的器件被组装至其上时，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件整体的厚度，并使在同一大小的空间下布局更多层器件的可能性成为现实。
另外，相较于现有技术中在基板上设置框架板实现互连，并在框架板上设置较多的用于增强可靠性和实现电磁屏蔽性能的非功能引脚。在基板上设置可靠性较强的封装体，能够使封装体自身用作电磁屏蔽性能，从而最大限度的减小用于电屏蔽和可靠性增强的非功能性引脚。也即为，有利于最大限度的减小电路板组件的非功能引脚，以减小板面面积的浪费。
一种可能的实施方式中，所述第一封装器件区包覆有第一器件，所述第一器件设于所述基板的所述上表面，所述第二封装器件区包覆有第二器件，所述第二器件设于所述基板的所述上表面，所述第一器件和所述第二器件具有高度差。
可以理解的是，第一器件的高度可理解为第一器件垂直于基板方向上的尺寸，具体 而言，所述尺寸是指：在第一器件本体上，距离所述基板最远的一点到该基板的垂直距离。第二器件的高度可理解为第二器件垂直于基板方向上的尺寸，具体而言，所述尺寸是指：在第二器件本体上，距离基板最远的一点到该基板的垂直距离。
而第一器件和第二器件设于基板的上表面，且彼此之间具有高度差。也即为，第一器件和第二器件具有高矮差异，从而当第一器件和第二器件都布局于基板表面时，第一器件远离基板的表面与基板的垂直距离和第二器件远离基板的表面与基板的垂直距离不相同。换言之，第一器件和第二器件布局在基板上时，能够形成高低不一的视觉效果。
示例性地，第一器件的高度小于第二器件的高度。也即为，第一器件相对而言为矮器件，第二器件相对而言为高器件。第一器件可以为但不限于为电阻、电容、WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第二器件可以为但不限于为电容、电感、晶振、NFC(Near Field Communication，近场通信)控制芯片、SOC或UFS(Universal Flash Storage，通用闪存存储)芯片等。
需说明的是，第一器件的数量可以为一个或多个。当第一器件的数量为多个时，多个第一器件可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第二器件的数量也可以为一个或多个。当第二器件的数量为多个时，多个第二器件可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第二器件的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
一种可能的实施方式中，所述电路板组件还包括第一导体和第二导体，所述第一导体位于所述第一封装器件区，所述第一导体的一端与所述基板连接，另一端与所述第一封装器件区的外表面连接，所述第二导体位于所述第二封装器件区，所述第二导体的一端与所述基板连接，另一端与所述第二封装器件区的外表面连接，所述第一导体与所述第二导体具有高度差。
可以理解的是，第一导体位于基板的上表面上第一器件所在区域，且一端与基板连接，另一端向远离基板的方向延伸，其中，第一导体可以为能够独立实现互连功能的电连接结构，或者，第一导体也可以为与其他导电结构组装而实现互连功能的电连接结构。第一导体的高度可理解为第一导体连接至基板的一端到另一端的长度，也即，第一导体垂直于基板方向上的尺寸。
第二导体位于基板的上表面上第二器件所在区域，且一端与基板连接，另一端向远离基板的方向延伸，其中，第二导体可以为能够独立实现互连功能的电连接结构，或者，第二导体也可以为与其他导电结构组装而实现互连功能的电连接结构。第二导体的高度可理解为第二导体连接至基板的一端到另一端的长度，也即，第二导体垂直于基板方向上的尺寸。
而第一导体和第二导体具有高度差，其中，高度可理解为垂直于基板方向的尺寸。也即为，第一导体和第二导体具有高矮差异，从而当第一导体和第二导体同时布局于基板表面时，能够形成高低不一的视觉效果。换言之，第一导体连接至基板的一端到另一 端的长度与第二导体连接至基板的一端到另一端的长度不相同。
可以理解的是，由于第一器件和第二器件具有高度差异，为充分利用器件之间的高度差异，故而布置在对应区域的第一导体和第二导体也相应的具有高度差异。此设置下，在基板的板面区域内，设置高器件的区域会设置高度较高的电连接结构，设置矮器件的区域会设置高度较低的电连接结构。由此，第一导体和第二导体的高度能够根据不同高度的器件灵活调整，以充分适配高矮器件的布局差异，避免因将第一导体和第二导体设置为统一高度而造成较矮器件上方的空间浪费，还有利于减少加工、生产和物料管理成本，可靠性佳。
示例性地，第一导体的高度小于第二导体的高度。也即为，第一导体相对而言为高度较高的电连接结构，第二导体相对而言为高度较低的电连接结构。而第一导体的数量可为多个，多个第一导体间隔排布于第一器件所在区域，且多个第一导体的高度相同。第二导体的数量可为多个，多个第二导体间隔排布于第二器件所在区域，且多个第二导体的高度相同。由此，在矮器件所在区域统一设置相同高度的第一导体，并在高器件所在区域也统一设置相同高度的第二导体，能够避免同区域内导体高度不一而造成的制造困难度和复杂度增加，使得加工较为简便和快捷。
具体而言，第一封装器件区包覆第一器件而将第一器件封装在基板上并包围第一导体。也即为，第一导体位于第一封装器件区，且一端与基板连接，另一端与第一封装器件区的外表面连接，其中，第一导体的另一端与第一封装器件区的外表面连接包括两者直接连接或两者通过中间媒介而间接连接。
第二封装器件区包覆第二器件而将第二器件封装在基板上并包围第二导体。也即为，第二导体位于第二封装器件区，且一端与基板连接，另一端与第二封装器件区的外表面连接，其中，第二导体的另一端与第二封装器件区的外表面连接包括两者直接连接或两者通过中间媒介而间接连接。
需说明的是，封装体的外表面可理解为封装体背离基板的表面，其包括第一封装器件区的外表面和第二封装器件区的外表面。而第一封装器件区的外表面可理解为第一封装器件区背离基板的表面。第二封装器件区的外表面可理解为第二封装器件区背离基板的表面。
而第一导体和第二导体的高度会随着所在区域的第一器件和第二器件的高度而发生变化，当第一器件的高度小于第二器件的高度时，第一导体的高度会小于第二导体的高度，反之亦然。
可以理解的是，通过在基板上设置高度不同的第一器件和第二器件，并在第一器件所在的区域布局第一导体，在第二器件所在的区域布局第二导体，能够使封装第一器件的第一封装器件区的高度适配第一导体的高度，封装第二器件的第二封装器件区的高度适配第二导体的高度。又因第一导体与第二导体具有高度差异，故而第一封装器件区和第二封装器件区的高度能够以第一导体和第二导体的高度差异为参照而呈现高低不平的外观形态。也即为，能够使封装体整体呈现高低起伏的外观形态。
由此，封装体的各个部分的高度能够恰好对应所封装的器件高度，使得封装体能够适配高矮器件的高度差异也呈现具有阶梯化高度的布局设置。一方面，能够根据器件的 高矮差异而有针对性的布局适宜高度的导体和封装体，有效避免了使封装体和导体整体设置为统一高度所造成的材料浪费的问题，有利于减小物料和生产成本。另一方面，利用高矮器件之间的高度差异而使封装体各部分的高度实现高矮器件错配，能够最大限度的减少因以高器件的高度作为参照而使封装体整体设置为统一高度，而造成的矮器件上方的空间虚耗。有利于合理利用垂直于基板方向上的空间，解决因器件高矮差异大所造成的堆叠空间浪费问题，并可在应用至多层堆叠结构时使得空间利用率最大化，提升多层器件堆叠的器件布局密度。
一种可能的实施方式中，所述电路板组件还包括第一过孔和第二过孔，所述第一导体与所述所述第一封装器件区的外表面通过所述第一过孔连接，所述第二导体与所述所述第二封装器件区的外表面通过所述第二过孔连接。也即为，所述第一过孔连接在所述第一导体和所述第一封装器件区的外表面之间，所述第二过孔连接在所述第二导体和所述第二封装器件区的外表面之间。
所述第一过孔内填充有第一电镀金属，所述第一电镀金属连接所述第一导体和所述第一封装器件区的外表面；所述第二过孔内填充有第二电镀金属，所述第二电镀金属连接所述第二导体和所述第二封装器件区的外表面。
通过设置填充有第一电镀金属的第一过孔和填充有第二电镀金属的第二过孔，能够实现封装体表面与内部器件的电气连接，并使得贯穿封装体的互连结构相对于现有技术而言能穿过更厚的封装体。示例性地，第一导体可以为金线或植针，第二导体可以为金线或植针。
应当理解，第一填充金属填充在第一过孔内可理解为在孔类结构中填充导电金属而形成的具有导电性能的电连接结构，第二填充金属填充在第二过孔内也可理解为在孔类结构中填充导电金属而形成的具有导电性能的电连接结构。示例性地，第一过孔和第二过孔的高度相同，从而使加工和制造都较为简便。或者，第一过孔和第二过孔的高度不相同，从而能够根据各导体的高度而相应的对金属过孔的高度进行调整，灵活性强。其中，第一过孔的高度可理解为第一过孔连接至第一导体的一端到另一端的长度，也即，第一过孔垂直于基板方向上的尺寸。第二过孔的高度可理解为第二过孔连接至第二导体的一端到另一端的长度，也即，第二过孔垂直于基板方向上的尺寸。
此设置下，第一过孔和第二过孔的布局位置不受影响，可随应用需求而相应被布置在封装体内的任意位置。一方面，能够节省框架板所占用的板面面积和空间大小，提高整体的出线面积，从而提升器件的布局面积。另一方面，能够使设置在封装体内部的器件就近出线，有利于简化走线复杂度和实现线路的最短连接。
一种可能的实施方式中，所述第一过孔、所述第一电镀金属与所述第一导体连接构成第一导电结构，所述第二过孔、所述第二电镀金属与所述第二导体连接构成第二导电结构，所述第一导电结构的深宽比在5:1～15:1的范围内，和/或，所述第二导电结构的深宽比在5:1～15:1的范围内。
其中，第一导电结构的深宽比可以理解为第一导电结构的深度与第一导电结构的宽度的比值，具体为第一导电结构的深度除以第一导电结构的宽度所得到的数值。而第一导电结构的深度可理解为第一导电结构连接至基板的一端到另一端的长度(可等同于第 一导电结构的高度)，第一导电结构的宽度可理解为以平行于基板的参考面截取第一导电结构，截取出的横截面的直径(宽度)尺寸。
需说明的是，第一导电结构的深宽比的具体数值既可以为整数数值，也可以为具有小数的数值，只需满足落在5:1～15:1的范围内(包括端点值)即可，对此不做严格限制。
第二导电结构的深宽比可以理解为第二导电结构的深度与第二导电结构的宽度的比值，具体为第二导电结构的深度除以第二导电结构的宽度所得到的数值。而第二导电结构的深度可理解为第二导电结构连接至基板的一端到另一端的长度(可等同于第二导电结构的高度)，第二导电结构的宽度可理解为以平行于基板的参考面截取第二导电结构，截取出的横截面的直径(宽度)尺寸。
需说明的是，第二导电结构的深宽比的具体数值既可以为整数数值，也可以为具有小数的数值，只需满足落在5:1～15:1的范围内(包括端点值)即可，对此不做严格限制。
此设置下，相对于现有技术中在基板上设置框架板以实现上下层的互连所导致的出线位置受限于板面的外周，非出线区占用的板面面积较大的问题。在封装体内部设置能够实现双面互连的第一导电结构和第二导电结构，能够使I/O(Input/Output，输入/输出)出线的布局位置不受影响，可随应用需求而相应被布置在封装体内的任意位置。一方面，能够节省框架板所占用的板面面积和空间大小，提高整体的出线面积，从而提升器件的布局面积。另一方面，能够使设置在封装体内部的器件就近出线，有利于简化走线复杂度和实现线路的最短连接。
可以理解的是，现有技术中，框架板中相邻两个通孔之间的孔间距过小后，在长期的电压差条件下，高电压的通孔易长出导电丝，导电丝易到达低电压的通孔而使两个通孔短路。也即为，当前通孔的间距已达到极限，无法进一步密集排布。示例性地，相邻两个通孔之间的中心距为0.5mm。
由此，本申请的实施例中，设置第一导电结构和第二导电结构还能突破现有技术的互连结构无法进一步密集排布的布局，使得相邻两个互连结构之间的距离能够最大限度的缩短，有利于实现高密化排布。示例性地，相邻两个导电结构的中心距小于或等于0.4mm。
另外，相对于现有技术中内较低的深宽比，由导体和金属过孔共同构成的导电结构能够实现更高的深宽比，并使得贯穿封装体的互连结构相对于现有技术而言能穿过更厚的封装体，有利于适应多场景的应用需求。
一种可能的实施方式中，所述第一导体自所述基板向垂直于所述基板的方向延伸，所述第二导体自所述基板向垂直于所述基板的方向延伸。
此设置下，加工和制造都较为简便，且有利于合理利用基板的板面空间，进一步降低互连结构的布局难度。
一种可能的实施方式中，所述第一导体和所述第二导体之间的高度差值大于或等于0.2mm。
其中，第一导体的高度可理解为第一导体连接至基板的一端到另一端的长度，也即，第一导体垂直于基板方向的尺寸。第二导体的高度可理解为第二导体连接至基板的一端到另一端的长度，也即，第二导体垂直于基板方向的尺寸。
而第一导体和第二导体的高度差值可理解为以两者的高度做减法，相减得到的数值。也即为，第一导体连接至基板的一端到另一端的距离与第二导体连接至基板的一端到另一端的距离的差值。
由此，高度差异满足此范围的第一导体和第二导体，能够充分适配高矮器件的布局差异，有利于解决因器件高矮差异大所造成的堆叠空间浪费问题，提升多层器件堆叠的器件布局密度。
一种可能的实施方式中，所述电路板组件还包括设于所述封装体的外表面的线路结构，所述线路结构包括第一焊盘和第二焊盘，所述第一焊盘设于所述第一封装器件区的外表面且与所述第一导体电连接，所述第二焊盘设于所述第二封装器件区的外表面且与所述第二导体电连接，所述第一焊盘与所述基板之间的垂直距离与所述第二焊盘与所述基板之间的垂直距离不相同。
需说明的是，封装体的外表面可理解为封装体背离基板的表面，其包括第一封装器件区的外表面和第二封装器件区的外表面。而第一封装器件区的外表面可理解为第一封装器件区背离基板的表面。第二封装器件区的外表面可理解为第二封装器件区背离基板的表面。
可以理解的是，第一焊盘和第二焊盘均为功能性焊盘，其可以起到电连接、机械固定等作用。也就是说，如果多个元器件(例如可以是电路板、电子元件)通过功能性焊盘相连，则可以通过功能性焊盘传输该多个元器件之间的电信号。
换言之，第一焊盘和第二焊盘上均能够设置电子器件，从而不仅封装体内部具有电子器件，封装体的外部也可继续堆叠器件而形成多层堆叠架构，有利于实现器件的高密化排布。
此设置下，在封装体上再次堆叠器件时，能够将不同高度的器件布局在距基板距离不同的平面上，从而能够利用不同平面上的焊盘之间的垂直距离，而最大限度的抵消器件之间的高度差异，相对于现有技术中仅能将器件设置于同一平面的焊盘，能够在相同空间大小和器件数量的限制下，有效避免器件叠层数量的增加，有利于器件的高密化排布。
一种可能的实施方式中，所述电路板组件还包括第三器件和第四器件；
所述第一器件的高度小于所述第二器件的高度，所述第三器件的高度小于所述第四器件的高度；
所述第三器件与所述第一焊盘和第二焊盘中的一个进行连接，所述第四器件与所述第一焊盘和第二焊盘中的另一个进行连接。
可以理解的是，第一器件和第二器件组成电路板组件的第一层器件，而电路板组件还包括第二层器件，第二层器件设于封装体背离基板的表面，以实现两层器件堆叠架构。由此，在封装体上二次组装器件，等同于增加了封装体背离基板表面的布局面积，能够使得电路板组件整体增加一层器件，有效提升多层架构下器件的排布密度。
需说明的是，第二层器件可以为同样高度的电子器件，也可以为具有高矮差异的电子器件，如下将以第二层器件为具有高矮差异的电子器件为例进行说明，但应当理解，并不以此为限。
具体而言，第二层器件包括第三器件和第四器件，第三器件的高度可理解为第三器件垂直于基板方向上的尺寸，具体而言，尺寸是指：在第三器件本体上，距离基板最远的一点到距离该基板最近的一点的垂直距离。第四器件的高度可理解为第四器件垂直于基板方向上的尺寸，具体而言，尺寸是指：在第四器件本体上，距离基板最远的一点到距离该基板最近的一点的垂直距离。
而第三器件和第四器件具有高度差，也即为，第三器件和第四器件具有高矮差异，两者相较而言，一者为高器件，另一者为矮器件。示例性地，第三器件可以为但不限于为电阻、电容、WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第四器件可以为但不限于为电容、电感、晶振、NFC控制芯片、SOC或UFS芯片等。
需说明的是，第三器件的数量可以为一个或多个。当第三器件的数量为多个时，多个第三器件可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第四器件的数量也可以为一个或多个。当第四器件的数量为多个时，多个第四器件可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第四器件的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
可以理解的是，由于应用电路板组件的终端或电子设备需要具有更多样化的功能，故而布置的电子元件也就越来越多。而将电子元件分类为第三器件和第四器件，能够根据第三器件和第四器件的高矮差异而有针对性的对电路板组件的空间进行布局，有利于缩小电路板组件100所占用的空间，满足电路板组件的轻薄化和高密化的发展趋势。
如下将以第一器件的高度小于第二器件的高度，第三器件的高度小于第四器件的高度为例进行说明，但应当理解，并不以此为限。
在一具体的应用场景中，第三器件设于第一焊盘，第四器件设于第二焊盘。从而形成第一器件与第四器件对应设置，第二器件与第三器件对应设置的器件布局。也即为，能够实现封装体内部矮器件搭配封装体外部高器件，封装体内部高器件搭配封装体外部矮器件的高矮错落分配。
此设置下，在封装体的表面二次组装器件，一方面，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件整体的厚度。另一方面，能够充分利用垂直空间，实现空间利用率的最大化，以突破多层器件堆叠架构下，器件高矮差异大造成的堆叠空间浪费问题，使在同一大小的空间下布局更多层器件的可能性成为现实，提升多层器件堆叠架构的器件布局密度。
在另一具体的应用场景中，第三器件设于第一焊盘，第四器件设于第二焊盘。由此，利用第一封装器件区和第二封装器件区之间的高度差异，能够最大限度的抵消器件之间的高度差异，相对于现有技术中仅能将器件设置于同一平面，能够在相同空间大小和器件数量的限制下，有效避免器件叠层数量的增加，有利于器件的高密化排布。
一种可能的实施方式中，所述线路结构还包括连接焊盘，所述连接焊盘覆盖所述第一封装器件区和所述第二封装器件区的连接处，所述连接焊盘与所述第一导电结构或所 述第二导电结构电连接。
可以理解的是，连接焊盘为功能性焊盘，其可以起到电连接、机械固定等作用。也就是说，如果多个元器件(例如可以是电路板、电子元件)通过功能性焊盘相连，则可以通过功能性焊盘传输该多个元器件之间的电信号。
换言之，连接焊盘上能够设置电子器件，从而不仅封装体内部具有电子器件，封装体的外部也可继续堆叠器件而形成多层堆叠架构，有利于实现器件的高密化排布。
而由于第一封装器件区和第二封装器件区的连接处呈台阶状，故而覆盖第一封装器件区和第二封装器件区连接处的连接焊盘也呈台阶状。此设置下，连接焊盘可区别于平面状的焊盘而呈现立体形态，也即为，连接焊盘能够适应封装体的过渡处的台阶变化而被布置在台阶处，从而有效避免了封装体上可布局器件面积的浪费，并增加了焊盘的数量。而焊盘数量的增加可等同于可供设置的器件的数量的增加，相当于提高了器件的布局密度，有利于适应器件的高密化排布需求。
一种可能的实施方式中，所述线路结构还包括一个子线路结构。或者，所述线路结构还包括多个子线路结构和设置在相邻两个子线路结构之间的绝缘层，所述绝缘层包括连接结构，相邻两个所述子线路结构通过所述绝缘层的所述连接结构进行电连接。
也即为，当所述线路结构具有多个层叠设置的子线路结构时，相邻两个所述子线路结构之间具有一层绝缘层，且相邻两个所述子线路结构通过贯穿所述绝缘层的连接结构彼此电连接。
由此，能够根据电路板组件的布线需求而对线路结构的组成灵活调整，有利于适应多场景下的应用需求。
一种可能的实施方式中，所述封装体的外表面形成一个或多个台阶结构。其中，封装体的外表面可理解为封装体背离基板的表面。
可以理解的是，由于第一封装器件区和第二封装器件区具有高度差值，故而根据第一封装器件区和第二封装器件区数量的配置，封装体背离基板的表面可形成一个或多个台阶结构。由此，具有阶梯高度的台阶结构使得在其上再次组装器件时，相对于平面结构更能够提供差异化和多元化的器件配置。也即为，能够在台阶结构距离基板垂直距离较小处组装相对更高的器件，在台阶结构距离基板垂直距离较大处组装相对更矮的器件，使得不同高度的器件被组装至其上时，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件整体的厚度，并使在同一大小的空间下布局更多层器件的可能性成为现实。
第二方面，本申请还提供一种电路板组件的制作方法，所述电路板组件的制作方法包括：
提供基板；及
在所述基板的上表面形成封装体，其中，所述封装体包括第一封装器件区和第二封装器件区，所述第一封装器件区和所述第二封装器件区具有高度差。
一种可能的实施方式中，在所述提供基板之后，以及在所述所述基板上形成封装体之前，所述方法还包括：
在所述基板的上表面贴装第一器件和第二器件，其中，所述第一器件与所述第二器 件具有高度差。
一种可能的实施方式中，所述方法还包括：
在所述第一器件所在区域形成第一导体，在所述第二器件所在区域形成第二导体，其中，所述第一导体的一端与所述基板连接，另一端向远离所述基板的方向延伸，所述第二导体的一端与所述基板连接，另一端向远离所述基板的方向延伸，所述第一导体与所述第二导体具有高度差。
示例性地，可在在所述基板的上表面贴装第一器件和第二器件的过程中，在所述第一器件所在区域形成第一导体，在所述第二器件所在区域形成第二导体。
一种可能的实施方式中，所述第一封装器件区包覆第一器件，且第一封装器件区的外表面与第一导体连接，第二封装器件区包覆第二器件，且第二封装器件区的外表面与第二导体连接。
一种可能的实施方式中，在所述在所述基板的上表面形成封装体之后，所述方法还包括：
在所述第一封装器件区的外表面和在所述第二封装器件区的外表面分别形成露出所述第一导体的第一过孔和露出所述第二导体的第二过孔；及
在所述第一过孔内填充第一电镀金属和在所述第二过孔内填充第二电镀金属，以使所述第一过孔、所述第一电镀金属和所述第一导体连接形成第一导电结构，所述第二过孔、所述第二电镀金属与所述第二导体连接形成第二导电结构。
一种可能的实施方式中，在所述在所述第一过孔内填充第一电镀金属和在所述第二过孔内填充第二电镀金属，之后，所述方法还包括：
在所述封装体的外表面形成与所述第一导电结构和所述第二导电结构电连接的线路结构。
一种可能的实施方式中，在所述在所述封装体的外表面形成与所述第一导电结构和所述第二导电结构电连接的线路结构之后，所述方法还包括：
在所述线路结构上贴装第二层器件，其中，所述第一器件和所述第二器件组成电路板组件的第一层器件。
一种可能的实施方式中，第一导体的延伸方向与基板垂直，第二导体的延伸方向与基板垂直。
一种可能的实施方式中，所述第一导体和所述第二导体之间的高度差值大于或等于0.2mm。
一种可能的实施方式中，所述第一导电结构的数量为多个，多个所述第一导电结构中的一者或多者的深宽比在5:1～15:1的范围内，和/或，所述第二导电结构的数量为多个，多个所述第二导电结构中的一者或多者的深宽比在5:1～15:1的范围内。
第三方面，本申请还提供一种终端，所述终端包括显示屏、天线模块和如权利要求上所述的电路板组件，所述显示屏和所述天线模块均电连接至所述电路板组件。
第四方面，本申请还提供一种电子设备，所述电子设备包括壳体和如上所述的电路板组件，所述电路板组件设于所述壳体内。
附图说明
图1是本申请实施例提供的终端的结构示意图；
图2是本申请实施例提供的电子设备的结构示意图；
图3是本申请实施例提供的电路板组件的一种结构示意图；
图4是本申请实施例提供的电路板组件的另一种结构示意图；
图5是本申请实施例提供的电路板组件的封装体的一种结构示意图；
图6是本申请实施例提供的电路板组件的封装体的另一种结构示意图；
图7是本申请实施例提供的电路板组件的封装体的又一种结构示意图；
图8是本申请实施例提供的电路板组件的封装体的连接面的一种结构示意图；
图9是本申请实施例提供的电路板组件的封装体的连接面的另一种结构示意图；
图10是本申请实施例提供的电路板组件的封装体的连接面的又一种结构示意图；
图11是本申请实施例提供的电路板组件的线路结构的一种结构示意图；
图12是本申请实施例提供的电路板组件的线路结构的另一种结构示意图；
图13是本申请第一实施例提供的电路板组件的一种结构示意图；
图14是本申请第一实施例提供的电路板组件的另一种结构示意图；
图15是本申请第二实施例提供的电路板组件的一种结构示意图；
图16是本申请第三实施例提供的电路板组件的一种结构示意图；
图17是本申请第四实施例提供的电路板组件的一种结构示意图；
图18是本申请实施例提供的电路板组件的制作方法的一种流程示意图；
图19是图18所示的电路板组件的制作方法的一种状态示意图；
图20是本申请实施例提供的电路板组件的封装体的一种步骤示意图；
图21是本申请实施例提供的电路板组件的制作方法的另一种流程示意图；
图22是本申请实施例提供的电路板组件的线路结构的一种流程示意图；
图23是图22所示的电路板组件的线路结构的一种步骤示意简图；
图24是本申请实施例提供的电路板组件的线路结构的另一种流程示意图；
图25是图24所示的电路板组件的线路结构的另一种步骤示意简图；
图26是本申请实施例提供的电路板组件的制作方法的再一种流程示意图；
图27是本申请实施例提供的电路板组件的制作方法的又一种流程示意图。
具体实施方式
为了方便理解，首先对本申请的实施例所涉及的术语进行解释。
和/或：仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
多个：是指两个或多于两个。
连接：应做广义理解，例如，A与B连接，可以是A与B直接相连，也可以是A与B通过中间媒介间接相连。
下面将结合附图，对本申请的具体实施方式进行清楚地描述。
随着如手机、笔记本电脑、平板电脑等电子产品日益深入人们的生活，其性能要求 也越来越高，而电子产品的整机内空间有限，常规的单层电路板组装技术难以兼顾电子产品高性能、小型化和超薄化发展趋势，故而使得多层器件堆叠结构应运而生。然而在现有的多层板级组装技术中，受到产品整机空间的限制以及垂直方向上的空间利用不充分的影响，使得多层器件堆叠结构的布局密度逐渐发展到瓶颈。
基于此，请结合参阅图1和图2，本申请的实施例提供一种终端200和电子设备300，能够提高多层器件堆叠结构的布局密度，适应电子产品的小型化发展趋势。其中，终端200可以为但不仅限于为手机、平板电脑和笔记本电脑。电子设备300可以为但不仅限于为电源模块、智能手环、智能手表、服务器、路由器、交换机、超级计算机、AI设备和数据中心。
如下将对终端200和电子设备300的结构形态分别进行描述，为方便理解，以手机这种具有广泛使用人群和丰富应用场景的终端200为例来进行说明，但并不以此为限。
终端200：
请参阅图1，终端200可以包括中框210、显示屏(图未示)、前盖230、后盖240、天线模块250和电路板组件100。前盖230和后盖240分别连接于中框210的相背的两侧，以与中框210配合围设形成终端200的容置空间，容置空间可以安装终端200的各类器件，如电路板组件100。显示屏固定至前盖230，并电连接至电路板组件100，能够显示图像、色彩、文字等视觉信息。天线模块250可固定至中框210或固定至终端200的容置空间，并电连接至电路板组件100。电路板组件100可向天线模块250收发电磁信号，天线模块250可根据接收的电磁信号辐射电磁波或根据接收的电磁波向电路板组件100发送电磁信号，从而实现电磁信号的收发。换言之，终端200能够在天线模块250的作用下发射和接收电磁信号，从而实现电磁信号的高增益和广覆盖。
需说明的是，图1的目的仅在于示意性的描述中框210、显示屏、前盖230、后盖240、天线模块250和电路板组件100的连接关系，并非是对各个设备的连接位置、具体构造及数量做具体限定。而本申请实施例示意的结构并不构成对终端200的具体限定。在本申请另一些实施例中，终端200可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
可以理解的是，当终端200为手机时，前盖230为用户握持手机时，朝向用户面部的盖板，其可以通过设置显示屏，以用于呈现图像、色彩、文字等视觉信息。后盖240为用户握持手机时，背向用户面部的盖板，其可以通过设置摄像模组以作为后置摄像头来捕获手机后方的静态图像或动态视频。电路板组件100为能够将电路板与各类电子元件组装后形成的组装架构，可以与终端200内的各类电子器件电气互连而实现相应的功能。
而当终端200的性能要求越来越高，功能越来越丰富时，会带来更多和更大的尺寸的功能模组(如多目摄像头、屏下指纹模组、屏下发声模组)的装配需求。由于功能模组的布局位置通常与电路板组件100相邻设置，故而当功能模组的尺寸越来越大时，为便于给功能模组预留出更大的布局空间，易导致电路板组件100横向平铺的尺寸越来越小。也即为，功能模组占用空间增大的需求会逐渐挤压电路板组件100的布局空间。由 此，电路板组件100横向尺寸的减小使得单层板结构的布局面积无法满足所有器件的布局要求，使得纵向堆叠的多层板结构应运而生。然而在现有的多层板结构中，受到整机空间的限制以及垂直方向上的空间利用不充分的影响，使得多层器件堆叠结构的布局密度逐渐发展到瓶颈。
由此，本申请实施例提供的电路板组件100不仅能够实现多层器件的纵向堆叠，还能够在终端200内部整机空间的小型化趋势下，最大限度的增加器件的布局面积，实现以空间换取面积，提高器件的布局密度的目的。
电子设备300：
请参阅图2，电子设备300可以包括壳体310和电路板组件100。壳体310为电子设备300的外观结构，能够容置和封装电子设备300的各种部件，使电子设备300的各种部件免受外部灰尘、水汽等的侵扰，具有良好的保护功能。电路板组件100设于壳体310内部，为能够将电路板与各类电子元件组装后形成的组装架构，可以与电子设备300内的各类电子器件电气互连而实现相应的功能。
需说明的是，图2的目的仅在于示意性的描述壳体310和电路板组件100的连接关系，并非是对各个设备的连接位置、具体构造及数量做具体限定。而本申请实施例示意的结构并不构成电子设备300的具体限定。在本申请另一些实施例中，电子设备300可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
可以理解的是，为适应多元化的场景布置需求，电子设备300逐步朝着小型化及超薄化的趋势发展，从而促使电路板组件100的厚度不断降低。现有的板级组装技术中，多层板结构的垂直方向上的空间利用不充分，同时连接相邻两层板的垂直连接结构也会占用板上布局面积，易导致板级布局面积无法得到进一步的提升。也即为，常规多层板结构已难以同时满足器件高密度排布和和多层板结构薄层化的发展需求。
由此，本申请实施例提供的电路板组件100不仅能够实现多层器件的纵向堆叠，还能够在电子设备300内部整机空间的小型化及超薄化的趋势下，最大限度的利用垂直方向上的空间，以增加器件的布局面积，提高器件的布局密度。
基于上述描述，应当理解，本申请实施例提供的电路板组件100应用至终端200或电子设备300时，有利于实现多层器件的纵向堆叠，能够将因堆叠空间利用不充分而导致空间浪费问题发生的可能性降低到最小，有效提高多层器件堆叠结构下器件的布局密度，具体将在下文进行描述。
请结合参阅图3和图4，电路板组件100包括基板10、第一器件21、第二器件22、第一导体31、第二导体32、封装体40和线路结构50。
基板10包括相背设置的上表面101和下表面102，其可用以承载电子元件或其他电路板(printed circuit board，PCB)。示例性地，基板10可以为但不限于为印刷电路板、柔性电路板或软硬结合电路板。
具体而言，当基板10仅用于承载电子元件时，其可以根据基板10上承载的电子元件的数量的不同，而被配置为单面板，也即能够单侧承载电子元件的电路板，从而使得电路板组件100整体呈现为具有单层器件的单层电路板结构。或者，也可被配置为双面 板，也即能够双侧承载电子元件的电路板，从而使得电路板组件100整体呈现为具有双层器件的双层电路板结构。另外，基板10既可以作为独立结构而仅依靠自身呈现单层或双层器件结构，或者，其也可以组装至其他电路板而呈现多层器件堆叠的结构。
而当基板10用于承载其他电路板时，其可以作为主电路板并通过在其上承载一个或多个电路板，进而实现多层电路板的堆叠。或者，其也可以作为过渡的电路板以承载一个或多个电路板，并与主电路板连接，进而实现多层电路板的堆叠。
示例性地，根据基板10上承载的电子元件的类型，基板10可以为但不限于为主板、射频(radio frequency，RF)板、应用处理器(application processor，AP)板。其中，射频板可以用于承载射频芯片(radio frequency integrated circuit，RF IC)、射频功率放大器(radio frequency power amplifier，RF PA)、无线保真(wireless fidelity，WIFI)芯片等。应用处理器板可以用于承载片上系统(system on chip，SOC)元件、双倍数据率(double data rate，DDR)存储器、主电源管理芯片(power management unit，PMU)、辅PMU等。
第一器件21和第二器件22设于基板10的上表面101，且彼此之间具有高度差，其中，第一器件21的高度可理解为第一器件21垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第一器件21本体上，距离基板10最远的一点到该基板10的垂直距离。第二器件22的高度可理解为第二器件22垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第二器件22本体上，距离基板10最远的一点到该基板10的垂直距离。
也即为，第一器件21和第二器件22具有高矮差异，从而当第一器件21和第二器件22同时布局于基板10表面时，第一器件21远离基板10的表面与基板10的垂直距离和第二器件22远离基板10的表面与基板10的垂直距离不相同。换言之，第一器件21和第二器件22布局在基板10上时，能够形成高低不一的视觉效果。
可以理解的是，由于应用电路板组件100的终端200或电子设备300需要具有更多样化的功能，故而布置在基板10上的电子元件也就越来越多。而将布置在基板10上的电子元件分类为第一器件21和第二器件22，能够根据第一器件21和第二器件22的高矮差异而有针对性的对电路板组件100的空间进行布局，有利于缩小电路板组件100所占用的空间，满足电路板组件100的轻薄化和高密化的发展趋势。
示例性地，第一器件21的高度小于第二器件22的高度。也即为，第一器件21相对而言为矮器件，第二器件22相对而言为高器件。第一器件21可以为但不限于为电阻、电容、WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第二器件22可以为但不限于为电容、电感、晶振、NFC(Near Field Communication，近场通信)控制芯片、SOC或UFS(Universal Flash Storage，通用闪存存储)芯片等。
需说明的是，第一器件21的数量可以为一个或多个。当第一器件21的数量为多个时，多个第一器件21可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件21的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第二器件22的数量也可以为一个或多个。当第二器件22的数量为多个时，多个第二器件22可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第二器件22的数量、类型、高度等可以根据实际情况 进行选取，对此不做严格限制。
一种可能的实施方式中，第一器件21的数量为多个，多个第一器件21的平均高度记作H1，第二器件22的数量为多个，多个第二器件22的平均高度记作H2，平均高度H1与平均高度H2的高度差异大于或等于0.2mm。其中，平均高度H1可理解为所有第一器件21的高度之和与第一器件21的总数量的比值，平均高度H2可理解为所有第二器件22的高度之和与第二器件22的总数量的比值。
示例性地，第一器件21的平均高度为1.05mm，第二器件22的平均高度为1.49mm，两者的平均高度的高度差异为0.44mm。
由此，高度差异满足此范围的第一器件21和第二器件22，能够使电路板组件100有针对性的对两类器件上方的空间进行布局，有利于解决因器件高矮差异大所造成的堆叠空间浪费问题，提升多层器件堆叠的器件布局密度。
请继续参阅图3和图4，第一导体31位于基板10的上表面101上第一器件21所在区域，且一端与基板10连接，另一端向远离基板10的方向延伸，其中，第一导体31可以为能够独立实现互连功能的电连接结构，或者，第一导体31也可以为与其他导电结构组装而实现互连功能的电连接结构。
第二导体32位于基板10的上表面101上第二器件22所在区域，且一端与基板10连接，另一端向远离基板10的方向延伸，其中，第二导体32可以为能够独立实现互连功能的电连接结构，或者，第二导体32也可以为与其他导电结构组装而实现互连功能的电连接结构。
由此，设置第一导体31和第二导体32能够分别实现第一器件21和第二器件22的双面互连，有利于缩短布线距离，最大限度的实现短距传输路径，可以有效地以更小的面积或体积承载更好的功率，能够提高电路板组件100整体的功率密度、排布密度和集成化程度。
示例性地，第一导体31自基板10向垂直于基板10的方向延伸。也即为，第一导体31的延伸方向与基板10垂直。第二导体32自基板10向垂直于基板10的方向延伸。也即为，第二导体32的延伸方向与基板10垂直。此设置下，加工和制造都较为简便，且有利于合理利用基板10的板面空间，进一步降低互连结构的布局难度。
本申请的实施例中，布局在第一器件21所在区域的第一导体31的高度高于第一器件21的高度，布局在第二器件22所在区域的第二导体32的高度高于第二器件22的高度，且第一导体31和第二导体32具有高度差，其中，第一导体31的高度可理解为第一导体31连接至基板10的一端到另一端的长度，也即，第一导体31垂直于基板10方向上的尺寸，第二导体32的高度可理解为第二导体32连接至基板10的一端到另一端的长度，也即，第二导体32垂直于基板10方向上的尺寸。
也即为，第一导体31和第二导体32具有高矮差异，从而当第一导体31和第二导体32同时布局于基板10表面时，能够形成高低不一的视觉效果。换言之，第一导体31连接至基板10的一端到另一端的长度与第二导体32连接至基板10的一端到另一端的长度不相同。
需说明的是，第一导体31和第二导体32的相对高低会随着所在区域的第一器件21 和第二器件22的相对高低而发生变化，当第一器件21的高度小于第二器件22的高度时，第一导体31的高度会小于第二导体32的高度，反之亦然。
可以理解的是，由于第一器件21和第二器件22具有高度差异，为充分利用器件之间的高度差异，故而布置在对应区域的第一导体31和第二导体32也相应的具有高度差异。此设置下，在基板10的板面区域内，设置高器件的区域会设置高度较高的电连接结构，设置矮器件的区域会设置高度较低的电连接结构。由此，第一导体31和第二导体32的高度能够根据不同高度的器件灵活调整，以充分适配高矮器件的布局差异，避免因将第一导体31和第二导体32设置为统一高度而造成较矮器件上方的空间浪费，还有利于减少加工、生产和物料管理成本，可靠性佳。
示例性地，第一导体31的高度小于第二导体32的高度。也即为，第一导体31相对而言为高度较高的电连接结构，第二导体32相对而言为高度较低的电连接结构。而第一导体31的数量可为多个，多个第一导体31间隔排布于第一器件21所在区域，且多个第一导体31的高度相同。第二导体32的数量可为多个，多个第二导体32间隔排布于第二器件22所在区域，且多个第二导体32的高度相同。由此，在矮器件所在区域统一设置相同高度的第一导体31，并在高器件所在区域也统一设置相同高度的第二导体32，能够避免同区域内导体高度不一而造成的制造困难度和复杂度增加，使得加工较为简便和快捷。
一种可能的实施方式中，第一导体31和第二导体32之间的高度差值大于或等于0.2mm。
由此，高度差异满足此范围的第一导体31和第二导体32，能够充分适配高矮器件的布局差异，有利于解决因器件高矮差异大所造成的堆叠空间浪费问题，提升多层器件堆叠的器件布局密度。
封装体40连接至基板10设有第一器件21和第二器件22的一侧，并可将第一器件21和第二器件22封装。应当理解，封装体40封装第一器件21和第二器件22的同时，也会接触第一导体31和第二导体32。由此，能够保护第一器件21和第二器件22不易受外部环境因素的干扰，为第一器件21和第二器件22提供良好的电磁屏蔽性能，并能通过第一导体31和第二导体32的电连接作用而为实现第一器件21和第二器件22的短距离双面互连提供良好的基础。
示例性地，封装体40可采用绝缘的树脂材料制成，树脂材料可以为酚醛树脂、环氧树脂、双马来酰亚胺三嗪树脂、环氧丙烯酸酯、聚丙二醇(Poly propylene glycol，PPG)、含有玻璃纤维的环氧树脂或含有玻璃纤维的环氧丙烯酸酯等。
请继续参阅图3和图4，封装体40包括第一封装器件区41和第二封装器件区42，其中，第一封装器件区41和第二封装器件区42可理解为构成封装体40的两个组成部分。示例性地，第一封装器件区41和第二封装器件区42邻接设置，也即为，第一封装器件区41和第二封装器件区42相互连接并共同构成封装体40。
而封装体40的外表面可理解为封装体40背离基板10的表面，其包括第一封装器件区41的外表面和第二封装器件区42的外表面。而第一封装器件区41的外表面可理解为第一封装器件区41背离基板10的表面。第二封装器件区42的外表面可理解为第二封装 器件42区背离基板10的表面。
具体而言，第一封装器件区41包覆第一器件21而将第一器件21封装在基板10上并包围第一导体31。也即为，第一导体31位于第一封装器件区41，且一端与基板10连接，另一端与第一封装器件区41背离基板10的表面连接，其中，第一导体31的另一端与第一封装器件区41背离基板10的表面连接包括两者直接连接或两者通过中间媒介而间接连接。
第二封装器件区42包覆第二器件22而将第二器件22封装在基板10上并包围第二导体32。也即为，第二导体32位于第二封装器件区42，且一端与基板10连接，另一端与第二封装器件区42背离基板10的表面连接，其中，第二导体32的另一端与第二封装器件区42背离基板10的表面连接包括两者直接连接或两者通过中间媒介而间接连接。
可以理解的是，通过在基板10上设置高度不同的第一器件21和第二器件22，并在第一器件21所在的区域布局第一导体31，在第二器件22所在的区域布局第二导体32，能够使封装第一器件21的第一封装器件区41的高度适配第一导体31的高度，封装第二器件22的第二封装器件区42的高度适配第二导体32的高度。又因第一导体31与第二导体32具有高度差异，故而第一封装器件区41和第二封装器件区42的高度能够以第一导体31和第二导体32的高度差异为参照而呈现高低不平的外观形态。也即为，能够使封装体40整体呈现高低起伏的外观形态。
由此，封装体40的各个部分的高度能够恰好对应所封装的器件高度，使得封装体40能够适配高矮器件的高度差异也呈现具有阶梯化高度的布局设置。一方面，能够根据器件的高矮差异而有针对性的布局适宜高度的导体和封装体40，有效避免了使封装体40和导体整体设置为统一高度所造成的材料浪费的问题，有利于减小物料和生产成本。另一方面，利用高矮器件之间的高度差异而使封装体40各部分的高度实现高矮器件错配，能够最大限度的减少因以高器件的高度作为参照而使封装体40整体设置为统一高度，而造成的矮器件上方的空间虚耗。有利于合理利用垂直于基板10方向上的空间，解决因器件高矮差异大所造成的堆叠空间浪费问题，并可在应用至多层堆叠结构时使得空间利用率最大化，提升多层器件堆叠的器件布局密度。
另外，相较于现有技术中在基板10上设置框架板实现互连，并在框架板上设置较多的用于增强可靠性和实现电磁屏蔽性能的非功能引脚。在基板10上设置可靠性较强的封装体40，能够使封装体40自身用作电磁屏蔽性能，从而最大限度的减小用于电屏蔽和可靠性增强的非功能性引脚。也即为，有利于最大限度的减小电路板组件100的非功能引脚，以减小板面面积的浪费。
基于上述描述，应当理解，第一封装器件区41和第二封装器件区42具有高度差，其中，第一封装器件区41的高度可理解为第一封装器件区41连接至基板10的一端到另一端的长度。也即，第一封装器件区41垂直于基板10方向上的尺寸，具体而言，尺寸是指，第一封装器件区41背离基板10的表面到基板10的上表面101的垂直距离。第二封装器件区42的高度可理解为第二封装器件区42连接至基板10的一端到另一端的长度。也即，第二封装器件区42垂直于基板10方向上的尺寸，具体而言，尺寸是指，第二封装器件区42背离基板10的表面到基板42的上表面101的垂直距离。
由此，当第一封装器件区41和第二封装器件区42同时布局于基板10表面时，第一封装器件区41远离基板10的表面与基板10的垂直距离和第二封装器件区42远离基板10的表面与基板10的垂直距离不相同。换言之，封装体40设置在基板10上时，能够形成高低不平的视觉效果。
需说明的是，第一封装器件区41和第二封装器件区42的相对高低会随着内部设置的第一导体31和第二导体32以及内部封装的第一器件21和第二器件22的相对高低而发生变化，当第一器件21的高度小于第二器件22的高度时，第一导体31的高度会小于第二导体32的高度，相应地第一封装器件区41的高度也会小于第二封装器件区42的高度，反之亦然。
一种可能的实施方式中，第一封装器件区41和第二封装器件区42之间的高度差值大于或等于0.2mm。
由此，高度差异满足此范围的第一封装器件区41和第二封装器件区42，能够充分适配高矮器件的布局差异，有利于解决因器件高矮差异大所造成的堆叠空间浪费问题，提升多层器件堆叠的器件布局密度。
可以理解的是，由于第一封装器件区41和第二封装器件区42具有高度差值，故而根据第一封装器件区41和第二封装器件区42数量的配置，封装体40背离基板10的表面可形成一个或多个台阶结构404。由此，具有阶梯高度的台阶结构404使得在其上再次组装器件时，相对于平面结构更能够提供差异化和多元化的器件配置。也即为，能够在台阶结构404距离基板10垂直距离较小处组装相对更高的器件，在台阶结构404距离基板10垂直距离较大处组装相对更矮的器件，使得不同高度的器件被组装至其上时，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件100整体的厚度，并使在同一大小的空间下布局更多层器件的可能性成为现实。
如下以第一器件21的高度小于第二器件22的高度，且封装第一器件21的第一封装器件区41的高度小于封装第二器件22的第二封装器件区42的高度为例来详细说明第一封装器件区41和第二封装器件区42数量差异所能形成的一个或多个阶梯布局。其中，第一封装器件区41和第二封装器件区42数量差异可理解为第一器件21和第二器件22布局的区域数量的差异。
一种可能的实施方式中，第一封装器件区41的数量为一个，第二封装器件区42的数量为一个，故而封装体40背离基板10的表面能够形成如图4所示的一个台阶结构404。
另一种可能的实施方式中，第一封装器件区41的数量为一个，第二封装器件区42的数量为两个，故而封装体40背离基板10的表面能够形成如图5所示的两个台阶结构404。
又一种可能的实施方式中，第一封装器件区41的数量为两个，第二封装器件区42的数量为一个，故而封装体40背离基板10的表面能够形成如图6所示的两个台阶结构404。
再一种可能的实施方式中，第一封装器件区41的数量为多个，第二封装器件区42的数量为多个，第一封装器件区41和第二封装器件区42交错排布，故而封装体40背离基板10的表面能够呈现图7所示的多个台阶结构404。也即为，每相邻的两个第一封装 器件区41之间具有一个第二封装器件区42，每相邻的两个第二封装器件区42之间具有一个第一封装器件区41。
基于上述描述，应当理解，根据基板10上的高矮器件的布局区域的数量配置第一封装器件区41和第二封装器件区42的数量，能够使位于封装体40内部的器件高矮分类集中布局，进而使封装体40整体呈现一个或多个的阶梯布局，从而使具有高度差的封装体40能够适配其内部电子器件的高低不一。有利于充分利用垂直于基板10方向上的空间，减小电路板组件100的厚度，使应用电路板组件100的设备更适于小型化及超薄化的发展趋势。
请结合参阅图3和图4，封装体40背离基板10的表面包括第一顶面401、第二顶面402和连接面403，其中，第一顶面401、第二顶面402和连接面403均可理解为封装体40的外表面。第一顶面401为第一封装器件区41背离基板10的表面，第二顶面402为第二封装器件区42背离基板10的表面，连接面403连接在第一顶面401和第二顶面402之间，第一顶面401、连接面403和第二顶面402依次弯折连接形成台阶结构404。也即为，第一顶面401、连接面403和第二顶面402依次连接并构成封装体40背离基板10的表面。
示例性地，如图8所示，连接面403可以是垂直于基板10的平面，从而能够使第一顶面401和第二顶面402之间形成直角过渡。或者，如图9所示，连接面403可以是与基板10呈夹角也即倾斜设置的平面，从而能够使第一顶面401和第二顶面402之间形成斜角过渡。或者，如图10所示，连接面403也可以是弧面，从而能够使第一顶面401和第二顶面402之间形成圆弧过渡。由此，能够使得台阶结构404具有多样化的形貌，以根据不同的场景而相应的设置不同的过渡形式，有利于多场景化的应用需求。
可以理解的是，由于第一顶面401为第一封装器件区41背离基板10的表面，第二顶面402为第二封装器件区42背离基板10的表面，故而第一导体31的另一端可与第一顶面401连接，第二导体32的另一端可与第二顶面402连接。如下将以第一导体31的另一端与第一顶面401通过中间媒介而间接连接，第二导体32的另一端与第二顶面402通过中间媒介而间接连接为例进行说明，但应当理解，并不以此为限。
请参阅图3，电路板组件100还包括第一过孔33、第二过孔34、第一电镀金属35和第二电镀金属36。
第一过孔33与第一导体31对应设置，第一过孔33连接第一导体31远离基板10的一端和第一顶面401(也即第一封装器件区41的外表面)。也即为，第一过孔33连接在第一导体31和第一顶面401之间。换言之，第一导体31与第一封装器件区41的外表面通过第一过孔33连接。
第二过孔34与第二导体32对应设置，第二过孔34连接第二导体32远离基板10的一端和第二顶面402(也即第二封装器件区42的外表面)。也即为，第二过孔34连接在第二导体32和第二顶面402之间。换言之，第二导体32与第二封装器件区42的外表面通过第二过孔34连接。
第一过孔33内填充有第一电镀金属35，第一电镀金属35连接第一导体31远离基板10的一端和第一顶面401(也即第一封装器件区41的外表面)；第二过孔34内填充有 第二电镀金属36，第二电镀金属36连接第二导体32远离基板10的一端和第二顶面402(也即第二封装器件区42的外表面)。
通过设置第一过孔33、第二过孔34、第一电镀金属35和第二电镀金属36，能够实现封装体40外表面与内部器件的电气连接，并使得贯穿封装体40的互连结构相对于现有技术而言能穿过更厚的封装体40。示例性地，第一导体31可以为金线或植针，第二导体32可以为金线或植针。
应当理解，第一填充金属35填充在第一过孔33内可理解为在孔类结构中填充导电金属而形成的具有导电性能的电连接结构，第二填充金属36填充在第二过孔34内也可理解为在孔类结构中填充导电金属而形成的具有导电性能的电连接结构。示例性地，第一过孔33和第二过孔34的高度相同，从而使加工和制造都较为简便。或者，第一过孔33和第二过孔34的高度不相同，从而能够根据各导体的高度而相应的对金属过孔的高度进行调整，灵活性强。其中，第一过孔33的高度可理解为第一过孔33连接至第一导体31的一端到另一端的长度，也即，第一过孔33垂直于基板10方向上的尺寸。第二过孔34的高度可理解为第二过孔34连接至第二导体32的一端到另一端的长度，也即，第二过孔34垂直于基板10方向上的尺寸。
由此，第一过孔33、第一电镀金属35与第一导体31连接构成第一导电结构37，第一导电结构37贯穿第一封装器件区41。第二过孔34、第二电镀金属36与第二导体32连接构成第二导电结构38，第二导电结构38贯穿第二封装器件区42。此设置下，相对于现有技术中在基板10上设置框架板以实现上下层的互连所导致的出线位置受限于板面的外周，非出线区占用的板面面积较大的问题。在封装体40内部设置能够实现双面互连的第一导电结构37和第二导电结构38，能够使I/O(Input/Output，输入/输出)出线的布局位置不受影响，可随应用需求而相应被布置在封装体40内的任意位置。一方面，能够节省框架板所占用的板面面积和空间大小，提高整体的出线面积，从而提升器件的布局面积。另一方面，能够使设置在封装体40内部的器件就近出线，有利于简化走线复杂度和实现线路的最短连接。
可以理解的是，现有技术中，框架板中相邻两个通孔之间的孔间距过小后，在长期的电压差条件下，高电压的通孔易长出导电丝，导电丝易到达低电压的通孔而使两个通孔短路。也即为，当前通孔的间距已达到极限，无法进一步密集排布。示例性地，相邻两个通孔之间的中心距为0.5mm。
由此，本申请的实施例中，设置第一导电结构37和第二导电结构38还能突破现有技术的互连结构无法进一步密集排布的布局，使得相邻两个互连结构之间的距离能够最大限度的缩短，有利于实现高密化排布。示例性地，相邻两个导电结构的中心距小于或等于0.4mm。
一种可能的实施方式中，第一导电结构37的数量为多个，多个第一导电结构37中的一者或多者的深宽比在5:1～15:1的范围内，和/或，第二导电结构38的数量为多个，多个第二导电结构38中的一者或多者的深宽比在5:1～15:1的范围内。
其中，第一导电结构37的深宽比可以理解为第一导电结构37的深度与第一导电结构37的宽度的比值，具体为第一导电结构37的深度除以第一导电结构37的宽度所得到 的数值。而第一导电结构37的深度可理解为第一导电结构37连接至基板10的一端到另一端的长度(可等同于第一导电结构37的高度)，第一导电结构37的宽度可理解为以平行于基板10的参考面截取第一导电结构37，截取出的横截面的直径(宽度)尺寸。
需说明的是，第一导电结构37的深宽比的具体数值既可以为整数数值，也可以为具有小数的数值，只需满足在5:1～15:1的范围内(包括端点值)即可，对此不做严格限制。
第二导电结构38的深宽比可以理解为第二导电结构38的深度与第二导电结构38的宽度的比值，具体为第二导电结构38的深度除以第二导电结构38的宽度所得到的数值。而第二导电结构38的深度可理解为第二导电结构38连接至基板10的一端到另一端的长度(可等同于第二导电结构38的高度)，第二导电结构38的宽度可理解为以平行于基板10的参考面截取第二导电结构38，截取出的横截面的直径(宽度)尺寸。
需说明的是，第二导电结构38的深宽比的具体数值既可以为整数数值，也可以为具有小数的数值，只需满足在5:1～15:1的范围内(包括端点值)即可，对此不做严格限制。
由此，相对于现有技术中内较低的深宽比，由导体和金属过孔共同构成的导电结构能够实现更高的深宽比，并使得贯穿封装体40的互连结构相对于现有技术而言能穿过更厚的封装体40，有利于适应多场景的应用需求。
请继续参阅图3，线路结构50设于封装体40背离基板10的表面，并电连接至第一导体31和第二导体32。也即为，线路结构50能够自第一封装器件区41而延伸至第二封装器件区42，并导通第一导体31和第二导体32。应当理解，由于线路结构50设于封装体40背离基板10的表面，故而线路结构50的形态会跟随封装体40背离基板10的表面的形态变化而变化。也即为，封装体40背离基板10的表面呈台阶状，线路结构50也会相应地呈现台阶状。由此，以封装体40表面的阶梯线路替代现有技术中的平面的电路板，有助于实现多层器件布局的高低错配，能够最大限度的提高空间利用率，降低电路板组件100的整体厚度。
而通过设置线路结构50，能够使得封装体40背离基板10的表面具有起到电性连接作用的线路层，能够为实现封装于封装体40内的第一器件21和第二器件22的双面互连提供良好的基础，有利于在局限化的空间布局内实现最短的互连路径及实现电路板组件100的薄型封装，实用性强，可靠性佳。
请结合参阅图11和图12，具体而言，线路结构50包括第一焊盘51、第二焊盘52和连接焊盘53，第一焊盘51设于第一封装器件区41背离基板10的表面且与第一导电结构37电连接，第二焊盘52设于第二封装器件区42背离基板10的表面且与第二导电结构38电连接，连接焊盘53覆盖第一封装器件区41和第二封装器件区42的连接处且与第一导电结构37或第二导电结构38电连接。
也即为，第一焊盘51设于第一顶面401，第二焊盘52设于第二顶面402，连接焊盘53设于连接面403，并可根据需要而延伸至第一顶面401和/或第二顶面402。而第一焊盘51、第二焊盘52和连接焊盘53均为功能性焊盘，其可以起到电连接、机械固定等作用。也就是说，如果多个元器件(例如可以是电路板、电子元件)通过功能性焊盘相连，则可以通过功能性焊盘传输该多个元器件之间的电信号。
换言之，第一焊盘51、第二焊盘52和连接焊盘53上均能够设置电子器件，从而不 仅封装体40内部具有电子器件，封装体40的外部也可继续堆叠器件而形成多层堆叠架构，有利于实现器件的高密化排布。
需说明的是，本申请的实施例对于第一焊盘51、第二焊盘52和连接焊盘53的数量不做限制，其可以根据实际情况进行选取，仅需满足能够连接电子器件即可。
本申请的实施例中，由于封装体40背离基板10的表面能够形成一个或多个台阶结构404，而台阶结构404是由第一封装器件区41和第二封装器件区42的高度差异而形成的，故而设置在第一封装器件区41上的第一焊盘51与基板10之间的垂直距离和设置在第二封装器件区42上的第二焊盘52与基板10之间的垂直距离不相同。
此设置下，在封装体40上再次堆叠器件时，能够将不同高度的器件布局在距基板10距离不同的平面上，从而能够利用不同平面上的焊盘之间的垂直距离，而最大限度的抵消器件之间的高度差异，相对于现有技术中仅能将器件设置于同一平面的焊盘，能够在相同空间大小和器件数量的限制下，有效避免器件叠层数量的增加，有利于器件的高密化排布。
而由于第一封装器件区41和第二封装器件区42的连接处呈台阶状，故而覆盖第一封装器件区41和第二封装器件区42连接处的连接焊盘53也呈台阶状。此设置下，连接焊盘53可区别于平面状的焊盘而呈现立体形态，也即为，连接焊盘53能够适应封装体40的过渡处的台阶变化而被布置在台阶处，从而有效避由此，能够根据电路板组件100的布线需求而对线路结构50的组成灵活调整，有利于适应多场景下的应用需求。免了封装体40上可布局器件面积的浪费，并增加了焊盘的数量。而焊盘数量的增加可等同于可供设置的器件的数量的增加，相当于提高了器件的布局密度，有利于适应器件的高密化排布需求。
请继续参阅图11和图12，本申请的实施例中，线路结构50可以包括一个或多个层叠设置的子线路结构54。
具体而言，如图11所示，当线路结构50包括一个子线路结构54时，相当于单层线路构成了线路结构50。也即为，第一焊盘51、第二焊盘52和连接焊盘53相应地也为单层结构。如图12所示，当线路结构50包括多个子线路结构54时，多个子线路结构54层叠设置，相邻两个子线路结构54之间具有一层绝缘层57。绝缘层57包括连接结构58，,相邻两个子线路结构54通过贯穿绝缘层57的连接结构58彼此电连接。也即为，第一焊盘51、第二焊盘52和连接焊盘53相应地也为多层结构。此设置下，各个焊盘均为多层结构，且相邻两个焊盘之间能够通过绝缘层57的间隔而避免产生桥接的问题，有利于长期保护所形成的线路图形。而在封装体40上形成多层子线路结构54，还能够构成一定的互联系统，使用于互连的设于封装体40内部的第一导体31和第二导体32的数量能够相应地有所减少。
一种可能的实施方式中，封装体40背离基板10的表面上需要焊接的线路和基材可被暴露而相应地形成第一焊盘51、第二焊盘52和连接焊盘53，而不需要焊接的线路和基材能够形成阻焊层(图未示)而被遮挡。
一方面能够避免焊料浪费，防止焊接工艺中因焊料桥接而产生的电气短路问题，有利于长期保护所形成的线路图形。另一方面因阻焊层具有良好的绝缘性能，有利于防止 因灰尘、水汽等外界环境因素造成的绝缘恶化、腐蚀等问题的发生，能够使得电路的高密度化成为可能。
本申请的实施例中，与基板10组装后的器件可被塑封而形成台阶形的封装体40，而在封装体40的表面再次组装器件和/或以基板10作为上层板而与多层板组装，均能够实现多层器件的堆叠。如下将通过四个具体实施例而对本申请的实施例中多层器件的堆叠可能性进行说明，其中，基板10上的第一器件21和第二器件22构成电路板组件100的第一层器件20。
第一实施例：
请参阅图13，电路板组件100还包括第二层器件61，第二层器件61设于封装体40背离基板10的表面，以实现两层器件堆叠架构。由此，在封装体40上二次组装器件，等同于增加了封装体40背离基板10表面的布局面积，能够使得电路板组件100整体增加一层器件，有效提升多层架构下器件的排布密度。
需说明的是，第二层器件61可以为同样高度的电子器件，也可以为具有高矮差异的电子器件，如下将以第二层器件61为具有高矮差异的电子器件为例进行说明，但应当理解，并不以此为限。
具体而言，第二层器件61包括第三器件611和第四器件612，第三器件611的高度可理解为第三器件611垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第三器件611本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。第四器件612的高度可理解为第四器件612垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第四器件612本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。
而第三器件611和第四器件612具有高度差，其中，高度可理解为垂直于基板10方向的尺寸。也即为，第三器件611和第四器件612具有高矮差异，两者相较而言，一者为高器件，另一者为矮器件。示例性地，第三器件611可以为但不限于为电阻、电容、WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第四器件612可以为但不限于为电容、电感、晶振、NFC控制芯片、SOC或UFS芯片等。
需说明的是，第三器件611的数量可以为一个或多个。当第三器件611的数量为多个时，多个第三器件611可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件21的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第四器件612的数量也可以为一个或多个。当第四器件612的数量为多个时，多个第四器件612可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第四器件612的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
可以理解的是，由于应用电路板组件100的终端200或电子设备300需要具有更多样化的功能，故而布置的电子元件也就越来越多。而将电子元件分类为第三器件611和第四器件612，能够根据第三器件611和第四器件612的高矮差异而有针对性的对电路板组件100的空间进行布局，有利于缩小电路板组件100所占用的空间，满足电路板组件 100的轻薄化和高密化的发展趋势。
如下将以第一器件21的高度小于第二器件22的高度，第三器件611的高度小于第四器件612的高度为例进行说明，但应当理解，并不以此为限。
一种可能的实施方式中，如图13所示，第三器件611设于第二顶面402，第四器件612设于第一顶面401。从而形成第一器件21与第四器件612对应设置，第二器件22与第三器件611对应设置的器件布局。也即为，能够实现封装体40内部矮器件搭配封装体40外部高器件，封装体40内部高器件搭配封装体40外部矮器件的高矮错落分配。
此设置下，在封装体40的表面二次组装器件，一方面，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件100整体的厚度。另一方面，能够充分利用垂直空间，实现空间利用率的最大化，以突破多层器件堆叠架构下，器件高矮差异大造成的堆叠空间浪费问题，使在同一大小的空间下布局更多层器件的可能性成为现实，提升多层器件堆叠架构的器件布局密度。
另一种可能的实施方式中，第三器件611设于第一顶面401，第四器件612设于第二顶面402。由此，利用第一封装器件区41和第二封装器件区42之间的高度差异，能够最大限度的抵消器件之间的高度差异，相对于现有技术中仅能将器件设置于同一平面，能够在相同空间大小和器件数量的限制下，有效避免器件叠层数量的增加，有利于器件的高密化排布。
请参阅图14，示例性地，电路板组件100还可包括屏蔽框91，屏蔽框91罩设于封装体40背离基板10的表面，且包围第二层器件61，以使电路板组件100整体具有良好的电磁屏蔽性能。其中，屏蔽框91既可以采用金属材料制成，也可以采用非金属材料制成并在非金属材料的表面增加导电镀层。
第二实施例：
本实施例中，与第一实施例相同的内容不再赘述，与第一实施例不同的是，基板10为双面板，能够双侧承载电子元件，以实现三层器件堆叠架构。
请参阅图15，电路板组件100还包括第三层器件62，第三层器件62设于基板10背离封装体40的表面，也即基板10的下表面102。由此，将基板10由单面板优化为双面板，等同于增加了基板10一个面的布局面积，能够使得电路板组件100整体增加一层器件，空间利用率更高，能够有效提升多层架构下器件的排布密度。
需说明的是，第三层器件62的数量可以为一个或多个。当第三层器件62的数量为多个时，多个第三层器件62可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第三层器件62的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
一种可能的实施方式中，如图15所示，电路板组件100还包括封装结构70，封装结构70将第三层器件62封装于基板10上。其中，封装结构70可参照第一实施例的封装体40而呈现阶梯状的外观形态，或者，封装结构70也可整体呈现高度一致的外观形态，对此不做严格限制。
由此，基板10的双面均能够实现塑封，而基板10双面塑封的翘曲程度会比基板10单面塑封的翘曲程度更小，有利于提高封装的平整度。
第三实施例：
本实施例中，与第二实施例相同的内容不再赘述，与第二实施例不同的是，将基板10整体作为上层板而与其他板进行组装，以实现四层器件堆叠架构。
请参阅图16，电路板组件100还包括电路板80、架高板90和第四层器件63。电路板80与基板10间隔层叠，架高板90连接在基板10和电路板80之间。基板10、电路板80和架高板90围成腔体A，第四层电路板80设于电路板80朝向基板10的表面，第三层器件62和所述第四层器件63均位于腔体A内。
由此，采用多层板堆叠技术，等同于增加了电路板80一个面的布局面积，能够使得电路板组件100整体增加一层器件，空间利用率更高，能够有效提升多层架构下器件的排布密度。
具体而言，第三层器件62包括第五器件621和第六器件622。第五器件621的高度可理解为第五器件621垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第五器件621本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。第六器件622的高度可理解为第六器件622垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第六器件622本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。
而第五器件621和第六器件622具有高度差，其中，高度可理解为垂直于基板10方向的尺寸。也即为，第五器件621和第六器件622具有高矮差异，两者相较而言，一者为高器件，另一者为矮器件。示例性地，第五器件621可以为但不限于为电阻、电容、WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第六器件622可以为但不限于为电容、电感、晶振、NFC控制芯片、SOC或UFS芯片等。
需说明的是，第五器件621的数量可以为一个或多个。当第五器件621的数量为多个时，多个第五器件621可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件21的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第六器件622的数量也可以为一个或多个。当第六器件622的数量为多个时，多个第六器件622可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第六器件622的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
请继续参阅图16，第四层器件63包括第七器件631和第八器件632。第七器件631的高度可理解为第七器件631垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第七器件631本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。第八器件632的高度可理解为第八器件632垂直于基板10方向上的尺寸，具体而言，尺寸是指：在第八器件632本体上，距离基板10最远的一点到距离该基板10最近的一点的垂直距离。
而第七器件631和第八器件632具有高度差，其中，高度可理解为垂直于基板10方向的尺寸。也即为，第七器件631和第八器件632具有高矮差异，两者相较而言，一者为高器件，另一者为矮器件。示例性地，第七器件631可以为但不限于为电阻、电容、 WIFI芯片、基带芯片、射频芯片或电源管理芯片等。第八器件632可以为但不限于为电容、电感、晶振、NFC控制芯片、SOC或UFS芯片等。
需说明的是，第七器件631的数量可以为一个或多个。当第七器件631的数量为多个时，多个第七器件631可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第一器件21的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
第八器件632的数量也可以为一个或多个。当第八器件632的数量为多个时，多个第八器件632可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第八器件632的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
可以理解的是，由于应用电路板组件100的终端200或电子设备300需要具有更多样化的功能，故而布置的电子元件也就越来越多。而将第三层器件62分类为第三器件611和第四器件612，将第四层器件63分类为第五器件621和第六器件622，能够根据各器件的高矮差异而有针对性的对电路板组件100的空间进行布局，有利于缩小电路板组件100所占用的空间，满足电路板组件100的轻薄化和高密化的发展趋势。
如下将以第五器件621的高度小于第六器件622的高度，第七器件631的高度小于第八器件632的高度为例进行说明，但应当理解，并不以此为限。
一种可能的实施方式中，如图16所示，第五器件621与第八器件632对应设置，第六器件622与第七器件631对应设置。也即为，能够实现在腔体A内实现矮器件搭配高器件，高器件搭配矮器件的高矮错落分配。
此设置下，在电路板组件100内部采用两次器件的高矮错位布局，一方面，能够呈现一个较为平整的布局设置，有利于在局限化的空间布局里压缩电路板组件100整体的厚度。另一方面，能够充分利用垂直空间，极大的压缩厚度空间，实现空间利用率的最大化，以突破多层器件堆叠架构下，器件高矮差异大造成的堆叠空间浪费问题，使在同一大小的空间下布局更多层器件的可能性成为现实，提升多层器件堆叠架构的器件布局密度。
另一种可能的实施方式中，第五器件621与第七器件631对应设置，第六器件622与第八器件632对应设置。
第四实施例：
本实施例中，与第三实施例相同的内容不再赘述，与第三实施例不同的是，电路板80为双面板，能够双侧承载电子元件，以实现五层器件堆叠架构。
请参阅图17，电路板组件100还包括第五层器件64，第五层器件64设于电路板80背离第四层器件63的表面。由此，将电路板80由单面板优化为双面板，等同于增加了电路板80一个面的布局面积，能够使得电路板组件100整体增加一层器件，空间利用率更高，能够有效提升多层架构下器件的排布密度。
另外，由于封装体40表面阶梯线路的应用，使得器件布局高矮错配，五层器件的堆叠厚度与现有技术中四层器件的堆叠厚度相当，相当于在同样的立体空间条件下，多增加一层器件布局，最大限度的提高空间利用率，有利于器件的高密化排布需求。
需说明的是，第五层器件64的数量可以为一个或多个。当第五层器件64的数量为多个时，多个第五层器件64可以为相同类型的器件，也可以为不同类型的器件，其可以具有相同的高度，也可以具有不同的高度。也即为，第五层器件64的数量、类型、高度等可以根据实际情况进行选取，对此不做严格限制。
本申请的实施例还提供一种电路板组件100的制作方法，关于电路板组件100的结构请参阅图1-图17以及前述描述，在此不在赘述。请参阅图18，电路板组件100的制作方法至少可以包括S100、S200和S300，详细描述如下。
S100：提供基板10。
S200：在基板10上贴装第一器件21和第二器件22，且在第一器件21所在区域形成第一导体31，在第二器件22所在区域形成第二导体32，其中，第一器件21与第二器件22具有高度差，第一导体31的一端与基板10连接，另一端向远离基板10的方向延伸，第二导体32的一端与基板10连接，另一端向远离基板10的方向延伸，第一导体31与第二导体32具有高度差。
S300：在基板10的上表面101形成封装体40，其中，封装体40包括第一封装器件区41和第二封装器件区42，第一封装器件区41和第二封装器件区42具有高度差。
以下将对各个步骤分别进行进一步的描述。
以下将结合图3和图4来描述上述的步骤S100。
S100：提供基板10。
可以理解的是，基板10具体可以通过压合、钻孔、电镀、图形、阻焊和表面处理等工艺形成。示例性地，基板10可以为单侧承载电子元件的电路板80。或者，基板10可以为双侧均可承载电子元件的电路板80。
以下将结合图15、图18和图19来描述上述的步骤S200。
S200：在基板10上贴装第一器件21和第二器件22，且在第一器件21所在区域形成第一导体31，在第二器件22所在区域形成第二导体32，其中，第一器件21与第二器件22具有高度差，第一导体31的一端与基板10连接，另一端向远离基板10的方向延伸，第二导体32的一端与基板10连接，另一端向远离基板10的方向延伸，第一导体31与第二导体32具有高度差。
可以理解的是，在在基板10上贴装第一器件21和第二器件22的过程中，可在第一器件21所在区域形成第一导体31，在第二器件22所在区域形成第二导体32。
如图19和图20所示，在基板10贴装器件的过程中，在基板10上沿垂直于基板10的方向竖直打第一导体31和第二导体32，形成自基板10竖直而上的导电良体。而第一导体31和第二导体32的相对高低会随着所在区域的第一器件21和第二器件22的相对高低而发生变化，当第一器件21的高度小于第二器件22的高度时，第一导体31的高度会小于第二导体32的高度，反之亦然。示例性地，第一器件21与第二器件22的高度差异可等同于第一导体31与第二导体32之间的高度差异。
如图15所示，当基板10为双侧均可承载电子元件的电路板80时，在基板10相背设置的两个表面的其中一个表面贴装第一器件21和第二器件22(两者构成第一层器件)的同时，也可在另一个表面贴装第三层器件62。其中，第三层器件62可以为高度一致的 器件，或者，第三层器件62也可以为具有高度差的器件。
以下将结合图11、图18、图19和图20来描述上述的步骤S300。
S300：在基板10上形成封装体40，其中，封装体40包括第一封装器件区41和第二封装器件区42，第一封装器件区41和第二封装器件区42具有高度差。
其中，第一封装器件区41包覆第一器件21，且第一封装器件区41的外表面与第一导体31连接，第二封装器件区42包覆第二器件22，且第二封装器件区42的外表面与第二导体32连接。
可以理解的是，第一导体31和第二导体32可以直接与封装体40的外表面连接也可以通过中间媒介而间接连接，如下将仅以通过间接媒介连接为例进行说明，但应当理解，并不以此为限。
其中，当基板10为双侧均可承载电子元件的电路板80时，在基板10相背设置的两个表面的其中一个表面形成封装第一器件21和第二器件22的封装体40的同时，在另一个表面形成封装第三层器件62的封装结构70。其中，封装结构70可参照封装体40而为阶梯状的外观形态，或者，封装结构70也可以为高度一致的外观形态。
其次，请结合参阅图20、图21、图22-图26，在在基板10上形成封装体40之后，电路板组件100的制作方法还至少包括S310、S320、S330和S340，详细描述如下：
S310：在第一封装器件区41的外表面和在第二封装器件区42的外表面分别形成露出第一导体31的第一过孔33和露出第二导体32的第二过孔34。
示例性地，如图20所示，可在第一导体31和第二导体32的对应位置，使用激光烧蚀封装体40的表面而形成小孔，以露出第一导体31和第二导体32。
S320：在第一过孔33内填充第一电镀金属35和在第二过孔34内填充第二电镀金属36，以使第一过孔33、第一电镀金属35与第一导体31电连接形成第一导电结构37，第二过孔34、第二电镀金属36与第二导体32电连接形成第二导电结构38。
示例性地，如图20所示，可电镀填平小孔，以形成自基板10延伸至封装体40背离基板10的表面的贯穿封装体40的具有大深宽比的I/O互连线路。
S330：在封装体40的外表面形成与第一导电结构37和第二导电结构38电连接的线路结构50。
请结合参阅图11、图22和图23，一种可能的实施方式中，线路结构50包括一个子线路结构54，也即为，线路结构50为单层线路结构50。
具体而言，单层线路结构50的形成至少包括如下步骤：
S331：在封装体40的外表面形成铜层55。
由此，铜层55能够自第一封装器件区41延伸至第二封装器件区42。也即为，铜层55能够均匀覆盖第一顶面401、连接面403和第二顶面402。
S332：在铜层55表面形成干膜56。
由此，干膜56能够与铜层55贴合紧密且无气泡产生。
S333：对干膜56进行曝光及显影处理。
由此，能够留下所需的线路图形。
S334：以干膜56为掩膜而蚀刻铜层55，以形成子线路结构54。
可以理解的是，对铜层55进行蚀刻，能够蚀刻掉非线路区域而留下线路，接着对线路进行表面处理，以完成封装体40表面的阶梯状的单层线路结构50。
请结合参阅图12、图24和图25，另一种可能的实施方式中，线路结构50包括多个子线路结构54，也即为，线路结构50为多层线路结构50。
具体而言，在单层线路结构50的基础上，也即S231～S234的基础上，多层线路结构50的形成至少包括如下步骤：
S335：在子线路结构54上形成绝缘层57。
S336：在绝缘层57上形成贯穿绝缘层57且与子线路结构54连接的连接结构58。
S337：重复步骤S331～S334以获得两层子线路结构54。或者，多次重复S331～S336以获得多层子线路结构54。
S340：在线路结构50上贴装第二层器件61，其中，第一器件21和第二器件22组成电路板组件100的第一层器件。
需说明的是，第二层器件61的具体的构成和排布形式可参考电路板组件100里的描述，在此不再赘述。
具体而言，请结合参阅图21和图26，在线路结构50上贴装第二层器件61至少包括如下步骤：
S341：在第一焊盘51、第二焊盘52和连接焊盘53上施加锡膏。
S342：在第一焊盘51、第二焊盘52和连接焊盘53上贴装第二层器件61。
S343：进行回流焊接，使第二层器件61与第一焊盘51、第二焊盘52和连接焊盘53连接。
请结合参阅图14-图17、图27，本申请的实施例还提供另一种电路板组件100的制作方法，与前述第一种制作方法相同的内容不再赘述，与第一种制作方法不同的是，电路板组件100的制作方法除S100、S200及S300外，至少还可以包括S400、S500、S600、S700和S800，详细描述如下。
S400：在线路结构50背离封装体40的表面贴装第二层器件61。
其中，第二层器件61的具体构成和排布方式可参阅电路板组件100实施例中的相关描述，在此不再赘述。
S500：在基板10背离封装体40的表面贴装第三层器件62。
其中，第三层器件62的具体构成和排布方式可参阅电路板组件100实施例中的相关描述，在此不再赘述。
S600：提供电路板80。
S700：以电路板80为单面板贴装第四层器件63和架高板90，以使架高板90包围第四层器件63。或者，以电路板80为双面板，在一侧贴装第四层器件63和架高板90，以使架高板90包围第四层器件63，并在另一侧贴装第五层器件64。
其中，第四层器件63、第五层器件64和框架板的具体构成和排布方式可参阅电路板组件100实施例中的相关描述，在此不再赘述。
S800：将电路板80组装至基板10上的架高板90。
可以理解的是，以电路板80作为上层板与架高板90组装，使得基板10与电路板80 能够通过架高板90互连，以得到五层器件堆叠的结构。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (23)

  1. 一种电路板组件(100)，其特征在于，所述电路板组件(100)包括：
    基板(10)；及
    封装体(40)，所述封装体(40)设于所述基板(10)的上表面(101)，所述封装体(40)包括第一封装器件区(41)和第二封装器件区(42)，所述第一封装器件区(41)和所述第二封装器件区(42)具有高度差。
  2. 如权利要求1所述的电路板组件(100)，其特征在于，所述电路板组件(100)还包括第一导体(31)和第二导体(32)，所述第一导体(31)的一端与所述基板(10)连接，另一端与所述第一封装器件区(41)的外表面连接，所述第二导体(32)的一端与所述基板(10)连接，另一端与所述第二封装器件区(42)的外表面连接，所述第一导体(31)与所述第二导体(32)具有高度差。
  3. 如权利要求1或2所述的电路板组件(100)，其特征在于，所述第一封装器件区(41)包覆有第一器件(21)，所述第二封装器件区(42)包覆有第二器件(22)，所述第一器件(21)和所述第二器件(22)均设于所述基板(10)的所述上表面(101)，所述第一器件(21)和所述第二器件(22)具有高度差。
  4. 如权利要求1-3任一项所述的电路板组件(100)，其特征在于，所述电路板组件(100)还包括第一过孔(33)和第二过孔(34)，所述第一导体(31)与所述第一封装器件区(41)的外表面通过所述第一过孔(33)连接，所述第二导体(32)与所述第二封装器件区(42)的外表面通过所述第二过孔(34)连接；
    所述第一过孔(33)内填充有第一电镀金属(35)，所述第一电镀金属(35)连接所述第一导体(31)和所述第一封装器件区(41)的外表面；所述第二过孔(34)内填充有第二电镀金属(36)，所述第二电镀金属(36)连接所述第二导体(32)和所述第二封装器件区(42)的外表面。
  5. 如权利要求4所述的电路板组件(100)，其特征在于，所述第一过孔(33)、所述第一电镀金属(35)和所述第一导体(31)连接构成第一导电结构(37)，所述第二过孔(34)、所述第二电镀金属(36)与所述第二导体(32)连接构成第二导电结构(38)；
    所述第一导电结构(37)的深宽比在5:1～15:1的范围内，或所述第二导电结构(38)的深宽比在5:1～15:1的范围内。
  6. 如权利要求1-5任一项所述的电路板组件(100)，其特征在于，所述电路板组件(100)还包括设于所述封装体(40)的外表面的线路结构(50)，所述线路结构(50)包括第一焊盘(51)和第二焊盘(52)，所述第一焊盘(51)设于所述第一封装器件区(41)的外表面，且与所述第一导体(31)电连接，所述第二焊盘(52)设于所述第二封装器件区(42)的外表面，且与所述第二导体(32)电连接，所述第一焊盘(51)与 所述基板(10)之间的垂直距离与所述第二焊盘(52)与所述基板(10)之间的垂直距离不相同。
  7. 如权利要求6所述的电路板组件(100)，其特征在于，所述电路板组件(100)还包括第三器件(611)和第四器件(612)；
    所述第一器件(21)的高度小于所述第二器件(22)的高度，所述第三器件(611)的高度小于所述第四器件(612)的高度；
    所述第三器件(611)与所述第一焊盘(51)和第二焊盘(52)中的一个进行连接，所述第四器件(612)与所述第一焊盘(51)和第二焊盘(52)中的另一个进行连接。
  8. 如权利要求6或7所述的电路板组件(100)，其特征在于，所述线路结构(50)还包括连接焊盘(53)，所述连接焊盘(53)覆盖所述第一封装器件区(41)与所述第二封装器件区(42)的连接处，所述连接焊盘(53)与所述第一导电结构(37)或所述第二导电结构(38)电连接。
  9. 如权利要求6-8任一项所述的电路板组件(100)，其特征在于，所述线路结构(50)还包括多个子线路结构(54)和设置在相邻两个子线路结构(54)之间的绝缘层(57)，所述绝缘层(57)包括连接结构(58)，相邻两个所述子线路结构(54)通过所述绝缘层(57)的所述连接结构(58)进行电连接。
  10. 如权利要求2-9任一项所述的电路板组件(100)，其特征在于，所述第一导体(31)和所述第二导体(32)之间的高度差值大于或等于0.2mm。
  11. 如权利要求2-10任一项所述的电路板组件(100)，其特征在于，所述第一导体(31)自所述基板(10)向垂直于所述基板(10)的方向延伸，所述第二导体(32)自所述基板(10)向垂直于所述基板(10)的方向延伸。
  12. 如权利要求1-11任一项所述的电路板组件(100)，其特征在于，所述封装体(40)的外表面形成一个或多个台阶结构(404)。
  13. 一种电路板组件(100)的制作方法，其特征在于，所述电路板组件(100)的制作方法包括：
    提供基板(10)；及
    在所述基板(10)的上表面(101)形成封装体(40)，其中，所述封装体(40)包括第一封装器件区(41)和第二封装器件区(42)，所述第一封装器件区(41)和所述第二封装器件区(42)具有高度差。
  14. 如权利要求13所述的方法，其特征在于，在所述提供基板(10)之后，以及在所 述所述基板(10)上形成封装体(40)之前，所述方法还包括：
    在所述基板(10)的上表面(101)贴装第一器件(21)和第二器件(22)，其中，所述第一器件(21)与所述第二器件(22)具有高度差。
  15. 如权利要求14所述的方法，其特征在于，所述方法还包括：
    在所述第一器件(21)所在区域形成第一导体(31)，在所述第二器件(22)所在区域形成第二导体(32)，其中，所述第一导体(31)的一端与所述基板(10)连接，另一端向远离所述基板(10)的方向延伸，所述第二导体(32)的一端与所述基板(10)连接，另一端向远离所述基板(10)的方向延伸，所述第一导体(31)与所述第二导体(32)具有高度差。
  16. 如权利要求15所述的方法，其特征在于，所述第一封装器件区(41)包覆第一器件(21)，且第一封装器件区(41)的外表面与第一导体(31)连接，第二封装器件区(42)包覆第二器件(22)，且第二封装器件区(42)的外表面与第二导体(32)连接。
  17. 如权利要求13-16任一项所述的方法，其特征在于，在所述在所述基板(10)的上表面(101)形成封装体(40)之后，所述方法还包括：
    在所述第一封装器件区(41)的外表面和在所述第二封装器件区(42)的外表面分别形成露出所述第一导体(31)的第一过孔(33)和露出所述第二导体(32)的第二过孔(34)；及
    在所述第一过孔(33)内填充第一电镀金属(35)和在所述第二过孔(34)内填充第二电镀金属(36)，以使所述第一过孔(33)、所述第一电镀金属(35)和所述第一导体(31)连接形成第一导电结构(37)，所述第二过孔(34)、所述第二电镀金属(36)与所述第二导体(32)连接形成第二导电结构(38)。
  18. 如权利要求17所述的方法，其特征在于，在所述在所述第一过孔(33)内填充第一电镀金属(35)和在所述第二过孔(34)内填充第二电镀金属(36)，之后，所述方法还包括：
    在所述封装体(40)的外表面形成与所述第一导电结构(37)和所述第二导电结构(38)电连接的线路结构(50)。
  19. 如权利要求18所述的方法，其特征在于，在所述在所述封装体(40)的外表面形成与所述第一导电结构(37)和所述第二导电结构(38)电连接的线路结构(50)之后，所述方法还包括：
    在所述线路结构(50)上贴装第二层器件61，其中，所述第一器件21和所述第二器件22组成电路板组件(100)的第一层器件。
  20. 如权利要求15-19任一项所述的方法，其特征在于，所述第一导体(31)和所述 第二导体(32)之间的高度差值大于或等于0.2mm。
  21. 如权利要求15-19任一项所述的方法，其特征在于，所述第一导电结构的深宽比在5:1～15:1的范围内，或所述第二导电结构(38)的深宽比在5:1～15:1的范围内。
  22. 一种终端(200)，其特征在于，所述终端(200)包括显示屏、天线模块和如权利要求1-12任一项所述的电路板组件(100)，所述显示屏和所述天线模块均电连接至所述电路板组件(100)。
  23. 一种电子设备(300)，其特征在于，所述电子设备(300)包括壳体(310)和如权利要求1-12任一项所述的电路板组件(100)，所述电路板组件(100)设于所述壳体(310)内。
PCT/CN2022/085583 2021-04-26 2022-04-07 电路板组件及其制作方法、终端及电子设备 WO2022228072A1 (zh)

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JP2005011927A (ja) * 2003-06-18 2005-01-13 Matsushita Electric Ind Co Ltd 複合回路基板
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