Nothing Special   »   [go: up one dir, main page]

WO2021227765A1 - 全反射型显示基板及其制作方法、全反射型显示装置 - Google Patents

全反射型显示基板及其制作方法、全反射型显示装置 Download PDF

Info

Publication number
WO2021227765A1
WO2021227765A1 PCT/CN2021/087469 CN2021087469W WO2021227765A1 WO 2021227765 A1 WO2021227765 A1 WO 2021227765A1 CN 2021087469 W CN2021087469 W CN 2021087469W WO 2021227765 A1 WO2021227765 A1 WO 2021227765A1
Authority
WO
WIPO (PCT)
Prior art keywords
display area
pattern
layer
total reflection
etching protection
Prior art date
Application number
PCT/CN2021/087469
Other languages
English (en)
French (fr)
Inventor
王继国
孙建
刘建涛
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/624,878 priority Critical patent/US20220285406A1/en
Publication of WO2021227765A1 publication Critical patent/WO2021227765A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the embodiments of the present invention relate to the field of display technology, and in particular to a total reflection type display substrate and a manufacturing method thereof, and a total emission type display device.
  • the total reflection type display device relies on the external ambient light to display, does not need a backlight, has the advantages of low power consumption, low cost and can realize multi-color display, so it gradually replaces traditional ink-type electronic paper and is applied to smart retail and electronic label (ESL) , E-books and other fields.
  • ESL electronic retail and electronic label
  • the display substrate of the total reflection display device includes a display area and a non-display area.
  • the non-display area is usually set at the periphery of the display area, the display area is provided with a reflective layer, and the non-display area is provided with binding pins (pin), The pin is connected with the signal line in the display area and bound with the driving circuit (IC) to connect the driving circuit and the signal line.
  • the bonding pins are generally formed of at least one layer of metal film. After the bonding pins are formed, they are exposed. Since the subsequent formation of the reflective layer requires a wet etching process, the bonding pins will be exposed to the etching solution. Etching, which causes bad binding, further affects signal transmission and leads to poor display.
  • the embodiment of the present invention provides a total reflection type display substrate, a manufacturing method thereof, and a total emission type display device, which are used to solve the problem that the bonding pins of the total reflection type display substrate will be etched in the subsequent wet etching process, resulting in bonding Poor, which further affects the signal transmission and leads to the problem of poor display.
  • the present invention is implemented as follows:
  • an embodiment of the present invention provides a total reflection display substrate, including:
  • a base substrate including a display area and a non-display area
  • the signal line is arranged in the display area
  • the binding pin is arranged in the non-display area, connected with the signal line, and used for binding with the driving circuit;
  • the reflective layer is arranged in the display area
  • the etching protection pattern is arranged in the same layer and the same material as the reflective layer, is arranged in the non-display area, and covers at least the side surface of the binding pin.
  • the etching protection pattern completely covers the bonding pins.
  • the reflective layer and the etching protection pattern include at least one metal film layer and at least one transparent metal oxide film layer that are stacked.
  • a first via hole is opened on the etching protection pattern to expose a part of the bonding pin.
  • the first via hole is disposed in a flat area of the etching protection pattern.
  • the binding pin includes: a first metal layer pattern and a second metal layer pattern, and the first metal layer pattern and the second metal layer pattern pass through an interlayer medium disposed therebetween.
  • the second via on the layer is connected, and the orthographic projections of the first via and the second via on the base substrate do not overlap.
  • the reflective layer is multiplexed as a pixel electrode.
  • an embodiment of the present invention provides a total reflection display device, including the display substrate of the first aspect described above.
  • an embodiment of the present invention provides a manufacturing method of a total reflection display substrate, including:
  • the base substrate including a display area and a non-display area
  • first conductive film layer Forming a first conductive film layer on the base substrate, the first conductive film layer covering the display area and the non-display area;
  • a first photoresist pattern and a second photoresist pattern are formed on the first conductive film layer, the first photoresist pattern is disposed in the display area, and the second photoresist pattern is disposed on In the non-display area;
  • the first conductive film layer is wet-etched to obtain a reflective layer and an etching protection pattern, and the reflective layer is disposed on the display In the area, the etching protection pattern is arranged in the non-display area and covers at least the side surface of the binding pin;
  • the method further includes:
  • a first via hole is formed on the etching protection pattern to expose a part of the binding pin.
  • the forming a first via hole on the etching protection pattern includes:
  • the first via hole is formed in the flat area of the etch protection pattern.
  • the etching protection pattern is reserved on at least the side surface of the bonding pin, so as to ensure that the bonding pin is not etched during the process of forming the reflective layer, and at the same time, the scratch resistance of the bonding pin is improved.
  • FIG. 1 is a schematic structural diagram of a total reflection display substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a total reflection display substrate according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a total reflection display substrate according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the structure of a reflective layer according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a total reflection display device according to an embodiment of the present invention.
  • 6A-6F are schematic diagrams of a manufacturing method of a total reflection display substrate according to an embodiment of the present invention.
  • an embodiment of the present invention provides a total reflection type display substrate, including:
  • a base substrate 101 which includes a display area and a non-display area
  • a signal line (not shown in the figure) is arranged in the display area; the signal line may be a gate line (Gate), a data line (Data), or a touch electrode signal line.
  • the binding pin 20 is arranged in the non-display area, is connected to the signal line, and is used for binding with the driving circuit;
  • the reflective layer 1091 is arranged in the display area
  • the etching protection pattern 1092 is set in the same layer and the same material as the reflective layer 1091, is set in the non-display area, and covers at least the side surface of the binding pin 20.
  • the etching protection pattern is reserved on at least the side surface of the bonding pin, so as to ensure that the bonding pin is not etched during the process of forming the reflective layer, and at the same time, the scratch resistance of the bonding pin is improved. Capability, thereby improving the stability of the product (If the surface of the binding pin is scratched during the module processing, it is more likely to have signal and electrical related defects in the subsequent reliability test).
  • the etching protection pattern 1092 completely covers the binding pin 20, thereby further improving the protection performance.
  • the binding pin 20 may be composed of a metal film layer or multiple metal film layers connected to each other.
  • the bonding pin 20 includes: a first metal layer pattern 1052 and a second metal layer pattern 1072, the first metal layer pattern 1052 and the second metal layer pattern 1072 are disposed between the two The second via on the interlayer dielectric layer 106 is connected.
  • the first metal layer pattern 1052 is a gate metal layer pattern, which is set in the same layer and the same material as the gate electrode 1051 in the display area, and is formed by a single patterning process.
  • the second metal layer pattern 1072 is a source-drain metal layer pattern, which is set in the same layer and the same material as the source electrode and the drain electrode 1071 in the display area, and is formed by a patterning process. Further optionally, when the signal line is a gate line, it is set in the same layer and the same material as the first metal layer pattern 1052 and the gate electrode 1051, and when the signal line is a data line, it is the same as the second metal layer pattern. 1072.
  • the source electrode and the drain electrode 1071 are arranged in the same layer and the same material.
  • the second metal layer pattern 1072 may be composed of a metal film layer or a multilayer metal film layer arranged in a stack.
  • the second metal layer pattern 1072 may have a sandwich structure of Ti (titanium), Al (aluminum), and Ti, where Al is easily oxidized, and Ti is not easily oxidized. Therefore, Ti is added on both sides of Al. The oxidation of Al can be prevented.
  • the reflective layer 1091 and the etching protection pattern 1092 include at least one metal film layer and at least one transparent metal oxide film layer arranged in a stack.
  • the transparent metal oxide film layer can prevent the metal film layer from being oxidized.
  • the etching protection pattern includes: a first transparent metal oxide film layer, a metal film layer, and a second transparent metal oxide film layer that are stacked. That is, transparent metal oxide film layers are provided on both sides of the metal film layer, so that the metal film layer can be better prevented from being oxidized.
  • the reflective layer 1091 and the etching protection pattern 1092 can be a sandwich structure of ITO (Indium Tin Oxide), Ag (Silver), and ITO. Ag is easily oxidized. Adding ITO protection on the upper and lower sides of Ag can be effective Prevent the oxidation of Ag.
  • the etching protection pattern 1092 is composed of at least one layer of metal film layer and at least one layer of transparent metal oxide film layer, the resistance of the transparent metal oxide film layer is relatively large, and it is bound to the pins of the driving circuit.
  • the resistance is greater than the bonding resistance between the bonding pin 20 (metal film layer) and the pin of the driving circuit. Therefore, in the embodiment of the present invention, optionally, please refer to FIG. 3, in the etching protection pattern 1092 A first via hole 30 is opened to expose part of the binding pins 20, so that the exposed binding pins 20 are used for binding with the pins of the driving circuit to reduce the binding resistance.
  • the binding pin 20 is composed of a multi-layer metal film layer connected to each other, the multi-layer metal film layer is connected through a second via provided on the interlayer dielectric layer between the metal film layers, and is connected to the first layer of the interlayer dielectric layer. At the position of the second via hole, the bonding pin 20 has a certain degree of depression.
  • the first pass on the etching protection pattern 1092 The hole needs to be provided in the flat area of the etching protection pattern 1092, that is, the first via hole needs to be staggered from the second via hole, and does not overlap with the orthographic projection of the second via hole on the base substrate 101 , Try to ensure that the exposed area of the binding pin 20 is a flat area.
  • the reflective layer is multiplexed as a pixel electrode. Therefore, there is no need to form a reflective layer separately, and the manufacturing cost is reduced. At the same time, the reflective layer with a square pattern can also ensure the reflection area and the reflectivity.
  • the total reflection type display substrate in the embodiment of the present invention includes:
  • a base substrate 101 which includes a display area and a non-display area
  • Buffer layer 102
  • the active layer 103 is disposed in the display area.
  • the active layer 103 may be a low-temperature polysilicon (P-Si) semiconductor layer.
  • Gate insulating layer 104
  • the gate electrode 1051 and the first metal layer pattern 1052, the gate electrode 1051 is arranged in the display area, the first metal layer pattern 1052 is arranged in the non-display area, and the gate electrode 1051 and the first metal layer pattern 1052 are arranged in the same layer and the same material;
  • Interlayer dielectric layer 106 Interlayer dielectric layer 106;
  • the source and drain electrodes 1071, the second metal layer pattern 1072, the source and drain electrodes 1071 are arranged in the display area, the second metal layer pattern 1072 is arranged in the non-display area, the source and drain electrodes 1071, the second metal layer
  • the patterns 1072 are arranged in the same layer and the same material.
  • the second metal layer pattern 1072 is connected to the first metal layer pattern 1052 through the second via hole on the interlayer dielectric layer 106, and the first metal layer pattern 1052 and the second metal layer pattern 1072 are formed together.
  • Binding pin 20; source and drain 1071, the second metal layer pattern 1072 can be a sandwich structure of Ti, Al, Ti;
  • the reflective layer 1091 and the etching protection pattern 1092 are arranged in the display area, the etching protection pattern 1092 is arranged in the non-display area, the reflective layer 1091 and the etching protection pattern 1092 are arranged in the same layer and the same material, and the etching protection pattern 1092 covers bonding pin 20.
  • the reflective layer 1091 and the etching protection pattern 1092 may be a sandwich structure of ITO, Ag, and ITO, and the etching protection pattern 1092 is provided with a first via 30 to expose a part of the binding pin 20 Therefore, the exposed binding pins 20 are used to bind the pins of the driving circuit.
  • An embodiment of the present invention also provides a total reflection type display device, including the total reflection type display substrate in any of the foregoing embodiments.
  • the total reflection type display device in the embodiment of the present invention includes a display substrate 100 and a color filter substrate 200.
  • the display substrate 100 is the above-mentioned display substrate in FIG. 2, and the structure is not described again.
  • the color filter substrate 200 includes: a base substrate 201, a black matrix (BM) 202, a filter layer 203, a planarization layer (OC) 204, a common electrode 205, and a spacer (PS) 206.
  • BM black matrix
  • OC planarization layer
  • PS spacer
  • the display substrate in the embodiment of the present invention is a TN (Twisted Nematic) type display substrate.
  • TN Transmission Nematic
  • it may also be other types of display substrates.
  • an embodiment of the present invention also provides a manufacturing method of a total reflection display substrate, including:
  • Step 61 Please refer to FIG. 6A to provide a base substrate 101, which includes a display area and a non-display area;
  • Step 62 Referring to FIG. 6A, a signal line (not shown in the figure) is formed in the display area, and a bonding pin 20 is formed in the non-display area;
  • the binding pin 20 may be composed of a metal film layer or multiple metal film layers connected to each other.
  • the bonding pin 20 includes: a first metal layer pattern 1052 and a second metal layer pattern 1072, the first metal layer pattern 1052 and the second metal layer pattern 1072 are disposed between the two The second via on the interlayer dielectric layer 106 is connected.
  • the first metal layer pattern 1052 is a gate metal layer pattern, which is set in the same layer and the same material as the gate electrode 1051 in the display area, and is formed by a patterning process.
  • the second metal layer pattern 1072 is a source and drain metal.
  • the layer pattern is set in the same layer and the same material as the source and drain electrodes 1071 in the display area, and is formed by a patterning process. Further optionally, when the signal line is a gate line, it is set in the same layer and the same material as the first metal layer pattern 1052 and the gate electrode 1051, and when the signal line is a data line, it is the same as the second metal layer pattern. 1072.
  • the source electrode and the drain electrode 1071 are arranged in the same layer and the same material.
  • Step 63 Referring to FIG. 6B, a first conductive film layer 109 is formed on the base substrate 101, and the first conductive film layer 109 covers the display area and the non-display area;
  • the first conductive film layer 109 is used to form a reflective layer disposed in the display area.
  • a wet etching process is required.
  • the reflective layer may be a pixel electrode, or other patterns that require a wet etching process during the formation process.
  • Step 64 Referring to FIG. 6C, a first photoresist pattern 41 and a second photoresist pattern 42 are formed on the first conductive film layer 109, and the first photoresist pattern 41 is disposed in the display area , The second photoresist pattern 42 is disposed in the non-display area;
  • Step 65 Please refer to FIG. 6D, using the first photoresist pattern 41 and the second photoresist pattern 42 as masks to perform wet etching on the first conductive film layer 109 to obtain a reflective layer 1091 and etching
  • the protective pattern 1092, the reflective layer 1091 is arranged in the display area
  • the etching protection pattern 1092 is arranged in the non-display area, and at least covers the side surface 20 of the binding pin (in the embodiment of the present invention, Completely cover the bonding pin 20).
  • the photoresist above the binding pin 20 is reserved, when the first conductive film layer 109 is wet-etched, the photoresist above the pin 20 and the first conductive film layer are bound.
  • the binding pins 20 can be protected to prevent the binding pins 20 from being etched by the etching solution.
  • Step 66 Please refer to FIG. 6E to remove the first photoresist pattern 41 and the second photoresist pattern 42.
  • the first conductive film layer used to form the reflective layer in the display area is wet-etched
  • the first conductive film layer on at least the side of the binding pin is reserved as an etching protection pattern, thereby protecting the binding
  • the fixed pins are not etched.
  • the etching protection pattern and the reflective layer are formed through a patterning process, the manufacturing process of the display substrate and the number of masks will not be increased.
  • the second metal layer pattern 1072 may be composed of a metal film layer or a multilayer metal film layer arranged in a stack.
  • the second metal layer pattern 1072 may have a sandwich structure of Ti, Al, and Ti, where Al is easy to be oxidized, and Ti is not easy to be oxidized. Therefore, adding Ti on both sides of Al can prevent the oxidation of Al.
  • the reflective layer 1091 and the etching protection pattern 1092 include at least one metal film layer and at least one transparent metal oxide film layer arranged in a stack.
  • the transparent metal oxide film layer can prevent the metal film layer from being oxidized.
  • the etching protection pattern includes: a first transparent metal oxide film layer, a metal film layer, and a second transparent metal oxide film layer that are stacked. That is, transparent metal oxide film layers are provided on both sides of the metal film layer, so that the metal film layer can be better prevented from being oxidized.
  • the reflective layer 1091 and the etching protection pattern 1092 may be a sandwich structure of ITO, Ag, and ITO. Ag is easily oxidized. Adding ITO protection on the upper and lower sides of Ag can effectively prevent the oxidation of Ag.
  • the second metal layer pattern 1072 is a sandwich structure of Ti, Al, and Ti, and the reflective layer 1091 is a sandwich structure of ITO, Ag, and ITO, if the etching protection pattern 1092 is not provided, in the process of forming the reflective layer 1091, The Al at the edge of the second metal layer pattern 1072 will be etched, the Al will be severely hollowed out, and the top Ti will have a higher risk of peeling.
  • Ti will cause the surface layer Al to be exposed after the Ti falls off ⁇ Al is easily oxidized ⁇ Al oxidation resistance increases ⁇ Bonding resistance increases ⁇ affects data transmission and causes display-related defects.
  • the bonding pin 20 can be prevented from being etched.
  • the etching protection pattern 1092 is composed of at least one layer of metal film layer and at least one layer of transparent metal oxide film layer, the resistance of the transparent metal oxide film layer is relatively large, and it is bound to the pins of the driving circuit. The resistance is greater than the bonding resistance between the bonding pin 20 (metal film layer) and the pin of the driving circuit. Therefore, in the embodiment of the present invention, optionally, please refer to FIG. 6F.
  • the method further includes: forming a first via 30 on the etching protection pattern 1092 to expose a part of the binding pin 20.
  • the binding pin 20 is composed of a multi-layer metal film layer connected to each other, the multi-layer metal film layer is connected through a second via provided on the interlayer dielectric layer between the metal film layers, and is connected to the first layer of the interlayer dielectric layer. At the position of the second via hole, the bonding pin 20 has a certain degree of depression.
  • the first pass on the etching protection pattern 1092 The hole needs to be provided in the flat area of the etching protection pattern 1092, that is, the first via hole needs to be staggered from the second via hole, and does not overlap with the orthographic projection of the second via hole on the base substrate 101 , Try to ensure that the exposed area of the binding pin 20 is a flat area. That is, the forming the first via hole on the etch protection pattern includes: forming the first via hole in the flat area of the etch protection pattern.
  • the reflective layer is multiplexed as a pixel electrode. Therefore, there is no need to form a reflective layer separately, and the manufacturing cost is reduced. At the same time, the reflective layer with a square pattern can also ensure the reflection area and the reflectivity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种全反射型显示基板及其制作方法、全反射型显示装置，全反射型显示基板包括：衬底基板，衬底基板包括显示区域和非显示区域；信号线，设置于显示区域内；绑定引脚，设置于非显示区域内，与信号线连接，且用于与驱动电路绑定；反射层，设置于显示区域内；刻蚀保护图形，与反射层同层同材料设置，设置于非显示区域内，且至少覆盖绑定引脚的侧面。本发明实施例中，在绑定引脚的至少侧面保留刻蚀保护图形，从而确保形成反射层的过程中绑定引脚不被刻蚀，同时，还提高了绑定引脚的抗划伤能力，从而提升了产品的稳定性。

Description

[根据细则37.2由ISA制定的发明名称]　全反射型显示基板及其制作方法、全反射型显示装置
相关申请的交叉引用
本申请主张在2020年05月13日在中国提交的中国专利申请号No.202010402256.0的优先权，其全部内容通过引用包含于此。
技术领域
本发明实施例涉及显示技术领域，尤其涉及一种全反射型显示基板及其制作方法、全发射型显示装置。
背景技术
全反射型显示装置依靠外界环境光显示，无需背光源，具备低功耗、低成本和可实现多色显示等优点，因而逐渐取代传统墨水型电子纸，应用于智能零售、电子标签(ESL)、电子书等领域。
全反射型显示装置的显示基板包括显示区域和非显示区域，非显示区域通常设置于显示区域外围，显示区域内设置有反射层，非显示区域内设置有绑定引脚(pin)，绑定引脚与显示区域内的信号线连接，并与驱动电路(IC)绑定，以连接驱动电路和信号线。
绑定引脚一般由至少一层金属膜层形成，绑定引脚形成之后，则裸露在外，由于在后续的反射层的形成过程中需要进行湿刻工艺，绑定引脚会被刻蚀液刻蚀，从而对绑定造成不良，进一步影响信号传输导致显示不良。
发明内容
本发明实施例提供一种全反射型显示基板及其制作方法、全发射型显示装置，用于解决全反射型显示基板的绑定引脚在后续湿刻工艺中会被刻蚀，造成绑定不良，进一步影响信号传输导致显示不良的问题。
为了解决上述技术问题，本发明是这样实现的：
第一方面，本发明实施例提供了一种全反射型显示基板，包括：
衬底基板，所述衬底基板包括显示区域和非显示区域；
信号线，设置于所述显示区域内；
绑定引脚，设置于所述非显示区域内，与所述信号线连接，且用于与驱动电路绑定；
反射层，设置于所述显示区域内；
刻蚀保护图形，与所述反射层同层同材料设置，设置于所述非显示区域内，且至少覆盖所述绑定引脚的侧面。
可选的，所述刻蚀保护图形完全覆盖所述绑定引脚。
可选的，所述反射层和所述刻蚀保护图形包括层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层。
可选的，所述刻蚀保护图形上开设有第一过孔，以裸露出部分所述绑定引脚。
可选的，所述第一过孔设置于所述刻蚀保护图形的平坦区域。
可选的，所述绑定引脚包括：第一金属层图形和第二金属层图形，所述第一金属层图形和所述第二金属层图形通过设置于两者之间的层间介质层上的第二过孔连接，所述第一过孔和所述第二过孔在所述衬底基板上的正投影不重叠。
可选的，所述反射层复用为像素电极。
第二方面，本发明实施例提供了一种全反射型显示装置，包括上述第一方面的显示基板。
第三方面，本发明实施例提供了一种全反射型显示基板的制作方法，包括：
提供衬底基板，所述衬底基板包括显示区域和非显示区域；
在显示区域内形成信号线，在所述非显示区域内形成绑定引脚，所述绑定引脚与所述信号线连接，且用于与驱动电路绑定；
在所述衬底基板上形成第一导电膜层，所述第一导电膜层覆盖所述显示区域和所述非显示区域；
在所述第一导电膜层上形成第一光刻胶图形和第二光刻胶图形，所述第一光刻胶图形设置于所述显示区域内，所述第二光刻胶图形设置于所述非显示区域内；
以所述第一光刻胶图形和第二光刻胶图形为掩膜，对所述第一导电膜层进行湿刻，得到反射层和刻蚀保护图形，所述反射层设置于所述显示区域内，所述刻蚀保护图形设置于所述非显示区域内，且至少覆盖所述绑定引脚的侧面；
去除所述第一光刻胶图形和第二光刻胶图形。
可选的，所述得到反射层和刻蚀保护图形之后还包括：
在所述刻蚀保护图形上形成第一过孔，以裸露出部分所述绑定引脚。
可选的，所述在所述刻蚀保护图形上形成第一过孔包括：
在所述刻蚀保护图形的平坦区域形成所述第一过孔。
本发明实施例中，在绑定引脚的至少侧面保留刻蚀保护图形，从而确保形成反射层的过程中绑定引脚不被刻蚀，同时，还提高了绑定引脚的抗划伤能力，从而提升了产品的稳定性。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为本发明一实施例的全反射型显示基板的结构示意图；
图2为本发明另一实施例的全反射型显示基板的结构示意图；
图3为本发明又一实施例的全反射型显示基板的结构示意图；
图4为本发明实施例的反射层的结构示意图；
图5为本发明一实施例的全反射型显示装置的结构示意图；
图6A-6F为本发明一实施例的全反射型显示基板的制作方法示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创 造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，本发明实施例提供一种全反射型显示基板，包括：
衬底基板101，所述衬底基板101包括显示区域和非显示区域；
信号线(图未示出)，设置于所述显示区域内；所述信号线可以为栅线(Gate)、数据线(Data)或触控电极信号线等。
绑定引脚20，设置于所述非显示区域内，与所述信号线连接，且用于与驱动电路绑定；
反射层1091，设置于所述显示区域内；
刻蚀保护图形1092，与所述反射层1091同层同材料设置，设置于所述非显示区域内，且至少覆盖所述绑定引脚20的侧面。
本发明实施例中，在绑定引脚的至少侧面保留刻蚀保护图形，从而确保形成反射层的过程中绑定引脚不被刻蚀，同时，还提高了绑定引脚的抗划伤能力，从而提升了产品的稳定性(在模组加工过程中如果绑定引脚表层出现划伤，在后续的信赖性测试过程中更容易出现信号电学相关不良)。
本发明实施例中，可选的，请参考图2，刻蚀保护图形1092完全覆盖所述绑定引脚20，从而进一步提高保护性能。
本发明实施例中，绑定引脚20可以由一层金属膜层或相互连接的多层金属膜层组成。举例来说，所述绑定引脚20包括：第一金属层图形1052和第二金属层图形1072，所述第一金属层图形1052和所述第二金属层图形1072通过设置于两者之间的层间介质层106上的第二过孔连接。可选的，所述第一金属层图形1052为栅金属层图形，与显示区域内的栅极1051同层同材料设置，通过一次构图工艺形成。所述第二金属层图形1072为源漏金属层图形，与显示区域内的源极和漏极1071同层同材料设置，通过一次构图工艺形成。进一步可选的，所述信号线为栅线时，与所述第一金属层图形1052、栅极1051同层同材料设置，所述信号线为数据线时，与所述第二金属层图形1072、源极和漏极1071同层同材料设置。
在本发明的一些实施例中，可选的，所述第二金属层图形1072可以由一层金属膜层或层叠设置的多层金属膜层组成。举例来说，所述第二金属层图形1072可以为Ti(钛)、Al(铝)、Ti夹层结构，其中，Al容易被氧化，Ti 不易被氧化，因而，在Al的两侧增加Ti，可以防止Al的氧化。
本发明实施例中，所述反射层1091和所述刻蚀保护图形1092包括层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层。透明金属氧化物膜层可以防止金属膜层被氧化。进一步可选的，所述刻蚀保护图形包括：层叠设置的第一透明金属氧化物膜层、金属膜层和第二透明金属氧化物膜层。即在金属膜层两侧设置透明金属氧化物膜层，从而可以更好的防止金属膜层被氧化。举例来说，所述反射层1091和所述刻蚀保护图形1092可以是ITO(氧化铟锡)、Ag(银)、ITO夹层结构，Ag容易氧化，在Ag的上下侧增加ITO保护，可以有效防止Ag的氧化。
若所述刻蚀保护图形1092由层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层组成，由于透明金属氧化物膜层电阻较大，与驱动电路的引脚的绑定电阻，会大于绑定引脚20(金属膜层)与驱动电路的引脚的绑定电阻，因而，本发明实施例中，可选的，请参考图3，在所述刻蚀保护图形1092上开设第一过孔30，以裸露出部分所述绑定引脚20，从而采用裸露出的所述绑定引脚20与驱动电路的引脚绑定，降低绑定电阻。
若绑定引脚20由相互连接的多层金属膜层组成，多层金属膜层通过设置在金属膜层之间的层间介质层上的第二过孔连接，在层间介质层的第二过孔位置处，绑定引脚20出出现一定程度的凹陷，为了减少层间介质层的第二过孔位置处凹陷对绑定的影响，所述刻蚀保护图形1092上的第一过孔需要设置于所述刻蚀保护图形1092的平坦区域，即所述第一过孔需要与第二过孔错开，和所述第二过孔在所述衬底基板101上的正投影不重叠，尽量保证绑定引脚20的裸露区域为平坦区域。
本发明实施例中，可选的，请参考图4，所述反射层复用为像素电极。从而无需单独形成反射层，降低制作成本。同时方形图案的反射层，也能够保证反射面积，保证反射率。
下面对全反射性显示基板的一具体结构进行说明。
请参考图3，本发明实施例中的全反射型显示基板包括：
衬底基板101，所述衬底基板101包括显示区域和非显示区域；
缓冲层102；
有源层103，设置于显示区域内，本发明实施例中，可选的，有源层103可以为低温多晶硅(P-Si)半导体层。
栅绝缘层104；
栅极1051和第一金属层图形1052，栅极1051设置于显示区域内，第一金属层图形1052设置于非显示区域内，栅极1051和第一金属层图形1052同层同材料设置；
层间介质层106；
源极和漏极1071、第二金属层图形1072，源极和漏极1071设置于显示区域内，第二金属层图形1072设置于非显示区域内，源极和漏极1071、第二金属层图形1072同层同材料设置，第二金属层图形1072通过层间介质层106上的第二过孔与第一金属层图形1052连接，第一金属层图形1052和第二金属层图形1072共同组成绑定引脚20；源极和漏极1071、第二金属层图形1072可以为Ti、Al、Ti夹层结构；
钝化层108；
反射层1091和刻蚀保护图形1092，反射层1091设置于显示区域内，刻蚀保护图形1092设置于非显示区域内，反射层1091和刻蚀保护图形1092同层同材料设置，刻蚀保护图形1092覆盖绑定引脚20。所述反射层1091和所述刻蚀保护图形1092可以是ITO、Ag、ITO夹层结构，所述刻蚀保护图形1092上开设有第一过孔30，以裸露出部分所述绑定引脚20，从而采用裸露出的所述绑定引脚20与驱动电路的引脚绑定。
本发明实施例还提供一种全反射型显示装置，包括上述任一实施例中的全反射型显示基板。
请参考图5，本发明实施例中的全反射型显示装置除了包括显示基板100和彩膜基板200，显示基板100为上述图2中的显示基板，结构不再重复描述。
彩膜基板200包括：衬底基板201、黑矩阵(BM)202、滤光层203、平坦层(OC)204、公共电极205和隔垫物(PS)206。
本发明实施例中的显示基板为TN(Twisted Nematic，扭转向列)型显示基板，当然，在本发明的其他一些实施例中，也可以为其他类型的显示基板。
请参考图6A-图6E，本发明实施例还提供一种全反射型显示基板的制作方法，包括：
步骤61：请参考图6A，提供衬底基板101，所述衬底基板101包括显示区域和非显示区域；
步骤62：请参考图6A，在显示区域内形成信号线(图未示出)，在所述非显示区域形成绑定引脚20；
本发明实施例中，绑定引脚20可以由一层金属膜层或相互连接的多层金属膜层组成。举例来说，所述绑定引脚20包括：第一金属层图形1052和第二金属层图形1072，所述第一金属层图形1052和所述第二金属层图形1072通过设置于两者之间的层间介质层106上的第二过孔连接。可选的，所述第一金属层图形1052为栅金属层图形，与显示区域内的栅极1051同层同材料设置，通过一次构图工艺形成，所述第二金属层图形1072为源漏金属层图形，与显示区域内的源极和漏极1071同层同材料设置，通过一次构图工艺形成。进一步可选的，所述信号线为栅线时，与所述第一金属层图形1052、栅极1051同层同材料设置，所述信号线为数据线时，与所述第二金属层图形1072、源极和漏极1071同层同材料设置。
步骤63：请参考图6B，在所述衬底基板101上形成第一导电膜层109，所述第一导电膜层109覆盖所述显示区域和所述非显示区域；
本发明实施例中，所述第一导电膜层109用于形成设置于显示区域内的反射层，在形成所述反射层的过程中，需要用到湿刻工艺。
所述反射层可以是像素电极，或者其他在形成过程中需要用到湿刻工艺的图形。
步骤64：请参考图6C，在所述第一导电膜层109上形成第一光刻胶图形41和第二光刻胶图形42，所述第一光刻胶图形41设置于所述显示区域，所述第二光刻胶图形42设置于所述非显示区域；
步骤65：请参考图6D，以所述第一光刻胶图形41和第二光刻胶图形42为掩膜，对所述第一导电膜层109进行湿刻，得到反射层1091和刻蚀保护图形1092，所述反射层1091设置于所述显示区域，所述刻蚀保护图形1092设置于所述非显示区域，且至少覆盖所述绑定引脚的侧面20(本发明实施例中， 完全覆盖绑定引脚20)。
本发明实施例中，由于保留了绑定引脚20上方的光刻胶，因而在对第一导电膜层109进行湿刻时，绑定引脚20上方的光刻胶以及第一导电膜层均可以对绑定引脚20进行保护，避免绑定引脚20被刻蚀液刻蚀。
步骤66：请参考图6E，去除所述第一光刻胶图形41和第二光刻胶图形42。
本发明实施例中，在对用于形成显示区域内的反射层的第一导电膜层进行湿刻时，保留绑定引脚至少侧面的第一导电膜层作为刻蚀保护图形，从而保护绑定引脚不被刻蚀。同时，由于刻蚀保护图形与反射层沟通一次构图工艺形成，从而不会增加显示基板的制作工序和掩膜板的数量。
在本发明的一些实施例中，可选的，所述第二金属层图形1072可以由一层金属膜层或层叠设置的多层金属膜层组成。举例来说，所述第二金属层图形1072可以为Ti、Al、Ti夹层结构，其中，Al容易被氧化，Ti不易被氧化，因而，在Al的两侧增加Ti，可以防止Al的氧化。
本发明实施例中，所述反射层1091和所述刻蚀保护图形1092包括层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层。透明金属氧化物膜层可以防止金属膜层被氧化。进一步可选的，所述刻蚀保护图形包括：层叠设置的第一透明金属氧化物膜层、金属膜层和第二透明金属氧化物膜层。即在金属膜层两侧设置透明金属氧化物膜层，从而可以更好的防止金属膜层被氧化。举例来说，所述反射层1091和所述刻蚀保护图形1092可以是ITO、Ag、ITO夹层结构，Ag容易氧化，在Ag的上下侧增加ITO保护，可以有效防止Ag的氧化。
若所述第二金属层图形1072为Ti、Al、Ti夹层结构，所述反射层1091是ITO、Ag、ITO夹层结构，若不设置刻蚀保护图形1092，在形成反射层1091的过程中，第二金属层图形1072边缘位置的Al会被刻蚀，Al镂空严重，顶部(Top)Ti剥落(Peeling)风险较大。造成的影响如下：Ti脱落之后会造成表层Al裸露→Al很容易被氧化→Al氧化电阻增加→绑定(Bonding)电阻增加→影响数据传输引起显示相关不良。
本发明实施例中，由于在绑定引脚20的至少侧面覆盖刻蚀保护图形1092， 因而，可以避免绑定引脚20被刻蚀。
若所述刻蚀保护图形1092由层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层组成，由于透明金属氧化物膜层电阻较大，与驱动电路的引脚的绑定电阻，会大于绑定引脚20(金属膜层)与驱动电路的引脚的绑定电阻，因而，本发明实施例中，可选的，请参考图6F，所述得到反射层和刻蚀保护图形之后还包括：在所述刻蚀保护图形1092上形成第一过孔30，以裸露出部分所述绑定引脚20。
若绑定引脚20由相互连接的多层金属膜层组成，多层金属膜层通过设置在金属膜层之间的层间介质层上的第二过孔连接，在层间介质层的第二过孔位置处，绑定引脚20出出现一定程度的凹陷，为了减少层间介质层的第二过孔位置处凹陷对绑定的影响，所述刻蚀保护图形1092上的第一过孔需要设置于所述刻蚀保护图形1092的平坦区域，即所述第一过孔需要与第二过孔错开，和所述第二过孔在所述衬底基板101上的正投影不重叠，尽量保证绑定引脚20的裸露区域为平坦区域。即，所述在所述刻蚀保护图形上形成第一过孔包括：在所述刻蚀保护图形的平坦区域形成所述第一过孔。
本发明实施例中，可选的，所述反射层复用为像素电极。从而无需单独形成反射层，降低制作成本。同时方形图案的反射层，也能够保证反射面积，保证反射率。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本发明的保护之内。

Claims (11)

  1. 一种全反射型显示基板，其特征在于，包括：
    衬底基板，所述衬底基板包括显示区域和非显示区域；
    信号线，设置于所述显示区域内；
    绑定引脚，设置于所述非显示区域内，与所述信号线连接，且用于与驱动电路绑定；
    反射层，设置于所述显示区域内；
    刻蚀保护图形，与所述反射层同层同材料设置，设置于所述非显示区域内，且至少覆盖所述绑定引脚的侧面。
  2. 如权利要求1所述的全反射型显示基板，其特征在于，所述刻蚀保护图形完全覆盖所述绑定引脚。
  3. 如权利要求1所述的全反射型显示基板，其特征在于，所述反射层和所述刻蚀保护图形包括层叠设置的至少一层金属膜层和至少一层透明金属氧化物膜层。
  4. 如权利要求1或3所述的全反射型显示基板，其特征在于，所述刻蚀保护图形上开设有第一过孔，以裸露出部分所述绑定引脚。
  5. 如权利要求4所述的全反射型显示基板，其特征在于，所述第一过孔设置于所述刻蚀保护图形的平坦区域。
  6. 如权利要求5所述的全反射型显示基板，其特征在于，所述绑定引脚包括：第一金属层图形和第二金属层图形，所述第一金属层图形和所述第二金属层图形通过设置于两者之间的层间介质层上的第二过孔连接，所述第一过孔和所述第二过孔在所述衬底基板上的正投影不重叠。
  7. 如权利要求1所述的全反射型显示基板，其特征在于，所述反射层复用为像素电极。
  8. 一种全反射型显示装置，其特征在于，包括如权利要求1-7任一项所述的全反射型显示基板。
  9. 一种全反射型显示基板的制作方法，其特征在于，包括：
    提供衬底基板，所述衬底基板包括显示区域和非显示区域；
    在显示区域内形成信号线，在所述非显示区域内形成绑定引脚，所述绑定引脚与所述信号线连接，且用于与驱动电路绑定；
    在所述衬底基板上形成第一导电膜层，所述第一导电膜层覆盖所述显示区域和所述非显示区域；
    在所述第一导电膜层上形成第一光刻胶图形和第二光刻胶图形，所述第一光刻胶图形设置于所述显示区域内，所述第二光刻胶图形设置于所述非显示区域内；
    以所述第一光刻胶图形和第二光刻胶图形为掩膜，对所述第一导电膜层进行湿刻，得到反射层和刻蚀保护图形，所述反射层设置于所述显示区域内，所述刻蚀保护图形设置于所述非显示区域内，且至少覆盖所述绑定引脚的侧面；
    去除所述第一光刻胶图形和第二光刻胶图形。
  10. 如权利要求9所述的全反射型显示基板的制作方法，其特征在于，所述得到反射层和刻蚀保护图形之后还包括：
    在所述刻蚀保护图形上形成第一过孔，以裸露出部分所述绑定引脚。
  11. 如权利要求10所述的全反射型显示基板的制作方法，其特征在于，所述在所述刻蚀保护图形上形成第一过孔包括：
    在所述刻蚀保护图形的平坦区域形成所述第一过孔。
PCT/CN2021/087469 2020-05-13 2021-04-15 全反射型显示基板及其制作方法、全反射型显示装置 WO2021227765A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/624,878 US20220285406A1 (en) 2020-05-13 2021-04-15 Full-reflection display substrate, manufacturing method thereof and full-reflection display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010402256.0 2020-05-13
CN202010402256.0A CN111554696B (zh) 2020-05-13 2020-05-13 全反射型显示基板及其制作方法、全发射型显示装置

Publications (1)

Publication Number Publication Date
WO2021227765A1 true WO2021227765A1 (zh) 2021-11-18

Family

ID=72006303

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/087469 WO2021227765A1 (zh) 2020-05-13 2021-04-15 全反射型显示基板及其制作方法、全反射型显示装置

Country Status (3)

Country Link
US (1) US20220285406A1 (zh)
CN (1) CN111554696B (zh)
WO (1) WO2021227765A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114080671A (zh) * 2020-04-30 2022-02-22 京东方科技集团股份有限公司 镜面显示面板及其制作方法、显示装置
CN111554696B (zh) * 2020-05-13 2024-03-29 京东方科技集团股份有限公司 全反射型显示基板及其制作方法、全发射型显示装置
CN112397526B (zh) * 2020-11-03 2023-12-01 Tcl华星光电技术有限公司 一种阵列基板及其制备方法与显示面板
CN112366220B (zh) * 2020-11-10 2024-02-27 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127303A (ja) * 1996-12-18 2001-05-11 Nec Corp 薄膜トランジスタアレイ基板およびその製造方法
CN101676781A (zh) * 2008-09-18 2010-03-24 统宝光电股份有限公司 影像显示系统及其制造方法
CN102403311A (zh) * 2010-09-16 2012-04-04 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
US20160322399A1 (en) * 2015-04-30 2016-11-03 Samsung Display Co., Ltd. Display device and manufacturing method thereof
CN106941093A (zh) * 2017-05-12 2017-07-11 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN110931540A (zh) * 2019-12-20 2020-03-27 京东方科技集团股份有限公司 镜面显示面板及其制作方法、镜面显示装置
CN111554696A (zh) * 2020-05-13 2020-08-18 京东方科技集团股份有限公司 全反射型显示基板及其制作方法、全发射型显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713310B2 (en) * 2002-03-08 2004-03-30 Samsung Electronics Co., Ltd. Ferroelectric memory device using via etch-stop layer and method for manufacturing the same
KR101283182B1 (ko) * 2006-01-26 2013-07-05 엘지이노텍 주식회사 발광 다이오드 패키지 및 그 제조 방법
US10297772B2 (en) * 2016-09-22 2019-05-21 Samsung Display Co., Ltd. Display device and manufacturing method thereof
KR20210014233A (ko) * 2019-07-29 2021-02-09 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
KR20210035358A (ko) * 2019-09-23 2021-04-01 삼성디스플레이 주식회사 표시 장치
KR20210101353A (ko) * 2020-02-07 2021-08-19 삼성디스플레이 주식회사 도전 패턴의 제조 방법, 표시 장치 및 이의 제조 방법
CN113611725A (zh) * 2020-05-04 2021-11-05 三星显示有限公司 显示装置及其制造方法
KR20220036437A (ko) * 2020-09-15 2022-03-23 삼성디스플레이 주식회사 표시 장치
KR20220065949A (ko) * 2020-11-13 2022-05-23 삼성디스플레이 주식회사 표시 장치
KR20220080801A (ko) * 2020-12-07 2022-06-15 삼성디스플레이 주식회사 디스플레이 장치 및 그 제조 방법
KR20230085262A (ko) * 2021-12-06 2023-06-14 삼성디스플레이 주식회사 발광 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127303A (ja) * 1996-12-18 2001-05-11 Nec Corp 薄膜トランジスタアレイ基板およびその製造方法
CN101676781A (zh) * 2008-09-18 2010-03-24 统宝光电股份有限公司 影像显示系统及其制造方法
CN102403311A (zh) * 2010-09-16 2012-04-04 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
US20160322399A1 (en) * 2015-04-30 2016-11-03 Samsung Display Co., Ltd. Display device and manufacturing method thereof
CN106941093A (zh) * 2017-05-12 2017-07-11 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN110931540A (zh) * 2019-12-20 2020-03-27 京东方科技集团股份有限公司 镜面显示面板及其制作方法、镜面显示装置
CN111554696A (zh) * 2020-05-13 2020-08-18 京东方科技集团股份有限公司 全反射型显示基板及其制作方法、全发射型显示装置

Also Published As

Publication number Publication date
CN111554696B (zh) 2024-03-29
CN111554696A (zh) 2020-08-18
US20220285406A1 (en) 2022-09-08

Similar Documents

Publication Publication Date Title
WO2021227765A1 (zh) 全反射型显示基板及其制作方法、全反射型显示装置
US11923397B2 (en) Micro light emitting diode display substrate and manufacturing method thereof
WO2011013434A1 (ja) 配線基板およびその製造方法、表示パネル、並びに表示装置
KR100660531B1 (ko) 반사투과 복합형 박막트랜지스터 액정표시장치
KR101320787B1 (ko) 기판 및 그 제조방법, 표시장치
CN111489647B (zh) 显示模组及其制造方法、显示装置
WO2021068805A1 (zh) 显示面板及其制造方法、显示装置
US20240063239A1 (en) Fingerprint sensor, method for manufacturing fingerprint sensor, and display device including fingerprint sensor
US20120146971A1 (en) Display device and method of manufacturing the same
US11793037B2 (en) Display panel and display device
US11428996B2 (en) Display device
JP2008090147A (ja) 接続端子基板及びこれを用いた電子装置
US20220317508A1 (en) Display substrate and method for manufacturing the same, display device
JP4040048B2 (ja) 液晶表示装置及びその製造方法
US11985863B2 (en) Display device and method of manufacturing the same
JP2004061687A (ja) 液晶表示装置用基板及びその製造方法及びそれを備えた液晶表示装置
KR100764050B1 (ko) 반사투과 복합형 액정표시장치 및 그 형성방법
US7142275B2 (en) Electro-optic device having multi-layer conductive layer, method of manufacturing the same, and electronic apparatus
US20040119918A1 (en) Electro-optic device, manufacturing method thereof, and electronic apparatus
US20220131113A1 (en) Display device and method of manufacturing the display device
WO2023142014A1 (zh) 触控显示面板、触控显示装置、触控显示母板
WO2018205659A1 (zh) 显示面板
US12147637B2 (en) Touch display panel, touch display apparatus and touch display mother board
CN112909018B (zh) 元件阵列基板及其制作方法
KR101252480B1 (ko) 액정표시소자 및 그 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21804208

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21804208

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26-06-2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21804208

Country of ref document: EP

Kind code of ref document: A1