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WO2020000183A1 - 半导体的晶圆级封装方法和半导体封装件 - Google Patents

半导体的晶圆级封装方法和半导体封装件 Download PDF

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Publication number
WO2020000183A1
WO2020000183A1 PCT/CN2018/092885 CN2018092885W WO2020000183A1 WO 2020000183 A1 WO2020000183 A1 WO 2020000183A1 CN 2018092885 W CN2018092885 W CN 2018092885W WO 2020000183 A1 WO2020000183 A1 WO 2020000183A1
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Prior art keywords
wafer
memory chip
chip units
logic
pad
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Application number
PCT/CN2018/092885
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English (en)
French (fr)
Inventor
赵立新
Original Assignee
格科微电子（上海）有限公司
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Priority to US17/255,015 priority Critical patent/US20240258269A1/en
Priority to PCT/CN2018/092885 priority patent/WO2020000183A1/zh
Publication of WO2020000183A1 publication Critical patent/WO2020000183A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Definitions

  • the invention relates to the field of semiconductor manufacturing, and in particular, to a wafer-level packaging method for a semiconductor and a semiconductor package.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • FLASH flash memory
  • Phase change memory Phase change Memory, PCM
  • a logic chip usually refers to a chip with a programmable logic device (PLD).
  • PLD programmable logic device
  • the two bare chips are individually packaged. After completion, they are soldered to the circuit board and connected by circuit board traces.
  • the two bare chips are connected to the substrate by wiring, and then packaged as a whole.
  • Micro pads are grown on the two bare wafers (that is, the wafer including the logic chip unit and the wafer including the memory chip unit), and the two are directly connected through the micro pads, and then packaged as a whole.
  • the package performance becomes better, the power consumption is reduced, the volume is reduced, and the cost is reduced.
  • the first two packaging methods generally there are dual in-line packaging, flat packaging, ball grid packaging, etc. These packaging methods need to cut the wafer into dies and then package them individually. Among them, the wafer-level package is processed on the entire wafer as a whole, the solder balls are grown, and then the packaged chips are obtained after dicing. Compared with general packaging, wafer-level packaging has the advantages of lower cost, better consistency, and smaller package size.
  • the third packaging method it is wafer-to-wafer packaging. Specifically, two wafers of the same size are directly bonded, and each chip on the two wafers is the same size.
  • the pin arrangement corresponds to the bonding. After completion, the connection between all the chips on the two wafers is completed, and then the whole package is made, and the external pads are led out, and the separated single chipset is obtained after cutting.
  • Wafer-to-wafer packaging completes the connection of all chips on two wafers at the same time. There is no need to connect the two chips one by one like the previous two methods, so the cost is lower, and because all chips are bonded and packaged at the same time, Therefore, it is better to get the consistency of the product than to package them one by one. However, the application range of wafer-to-wafer packaging is still very narrow.
  • the problem solved by the present invention is to provide a semiconductor wafer-level packaging method and a semiconductor package, so as to expand the application range of wafer to wafer packaging, improve the flexibility of semiconductor packaging, simplify the packaging method, and reduce chips of different areas. Area wasted during packaging.
  • the present invention provides a wafer-level packaging method for a semiconductor, including:
  • a second wafer having one or more logic chip units is provided, and the area of each of the logic chip units corresponds to the area of N memory chip units, where N is a natural number greater than or equal to 1 and adjacent to the logic There is a second scribe line between the chip units, and the second scribe line matches the first scribe lines on the periphery of the N memory chip units;
  • the first wafer and the second wafer are bonded, so that the logic chip unit and the N memory chip units are correspondingly matched.
  • the step of bonding the first wafer and the second wafer includes:
  • the first butt pad and the second butt pad are electrically bonded.
  • the step of bonding the first wafer and the second wafer includes:
  • the first wafer is physically connected to the second wafer;
  • the logic chip unit and the memory chip unit are electrically coupled through a TSV process.
  • the first butt pad is electrically connected to a pad of a first multilayer metal layer inside the first wafer, and the pad of the first multilayer metal layer is electrically connected to the first Internal wafer bus;
  • the second butt pad is electrically connected to the pad of the second multilayer metal layer inside the second wafer, and the pad of the second multilayer metal layer is electrically connected to the first Two wafer internal bus.
  • the memory chip unit includes at least one of SRAM, DRAM, FLASH, PCM, DDR, DDR2, DDR3, and DDR4.
  • the peripheral circuit includes at least one of a control logic circuit, an interface conversion logic circuit, and a code correction logic circuit.
  • providing the first wafer further includes:
  • a test circuit module is formed in the first cutting track region.
  • providing the second wafer further includes:
  • a test circuit module is formed in the second cutting track area.
  • the method further includes: grinding and thinning the first wafer and the second wafer.
  • the present invention also provides a semiconductor package, including:
  • a first wafer having one or more memory chip units and a first scribe line between adjacent memory chip units
  • the second wafer has one or more logic chip units, and there is a second scribe line between adjacent logic chip units, and the area of the logic chip units corresponds to the area of N memory chip units, where N A natural number greater than or equal to 1;
  • the first wafer and the second wafer are bonded to each other, the logic chip unit corresponds to N memory chip units, and the second scribe line matches the first scribe line on the periphery of the N memory chip units. .
  • a logic chip unit is designed to match N memory chip units, where N is a natural number greater than or equal to 1, thereby ensuring that two wafers can be directly bonded and packaged, especially when N is greater than At 1, it is possible to make full use of the area correspondence between the two chip units for matching, thereby reducing area waste and increasing the scope of memory wafer packaging.
  • test circuit module is formed on the scribe line of the wafer.
  • the test circuit module is formed in a first scribe line of the first wafer, and the test circuit module may be connected to the first butt pad to test the memory chip unit, thereby improving the final package yield.
  • FIG. 1 is a schematic diagram of a first wafer according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a memory chip in the first wafer shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a second wafer according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the first wafer shown in FIG. 1 and the second wafer shown in FIG. 3 facing each other before bonding;
  • FIG. 5 is a schematic diagram of a bonding arrangement of a first wafer and a second wafer according to another embodiment of the present invention.
  • the present invention provides a new wafer-level packaging method for semiconductors, which improves the application range of wafer-to-wafer packaging by matching a logic chip unit with more than one memory chip unit, and Reduce waste of chip area.
  • An embodiment of the present invention provides a semiconductor wafer-level packaging method. Please refer to FIGS. 1 to 4 in combination.
  • FIG. 1 shows four memory chip units 110 of a first wafer 100 arranged in a 2 ⁇ 2 matrix as a representative.
  • Each memory chip unit 110 has a memory array circuit (refer to FIG. 2) and a peripheral circuit (not shown), and adjacent memory chip units 110 have a first cutting track 101.
  • the memory chip unit 110 may be at least one of SRAM, DRAM, FLASH, PCM, DDR, DDR2, DDR3, and DDR4. In this embodiment, the memory chip unit 110 is specifically described using a DRAM as an example.
  • the memory chip unit 110 may include a memory array 10, a control logic circuit 20, an interface conversion logic circuit 30, an original bus 40 (including an address bus and a data bus), and an ultra-wide bus 40 '(including an ultra-wide address bus). And ultra-wide data bus).
  • the memory array 10 includes: eight banks (bank0 to bank7), each bank includes a plurality of memory cells, and the memory array 10 is used to store data.
  • control logic circuit 20 includes: a row address latch, a memory array control (circuit), a column address latch, a bit selection logic (circuit), etc.
  • the control logic circuit 20 is used to control a memory array 10 to implement read and write operations on specific storage units in each bank.
  • the interface conversion logic circuit 30 is configured to transmit data read from the bank after serial-to-parallel conversion, and then transmit the data from a specific interface.
  • the data bus width through the interface conversion logic circuit 30 will be greatly limited.
  • the original bus 40 includes an original address bus and an original data bus.
  • the width of the original address bus is generally about 15 bits; the width of the original data bus is generally 4, 8, 16 bits.
  • the width of the original data bus before the serial-parallel conversion of the interface logic conversion circuit is 16 bits, and the width of the original data bus after the serial-parallel conversion of the interface logic conversion circuit is reduced to 4 bits.
  • the original data bus after serial-to-parallel conversion will eventually be connected to the signal pad (not shown) to meet the needs of traditional DRAM packages.
  • the ultra-wide bus 40 ′ includes an ultra-wide address bus and an ultra-wide data bus.
  • the width of the ultra-wide bus 40 ' is significantly wider than that of the original bus 40.
  • the ultra-wide address bus can be divided into multiple channels (for example, 2, 4, 8 and so on, only one channel is illustrated in this embodiment), and each channel has a width of about 32 bits.
  • the ultra-wide data bus can also be divided into multiple channels, and the width of each channel can be 64, 128, or 256 bits, or even wider. In this embodiment, the width of the ultra-wide data bus is 128 bits.
  • the ultra-wide data bus does not pass through the interface conversion logic circuit 30, but is directly connected with a micro pad (not shown) together with the ultra-wide address bus to implement a DRAM of the ultra-wide bus.
  • the internal bus of the memory chip unit 110 can be connected to multiple sets of storage arrays.
  • the storage array may include multiple banks for storing data.
  • the internal bus is a wide data bus and control bus connected to the storage array, and the data width may be greater than or equal to 64 bits.
  • the internal bus is connected to at least a group of storage arrays.
  • a first top metal layer may be formed on the memory chip unit 110 of the DRAM, and a power pad (not shown) is formed on the first top metal layer.
  • Signal pad (not shown) and micro pad (not shown), the internal bus of the memory chip unit 110 is electrically connected to the micro pad.
  • the first wafer 100 provided in this embodiment further includes a first docking pad 111 formed on an upper surface of the first wafer 100, as shown in FIG. 1.
  • the first docking pad 111 is electrically connected to the pad (including the power pad and the signal pad) of the first multilayer metal layer inside the first wafer 100, and the pad of the first multilayer metal layer is electrically The internal bus of the first wafer 100 is connected. Therefore, the first docking pad 111 is electrically connected to the internal bus of the first wafer 100.
  • the first docking pad 111 formed in this embodiment leads a wider internal bus to the surface of the DRAM.
  • Each first docking pad 111 is connected to at least one of the internal buses.
  • the first docking pad 111 can also be connected to multiple internal buses.
  • one or a first multilayer metal layer may be formed on the memory chip unit 110, and then a first docking pad 111 is formed in the top metal layer, as shown in FIG.
  • a wide internal bus is drawn from the memory array of the memory chip unit 110 and is electrically connected to the first docking pad 111.
  • the power pad and the signal pad in the existing DRAM package are still used.
  • the power pad is used to supply power to the DRAM
  • the signal pad is used to implement DRAM reading through a conventional interface control logic circuit.
  • the peripheral circuit may include at least one of a control logic circuit, an interface conversion logic circuit, and a code correction logic circuit.
  • the control logic circuit includes: a row address latch, a memory array control circuit, a column address latch, a bit selection logic circuit, and the like, which are used to control the memory array and implement read and write operations to specific memory cells in the bank.
  • the interface conversion logic circuit is configured to transmit data read from the bank through serial-to-parallel conversion and transmit it from a specific interface. The data bus width through the interface conversion logic circuit will be greatly limited.
  • a memory cell of one or more banks of a standard DRAM plus a peripheral circuit may be used as the memory chip unit 110, or one or more blocks of a standard FLASH may be used.
  • the upper peripheral circuit becomes a memory chip unit 110.
  • the first wafer 100 provided in this embodiment may further include: forming a test circuit module in a region of the first scribe line 101.
  • the test circuit module is formed in the first scribe line 101 of the first wafer 100, and the test circuit module may be connected to the first docking pad 111 so as to test the memory chip unit 110.
  • FIG. 3 shows one of the logic chip units 210 of the second wafer 200 as a representative.
  • each logic chip unit 210 corresponds to the area of four memory chip units 110.
  • the second scribe line 201 there is a second scribe line 201 between adjacent logic chip units 210, and the second scribe line 201 matches the first scribe line 101 on the periphery of the four memory chip units (refer to the corresponding content in FIG. 4 later).
  • the area of each logic chip unit 210 corresponding to the area of the four memory chip units 110 means that the area of each logic chip unit 210 is substantially equal to the area of the four memory chip units 110, and that the four memories
  • the area shape of the chip unit 110 is the same as the area shape of each logic chip unit 210.
  • the first docking pad 111 on the four memory chip units 110 and the second docking pad 211 on the logic chip unit 210 are opposite to each other. It is ensured that the first docking pad 111 of the subsequent one logic chip unit 210 and the second docking pad 211 of the four memory chip units 110 can be electrically connected to each other to form a bonding structure.
  • the existing wafer-to-wafer packaging is still very narrow in application.
  • the wafer-to-wafer packaging requires the same chip size on the two wafers that are docked, while the logic wafer and storage wafer are generally composed of Produced by different manufacturers, the size is generally different. If you want to make the two the same size, fill small chips to increase the chip area, which will cause waste.
  • the size of logic wafers of different designs is very different.
  • a storage wafer cannot adapt to logic wafers of different sizes. Generally, it can only be used for one type of logic wafer.
  • one logic chip unit can correspond to one or more memory chip units, which expands the application range of wafer-to-wafer packaging, reduces area waste, and improves packaging application of memory wafers. range.
  • each logic chip unit 210 may also correspond to the area of one, two, three, or more than five memory chip units 110. The present invention does not address this. limited. That is, the area of each logic chip unit 210 may correspond to the area of N memory chip units 110, where N is a natural number greater than or equal to one.
  • the upper surface of the provided second wafer 200 further includes a second docking pad 211 on the surface of the logic chip unit 210.
  • the second docking pad 211 is electrically connected to the pad of the second multilayer metal layer inside the second wafer 200, and the pad of the second multilayer metal layer is electrically connected to the internal bus of the second wafer 200.
  • the process of forming the second docking pad 211 is similar to the process of forming the first docking pad 111, and reference may be made to the foregoing corresponding content.
  • the positions of the second docking pad 211 and the first docking pad 111 correspond to each other, thereby ensuring that the subsequent logic chip unit 210 can be matched with the memory chip unit 110 correspondingly.
  • the first wafer 100 provided in this embodiment further includes: forming a test circuit module in a region of the second scribe line 201.
  • the test circuit module is formed in the second scribe line 201 of the second wafer 200, and the test circuit module may be connected to the second docking pad 211 so as to test the logic chip unit 210, thereby improving the final packaging quality. rate.
  • first wafer 100 and second wafer 200 may be repaired.
  • the method for repairing a wafer is not specifically limited in the present invention, and there are various methods for repairing a wafer in the prior art, such as laser trimming, etc., which can be applied to the present invention. Through the repair, the yield of the first wafer 100 can be further improved.
  • the first wafer 100 and the second wafer 200 are bonded, so that the logic chip unit 210 and the four memory chip units 110 are correspondingly matched.
  • FIG. 4 shows the moment before the first wafer 100 and the second wafer 200 are bonded (that is, the two wafers face each other).
  • the first scribe lane 101 of the combined periphery of the four memory chip units 110 corresponds to the second scribe lane 201 of the one logic chip unit 210 (you can intuitively judge according to the four dotted lines that are not marked in FIG. 4) Therefore, it is ensured that one logic chip unit 210 and four memory chip units 110 are correspondingly matched.
  • the first butt pads 111 of the four memory chip units 110 correspond to the second butt pads 211 of the one logic chip unit 210. Therefore, the first wafer 100 and the second When the wafer 200 is used, the first docking pad 111 and the second docking pad 211 are electrically bonded.
  • the thickness of the logic circuit and metal wiring part of the wafer is about 100 ⁇ m, but the overall thickness of the wafer is about 1000 ⁇ m to provide better support.
  • the logic circuit part and the routing part are in the middle of the two wafers. At this time, the wafer is too thick to prevent heat dissipation. Reducing the thickness of the wafer can improve the heat dissipation effect, so that the thickness of the final component Smaller, improved heat dissipation performance.
  • subsequent wafer cutting may be performed to form a single chip combination (each chip combination includes 1 logical chip unit 210 and 4 Memory chip units 110, and electrically bonded between them), and plastically package each chip combination.
  • Another embodiment of the present invention provides another wafer-level packaging method for semiconductors, please refer to FIG. 5.
  • a first wafer 300 having one or more memory chip units (not shown) is provided.
  • Each memory chip unit has a memory array circuit and a peripheral circuit, and adjacent memory chip units have a first cut. Track (not shown).
  • the memory chip unit may be at least one of SRAM, DRAM, FLASH, PCM, DDR, DDR2, DDR3, and DDR4.
  • the memory chip unit is specifically described by taking a DRAM as an example.
  • the memory chip unit includes: a memory array, a control logic circuit, an interface conversion logic circuit, an original bus, and an ultra-wide bus.
  • the first wafer 300 provided in this embodiment further includes a first docking pad 311 formed on an upper surface of the first wafer 300.
  • the first docking pad 311 is electrically connected to the pad (including the power pad and the signal pad) of the first multilayer metal layer inside the first wafer 300, and the pad of the first multilayer metal layer is electrically The internal bus of the first wafer 300 is connected.
  • a layer or a first multilayer metal layer may be formed on the memory chip unit, and then a first docking pad 311 is formed in the top metal layer, and a wide width is drawn from the memory array of the memory chip unit
  • the internal bus is electrically connected to the first docking pad 311.
  • the peripheral circuit may include at least one of a control logic circuit, an interface conversion logic circuit, and a code correction logic circuit.
  • the control logic circuit includes a row address latch, a memory array control circuit, a column address latch, a bit selection logic circuit, and the like.
  • the first wafer 300 provided in this embodiment further includes: forming a test circuit module in a first scribe lane area.
  • the test circuit module is formed in a first scribe line of the first wafer 300, and the test circuit module may be connected to the first docking pad 311 to test the memory chip unit, thereby improving the final package yield.
  • a second wafer 400 having one or more logic chip units is provided.
  • the area of each logic chip unit corresponds to the area of a plurality of memory chip units. It has a second dicing track (not shown).
  • the second dicing track is matched with the first dicing track on the periphery of the plurality of memory chip units, and reference may be made to the corresponding content in the foregoing embodiment.
  • the area of each logic chip unit corresponding to the area of multiple memory chip units means that the area of each logic chip unit is substantially equal to the area of multiple memory chip units, and the area of multiple memory chip units
  • the shape is the same as the area shape of each logic chip unit.
  • the first docking pad 311 on the multiple memory chip units is opposite to the second docking pad 411 on the logic chip unit. This ensures that the The first docking pad 311 can be electrically connected to the second docking pads 411 of the plurality of memory chip units to form a bonding structure.
  • a second docking pad 411 is formed on a surface of the second wafer 400.
  • the process of forming the second docking pad 411 is similar to the process of forming the first docking pad 311, and reference may be made to the corresponding content in the foregoing embodiment.
  • the second docking pad 411 is electrically connected to the pad of the second multilayer metal layer inside the second wafer 400, and the pad of the second multilayer metal layer is electrically connected to the internal bus of the second wafer 400.
  • the first wafer 300 provided in this embodiment further includes: forming a test circuit module in a second scribe line region.
  • the test circuit module is formed in a second scribe line of the second wafer 400, and the test circuit module may be connected to the second docking pad 411 to test the logic chip unit, thereby improving the final package yield.
  • the difference from the previous embodiment is that in this embodiment, when the first wafer 300 and the second wafer 400 are bonded, the first wafer 300 and the second wafer 400 are physically connected first.
  • the two are specifically overlapped, so that the logic chip unit and the plurality of memory chip units are correspondingly matched.
  • the step of bonding the first wafer 300 and the second wafer 400 further includes: electrically coupling the logic chip unit and the memory chip unit through a TSV process.
  • a TSV structure 413 is formed in the second wafer 400 to electrically connect the second docking pad 411, and the TSV is formed.
  • the other end of the structure 413 is electrically connected to the metal layer 412.
  • a through-silicon via structure 414 is also made in the second wafer 400 to electrically connect the first docking pad 311, and the other end of the TSV structure 413 is also electrically connected to the metal layer 412. Therefore, the first docking pad 311 passes through silicon
  • the via structure 414, the metal layer 412, and the through silicon via structure 413 are electrically connected to the second docking pad 411.
  • wafer thinning, wafer dicing, and chip plastic packaging operations can also be performed subsequently, and details are not described herein again.
  • the wafer-level packaging method for a semiconductor provided in this embodiment can flexibly perform wafer-level packaging of logic chips and memory chips, and has simple operation and low process cost.
  • the semiconductor package includes: a first wafer having one or more memory chip units, and a first chip between adjacent memory chip units. A dicing track; a second wafer having one or more logic chip units, and a second dicing track between adjacent logic chip units, the area of the logic chip units corresponding to the area of N memory chip units Where N is a natural number greater than or equal to 1; the first wafer and the second wafer are bonded to each other, the logic chip unit corresponds to N memory chip units, and the second scribe lane and N The first scribe lines on the periphery of the memory chip unit are matched.
  • the semiconductor package may be formed according to the wafer-level packaging method of the foregoing embodiment. Therefore, for the structure and properties of the semiconductor package, reference may be made to the corresponding content of the foregoing embodiment of the present specification.

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Abstract

一种半导体的晶圆级封装方法和半导体封装件。其中，所述半导体的晶圆级封装方法包括：提供具有一个或多个存储器芯片单元的第一晶圆，每个所述存储器芯片单元具有存储阵列电路与外围电路，相邻所述存储器芯片单元之间具有第一切割道；提供具有一个或多个逻辑芯片单元的第二晶圆，每个所述逻辑芯片单元的面积对应 N 个所述存储器芯片单元的面积，其中 N 为大于或者等于 1 的自然数，相邻所述逻辑芯片单元之间具有第二切割道，所述第二切割道与 N 个所述存储芯片单元外围的所述第一切割道匹配；键合所述第一晶圆和第二晶圆，使所述逻辑芯片单元与 N 个所述存储器芯片单元对应匹配。所述半导体的晶圆级封装方法提高存储器晶圆的封装适用范围。

Description

半导体的晶圆级封装方法和半导体封装件 技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体的晶圆级封装方法和半导体封装件。
背景技术
存储器有多种，比如静态随机存储器(Static Random Access Memory，SRAM)，动态随机存储器(Dynamic Random Access Memory，DRAM)，闪存(FLASH)，相变存储器(Phase Change Memory，PCM)等等，它们广泛用于各种电子设备中，在电路中占据重要的位置。
逻辑芯片通常指具有可编程逻辑器件(programmable logic device，PLD)的芯片，逻辑芯片集成度很高，足以满足设计一般的数字系统的需要。
现有存储芯片和逻辑芯片连接的方式目前一般有如下几种：
1.两者裸片各自封装，完成之后都焊接在电路板上，通过电路板走线相连。
2.两者裸片通过打线至基板上相连，然后整体封装。
3.两者裸片晶圆(即包括有逻辑芯片单元的晶圆和包括有存储器芯片单元的晶圆)上生长微焊盘，通过微焊盘两者直接相连，然后整体封装。
以上三种方式从总体上说，从方式1到方式3，封装性能变好，功耗减少，体积变小，成本降低。
对于前两种封装方式，一般有双列直插封装，扁平封装，球栅封装等，这些封装方法需要将晶圆切割成裸片后再单独封装。其中，晶圆级封装是在整片晶圆上整体处理，长出锡球，然后进行切割后即得到封装好的芯片。晶圆级封装相对一般封装具有成本更低，一致性更好，封装体积更小等优点。
对于第三种封装方式，是晶圆至晶圆封装，具体是将两块大小一样的晶圆直接键合，两块晶圆上每个芯片的大小一样，管脚排布相对应，键合完成后两块晶圆上的所有芯片之间的连接即完成，然后再做整体封装，引出对外焊盘，切分开之后即得到连接好的单个芯片组。
晶圆至晶圆封装同时完成两块晶圆上所有芯片的连接，不需要像前面两种方式，需要逐个对两种芯片做连接，因此成本更低，并且因为所有芯片同时键合和封装，所以得到产品的一致性比逐个封装更好。但目前晶圆至晶圆封装的应用范围还非常狭窄。
为此，需要一种新的半导体的晶圆级封装方法和半导体封装件，以扩大晶圆至晶圆封装的应用范围，提高半导体封装的灵活性，并且简化封装方法，并且能够降低不同面积的芯片在封装时的面积浪费，提高存储器晶圆的封装适用范围。
发明内容
本发明解决的问题是提供一种半导体的晶圆级封装方法和半导体封装件，以扩大晶圆至晶圆封装的应用范围，提高半导体封装的灵活性，并且简化封装方法，降低不同面积的芯片在封装时的面积浪费。
为解决上述问题，本发明提供一种半导体的晶圆级封装方法，包括：
提供具有一个或多个存储器芯片单元的第一晶圆，每个所述存储器芯片单元具有存储阵列电路与外围电路，相邻所述存储器芯片单元之间具有第一切割道；
提供具有一个或多个逻辑芯片单元的第二晶圆，每个所述逻辑芯片单元的面积对应N个所述存储器芯片单元的面积，其中N为大于或者等于1的自然数，相邻所述逻辑芯片单元之间具有第二切割道，所述第二切割道与N个所述存储芯片单元外围的所述第一切割道匹配；
键合所述第一晶圆和第二晶圆，使所述逻辑芯片单元与N个所述存储器芯片单元对应匹配。
可选的，键合所述第一晶圆和第二晶圆的步骤包括：
形成位于所述第一晶圆上表面的第一对接焊盘；
形成位于所述第二晶圆上表面的第二对接焊盘；
电性键合所述第一对接焊盘与所述第二对接焊盘。
可选的，键合所述第一晶圆和第二晶圆的步骤包括：
所述第一晶圆与第二晶圆物理连接；
通过硅穿孔工艺电性耦合所述的逻辑芯片单元与存储器芯片单元。
可选的，所述第一对接焊盘电性连接所述第一晶圆内部的第一多层金属层的焊盘，所述第一多层金属层的焊盘电性连接所述第一晶圆内部总线；所述第二对接焊盘电性连接所述第二晶圆内部的第二多层金属层的焊盘，所述第二多层金属层的焊盘电性连接所述第二晶圆内部总线。
可选的，所述存储器芯片单元包括：SRAM、DRAM、FLASH、PCM、DDR、DDR2、DDR3和DDR4中的至少一种。
可选的，所述外围电路包括：控制逻辑电路、接口转换逻辑电路和纠码逻辑电路中的至少一种。
可选的，提供所述第一晶圆还包括：
于所述第一切割道区域形成测试电路模块。
可选的，提供所述第二晶圆还包括：
于所述第二切割道区域形成测试电路模块。
可选的，键合所述第一晶圆和第二晶圆之后还包括：研磨减薄所述第一晶圆和第二晶圆。
为解决上述问题，本发明还提供了一种半导体封装件，包括：
第一晶圆，具有一个或多个存储器芯片单元，相邻所述存储器芯片单元之间具有第一切割道；
第二晶圆，具有一个或多个逻辑芯片单元，相邻所述逻辑芯片 单元之间具有第二切割道，所述逻辑芯片单元的面积对应N个所述存储器芯片单元的面积，其中，N为大于或者等于1的自然数；
所述第一晶圆和第二晶圆相互键合，所述逻辑芯片单元对应N个所述存储器芯片单元，所述第二切割道与N个所述存储芯片单元外围的第一切割道匹配。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的技术方案中，设计一个逻辑芯片单元与N个存储芯片单元对应匹配，其中，N为大于或者等于1的自然数，从而保证两个晶圆能够直接进行键合与封装，特别当N大于1时，可以充分利用两个芯片单元之间的面积对应关系进行匹配，从而降低面积浪费，提高存储器晶圆的封装适用范围。
进一步，在晶圆的切割道设置形成测试电路模块。所述测试电路模块形成在第一晶圆的第一切割道中，所述测试电路模块可以与第一对接焊盘相连，以便对存储器芯片单元进行测试，从而提高最终的封装良率。
附图说明
图1是本发明实施例所提供的第一晶圆示意图；
图2是图1所示第一晶圆中存储器芯片组成结构示意图；
图3是本发明实施例所提供的第二晶圆示意图；
图4是图1所示第一晶圆和图3所示第二晶圆键合前正对设置的示意图；
图5是本发明又一实施例所提供的第一晶圆和第二晶圆键合设置的示意图。
具体实施方式
正如背景技术所述，目前的晶圆至晶圆封装在应用还非常狭窄，一种存储晶圆无法适应不同大小的逻辑晶圆，一般只能使用于一种逻辑晶圆。
为此，本发明提供一种新的半导体的晶圆级封装方法，所述方法通过使得一个逻辑芯片单元与一个以上的存储器芯片单元进行匹配，从而提高晶圆至晶圆封装的应用范围，并且降低芯片面积的浪费。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
本发明实施例提供一种半导体的晶圆级封装方法，请结合参图1至图4。
请参考图1，提供具有一个或多个存储器芯片单元110的第一晶圆100。图1中显示了第一晶圆100的4个呈2×2矩阵排列的存储器芯片单元110为代表。每个存储器芯片单元110具有存储阵列电路(请参考图2)与外围电路(未显示)，相邻存储器芯片单元110之间具有第一切割道101。
存储器芯片单元110可以为SRAM、DRAM、FLASH、PCM、DDR、DDR2、DDR3和DDR4中的至少一种。本实施例中，存储器芯片单元110具体以DRAM为例进行说明。
请参考图2，存储器芯片单元110可以包括存储阵列10、控制逻辑电路20、接口转换逻辑电路30、原有总线40(包括地址总线和数据总线)和超宽总线40’(包括超宽地址总线和超宽数据总线)。
请继续参考图2，所述存储阵列10包括：8个bank(bank0～bank7)，每个bank中包括有多个存储单元，存储阵列10用于存储数据。
请继续参考图2，所述控制逻辑电路20包括：行地址锁存、存储阵列控制(电路)、列地址锁存、位选择逻辑(电路)等，所述控制逻辑电路20用于控制存储阵列10，以实现对所述各bank中特定存储单元的读写操作。
所述接口转换逻辑电路30用于将从所述bank中读取出来的数据经过串并转换后，从特定接口中传输出去。经过所述接口转换逻辑电路30的数据总线宽度将大大限缩。
请继续参考图2，所述原有总线40包括：原有地址总线和原有数据总线。所述原有地址总线宽度一般在15比特左右；所述原有数据总线宽度一般为4、8、16比特。在本实施例中，所述接口逻辑转换电路串并转换前的原有数据总线宽度为16比特，经所述接口逻辑转换电路串并转换之后的原有数据总线宽度缩窄为了4比特。经串并转换后的原有数据总线将最终连接到信号焊盘(图未示)上，以满足传统DRAM封装的需要。
请继续参考图2，所述超宽总线40’包括超宽地址总线和超宽数据总线。所述超宽总线40’的宽度明显宽于所述原有总线40。具体地，所述超宽地址总线可分为多路(比如：2、4、8路等，本实施例中仅以1路示意)，每一路宽度在32比特左右。所述超宽数据总线也可分为多路，每路宽度可为64、128、256比特，甚至更宽。本实施例中，所述超宽数据总线的宽度为128比特。所述超宽数据总线不经过所述接口转换逻辑电路30，而是连同所述超宽地址总线一起，直接与微焊盘(图未示)连接，以实现超宽总线的DRAM。
当存储器芯片单元110为DRAM时，为保证DRAM的可靠性或者提高复用率，存储器芯片单元110内部总线可以与多组存储阵列连接。所述存储阵列可以包括多个bank，用于存储数据。所述内部总线是与所述存储阵列相连、宽度较宽的数据总线和控制总线，其数据宽度可大于或者等于64比特。所述内部总线至少与一组存储阵列相连。
图1和图2虽未显示，但本实施例中，DRAM的存储器芯片单元110上可以形成有第一顶层金属层(未显示)，第一顶层金属层上形成有电源焊盘(未显示)、信号焊盘(未显示)和微焊盘(未显示)，存储器芯片单元110的内部总线与微焊盘电相连。
本实施例所提供的第一晶圆100中，还包括形成位于第一晶圆100上表面的第一对接焊盘111，如图1所示。第一对接焊盘111电性连接第一晶圆100内部的第一多层金属层的焊盘(包括所述电源焊盘和信号焊盘等)，第一多层金属层的焊盘电性连接第一晶圆100 内部总线，因此，第一对接焊盘111电性连接第一晶圆100内部总线。
本实施例额外形成的第一对接焊盘111将较宽的内部总线引出至DRAM表面。每个第一对接焊盘111至少与一根所述内部总线相连。为保证DRAM的可靠性或者提高复用率，第一对接焊盘111也可连接多根内部总线。
本实施例中，可以在存储器芯片单元110上可以形成有一层或者第一多层金属层，然后在顶层的金属层中形成第一对接焊盘111，如图1所示。并且从所述存储器芯片单元110的存储阵列中引出宽的内部总线与第一对接焊盘111电相连。
本实施例仍沿用现有DRAM封装中的电源焊盘和信号焊盘。所述电源焊盘用于为DRAM供电，所述信号焊盘用于通过传统的接口控制逻辑电路实现DRAM读取。
本实施例中，正如上述所述，所述外围电路可以包括控制逻辑电路、接口转换逻辑电路和纠码逻辑电路中的至少一种。所述控制逻辑电路包括：行地址锁存、存储阵列控制电路、列地址锁存、位选择逻辑电路等，用于控制所述存储阵列，实现对所述bank中特定存储单元的读写操作。所述接口转换逻辑电路用于将从所述bank中读取出来的数据经过串并转换，从特定接口中传输出去。经过所述接口转换逻辑电路的数据总线宽度将大大限缩。
需要说明的是，在本发明的其它实施例中，也可以采用标准DRAM的一个或多个bank的存储单元加上外围电路成为存储器芯片单元110，或者采用标准FLASH的一个或多个区块加上外围电路成为一个存储器芯片单元110。
图1和图2虽未显示，但本实施例所提供的第一晶圆100还可以包括：于第一切割道101区域形成测试电路模块。所述测试电路模块形成在第一晶圆100的第一切割道101中，所述测试电路模块可以与第一对接焊盘111相连，以便对存储器芯片单元110进行测试。
请参考图3，提供具有一个或多个逻辑芯片单元210的第二晶圆200，图3中显示了第二晶圆200的其中一个逻辑芯片单元210为代表。
本实施例中，每个逻辑芯片单元210的面积对应4个存储器芯片单元110的面积。
本实施例中，相邻逻辑芯片单元210之间具有第二切割道201，第二切割道201与4个存储芯片单元外围的第一切割道101匹配(后续请参考图4相应内容)。
本实施例中，每个逻辑芯片单元210的面积对应4个存储器芯片单元110的面积是指：每个逻辑芯片单元210的面积与4个存储器芯片单元110的面积基本相等，并且，4个存储器芯片单元110的面积形状与每个逻辑芯片单元210的面积形状相同，4个存储器芯片单元110上的第一对接焊盘111与逻辑芯片单元210上的第二对接焊盘211位置相对，这样，保证后续1个逻辑芯片单元210的第一对接焊盘111能够与4个存储器芯片单元110的第二对接焊盘211相互电连接在一起，形成键合结构。
现有晶圆至晶圆封装在应用还非常狭窄，其中一个主要原因是：晶圆至晶圆封装要求对接的两片晶圆上的芯片大小一致，而逻辑晶圆和存储晶圆一般是由不同厂家生产，大小一般是不相同的。如果要将两者做成相同大小，将小的芯片填充以扩大芯片面积，这样将会造成浪费。并且不同设计的逻辑晶圆的大小差别很大，一种存储晶圆无法适应不同大小的逻辑晶圆，一般只能使用于一种逻辑晶圆。
而本发明的实施例中，1个逻辑芯片单元可以对应1个或者1个以上的存储器芯片单元，扩大了晶圆至晶圆封装的应用范围，并且降低面积浪费，提高存储器晶圆的封装适用范围。
需要说明的是，在本发明的其它实施例中，每个逻辑芯片单元210的面积也可以对应1个、2个、3个或者5个以上的存储器芯片单元110的面积，本发明对此不作限定。也就是说，每个逻辑芯片单元210的面积可以对应N个存储器芯片单元110的面积，其中N 为大于或等于1的自然数。
本实施例中，所提供的第二晶圆200上表面还具有位于逻辑芯片单元210表面的第二对接焊盘211。第二对接焊盘211电性连接第二晶圆200内部的第二多层金属层的焊盘，第二多层金属层的焊盘电性连接第二晶圆200内部总线。形成第二对接焊盘211与形成第一对接焊盘111的过程类似，可参考前述相应内容。
本实施例中，第二对接焊盘211与第一对接焊盘111位置相对应，从而保证后续逻辑芯片单元210能够与存储器芯片单元110对应匹配。
本实施例所提供的第一晶圆100还包括：于第二切割道201区域形成测试电路模块。所述测试电路模块形成在第二晶圆200的第二切割道201中，所述测试电路模块可以与第二对接焊盘211相连，以便对逻辑芯片单元210进行测试，从而提高最终的封装良率。
需要说明的是，可以对所提供的第一晶圆100和第二晶圆200进行修复。本发明对修复晶圆的方法不作具体限定，现有技术中已有多种修复晶圆的方法，比如：激光修复(laser trimming)等，皆可应用于本发明。通过修复，可进一步提高所述第一晶圆100的良品率。
请参考图4，键合第一晶圆100和第二晶圆200，使逻辑芯片单元210与4个存储器芯片单元110对应匹配。
图4显示了第一晶圆100和第二晶圆200键合之前的瞬间(即两个所述晶圆正对的情形)。
本实施例中，4个存储器芯片单元110的组合外围的第一切割道101与1个逻辑芯片单元210的第二切割道201相对应(可根据图4中各未标注的四条虚线直观判断)，从而保证1个逻辑芯片单元210与4个存储器芯片单元110对应匹配。并且，正如前面所述，4个存储器芯片单元110的第一对接焊盘111与1个逻辑芯片单元210的第二对接焊盘211相对应，因此，在键合第一晶圆100和第二晶圆200时，即是电性键合第一对接焊盘111与第二对接焊盘211。
本实施例中，在键合第一晶圆100和第二晶圆200之后，还可以研磨减薄第一晶圆100和第二晶圆200中的至少其中之一。一般晶圆的逻辑电路和金属走线部分用到的厚度大约在100μm左右，但晶圆整体厚度在1000μm左右以提供较好的支撑。键合后的晶圆，逻辑电路部分和走线部分处于两片晶圆中间位置，此时晶圆太厚不利于散热，减薄晶圆厚度可以提升散热效果，从而使最终得到的组件厚度较小，散热性能提高。
本实施例中，在将第一晶圆100和第二晶圆200键合之后，后续还可以进行晶圆的切割，以形成单个芯片组合(每个芯片组合包括1个逻辑芯片单元210与4个存储器芯片单元110，并且它们之间电性键合)，并对每个芯片组合进行塑封。
本发明又一实施例提供另一种半导体的晶圆级封装方法，请参考图5。
请参考图5，提供具有一个或多个存储器芯片单元(未示出)的第一晶圆300，每个存储器芯片单元具有存储阵列电路与外围电路，相邻存储器芯片单元之间具有第一切割道(未示出)。
存储器芯片单元可以为SRAM、DRAM、FLASH、PCM、DDR、DDR2、DDR3和DDR4中的至少一种。本实施例中，存储器芯片单元具体以DRAM为例进行说明。
具体地，所述存储器芯片单元包括：存储阵列、控制逻辑电路、接口转换逻辑电路、原有总线和超宽总线。
本实施例所提供的第一晶圆300中，还包括形成位于第一晶圆300上表面的第一对接焊盘311。第一对接焊盘311电性连接第一晶圆300内部的第一多层金属层的焊盘(包括所述电源焊盘和信号焊盘等)，第一多层金属层的焊盘电性连接第一晶圆300内部总线。
本实施例中，可以在存储器芯片单元上形成一层或者第一多层金属层，然后在顶层的金属层中形成第一对接焊盘311，并且从所述存储器芯片单元的存储阵列中引出宽的内部总线与第一对接焊盘311电相连。
本实施例中，所述外围电路可以包括控制逻辑电路、接口转换逻辑电路和纠码逻辑电路中的至少一种。所述控制逻辑电路包括：行地址锁存、存储阵列控制电路、列地址锁存、位选择逻辑电路等。
本实施例所提供的第一晶圆300还包括：于第一切割道区域形成测试电路模块。所述测试电路模块形成在第一晶圆300的第一切割道中，所述测试电路模块可以与第一对接焊盘311相连，以便对存储器芯片单元进行测试，从而提高最终的封装良率。
请继续参考图5，提供具有一个或多个逻辑芯片单元(未示出)的第二晶圆400，每个逻辑芯片单元的面积对应多个存储器芯片单元的面积，相邻逻辑芯片单元之间具有第二切割道(未示出)，第二切割道与多个存储芯片单元外围的第一切割道匹配，可参考前述实施例相应内容。
本实施例中，每个逻辑芯片单元的面积对应多个存储器芯片单元的面积是指：每个逻辑芯片单元的面积与多个存储器芯片单元的面积基本相等，并且，多个存储器芯片单元的面积形状与每个逻辑芯片单元的面积形状相同，多个存储器芯片单元上的第一对接焊盘311与逻辑芯片单元上的第二对接焊盘411位置相对，这样，保证后续1个逻辑芯片单元的第一对接焊盘311能够与多个存储器芯片单元的第二对接焊盘411相互电连接在一起，形成键合结构。
请继续参考图5，第二晶圆400表面形成有第二对接焊盘411。形成第二对接焊盘411与形成第一对接焊盘311的过程类似，可参考前述实施例相应内容。
第二对接焊盘411电性连接第二晶圆400内部的第二多层金属层的焊盘，第二多层金属层的焊盘电性连接第二晶圆400内部总线。
本实施例所提供的第一晶圆300还包括：于第二切割道区域形成测试电路模块。所述测试电路模块形成在第二晶圆400的第二切割道中，所述测试电路模块可以与第二对接焊盘411相连，以便对逻辑芯片单元进行测试，从而提高最终的封装良率。
请参考图5，与前述实施例不同的是，本实施例在键合第一晶圆 300与第二晶圆400时，先使第一晶圆300与第二晶圆400物理连接，本实施例中，具体使得两者叠合在一起，从而使逻辑芯片单元与多个存储器芯片单元对应匹配。
请继续参考图5，键合所述第一晶圆300和第二晶圆400的步骤还包括：通过硅穿孔工艺电性耦合所述的逻辑芯片单元与存储器芯片单元。图5中，显示了在第一晶圆300与第二晶圆400叠合在一起后，在第二晶圆400中制作硅通孔结构413电连接第二对接焊盘411，并且硅通孔结构413的另一端电连接金属层412。同时第二晶圆400中还制作了硅通孔结构414电连接第一对接焊盘311，并且硅通孔结构413的另一端也电连接金属层412，因此，第一对接焊盘311通过硅通孔结构414、金属层412和硅通孔结构413与第二对接焊盘411电性连接。
本实施例后续同样可以进行晶圆减薄、晶圆切割和芯片塑封的操作，在此不再赘述。
本实施例所提供的半导体的晶圆级封装方法能够灵活地对逻辑芯片和存储器芯片进行晶圆级封装，并且操作简便，工艺成本低。
本发明又一实施例还提供了一种半导体封装件，具体的，所述半导体封装件包括：第一晶圆，具有一个或多个存储器芯片单元，相邻所述存储器芯片单元之间具有第一切割道；第二晶圆，具有一个或多个逻辑芯片单元，相邻所述逻辑芯片单元之间具有第二切割道，所述逻辑芯片单元的面积对应N个所述存储器芯片单元的面积，其中，N为大于或者等于1的自然数；所述第一晶圆和第二晶圆相互键合，所述逻辑芯片单元对应N个所述存储器芯片单元，所述第二切割道与N个所述存储芯片单元外围的第一切割道匹配。所述半导体封装件可以根据前述实施例的晶圆级封装方法形成，因此，所述半导体封装件的结构和性质可参考本说明书前述实施例相应内容。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改， 因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

  1. 一种半导体的晶圆级封装方法，其特征在于，包括：
    提供具有一个或多个存储器芯片单元的第一晶圆，每个所述存储器芯片单元具有存储阵列电路与外围电路，相邻所述存储器芯片单元之间具有第一切割道；
    提供具有一个或多个逻辑芯片单元的第二晶圆，每个所述逻辑芯片单元的面积对应N个所述存储器芯片单元的面积，其中N为大于或者等于1的自然数，相邻所述逻辑芯片单元之间具有第二切割道，所述第二切割道与N个所述存储芯片单元外围的所述第一切割道匹配；
    键合所述第一晶圆和第二晶圆，使所述逻辑芯片单元与N个所述存储器芯片单元对应匹配。
  2. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，键合所述第一晶圆和第二晶圆的步骤包括：
    形成位于所述第一晶圆上表面的第一对接焊盘；
    形成位于所述第二晶圆上表面的第二对接焊盘；
    电性键合所述第一对接焊盘与所述第二对接焊盘。
  3. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，键合所述第一晶圆和第二晶圆的步骤包括：
    所述第一晶圆与第二晶圆物理连接；
    通过硅穿孔工艺电性耦合所述的逻辑芯片单元与存储器芯片单元。
  4. 根据权利要求2所述的半导体的晶圆级封装方法，其特征在于，所述第一对接焊盘电性连接所述第一晶圆内部的第一多层金属层的焊盘，所述第一多层金属层的焊盘电性连接所述第一晶圆内部总线；所述第二对接焊盘电性连接所述第二晶圆内部的第二多层金属层的焊盘，所述第二多层金属层的焊盘电性连接所述第二晶圆内部总线。
  5. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，所述存储器芯片单元包括：SRAM、DRAM、FLASH、PCM、DDR、DDR2、DDR3和DDR4中的至少一种。
  6. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，所述外围电路包括：控制逻辑电路、接口转换逻辑电路和纠码逻辑电路中的至少一种。
  7. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，提供所述第一晶圆还包括：
    于所述第一切割道区域形成测试电路模块。
  8. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，提供所述第二晶圆还包括：
    于所述第二切割道区域形成测试电路模块。
  9. 根据权利要求1所述的半导体的晶圆级封装方法，其特征在于，键合所述第一晶圆和第二晶圆之后还包括：研磨减薄所述第一晶圆和第二晶圆。
  10. 一种半导体封装件，其特征在于，包括：
    第一晶圆，具有一个或多个存储器芯片单元，相邻所述存储器芯片单元之间具有第一切割道；
    第二晶圆，具有一个或多个逻辑芯片单元，相邻所述逻辑芯片单元之间具有第二切割道，所述逻辑芯片单元的面积对应N个所述存储器芯片单元的面积，其中，N为大于或者等于1的自然数；
    所述第一晶圆和第二晶圆相互键合，所述逻辑芯片单元对应N个所述存储器芯片单元，所述第二切割道与N个所述存储芯片单元外围的第一切割道匹配。
PCT/CN2018/092885 2018-06-26 2018-06-26 半导体的晶圆级封装方法和半导体封装件 WO2020000183A1 (zh)

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CN102117800A (zh) * 2010-01-05 2011-07-06 联华电子股份有限公司 半导体芯片堆迭及其制作方法
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