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CN108962301B - 一种存储装置 - Google Patents

一种存储装置 Download PDF

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CN108962301B
CN108962301B CN201810510628.4A CN201810510628A CN108962301B CN 108962301 B CN108962301 B CN 108962301B CN 201810510628 A CN201810510628 A CN 201810510628A CN 108962301 B CN108962301 B CN 108962301B
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memory
ddr
package
logic chip
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CN108962301A (zh
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濮必得
殷和国
赵修金
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Simonda Semiconductor Technology Jinan Co ltd
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Jinan Deouya Security Technology Co ltd
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    • H01L2224/321—Disposition
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Abstract

本发明提供一种存储装置，所述装置包括逻辑芯片，以及一个或多个存储芯片，用于连接或键合逻辑和存储器芯片的封装以实现芯片间传导电信号，设置在封装内的互连网络用于提供多个路径的电连接(i)封装外部连接器和逻辑芯片之间的DQ和DQS信号的多个导电路径，以及(ii)将内部DQ和/或连接逻辑芯片和存储器阵列芯片DQS信号电分离，其中内部DQ和/或连接逻辑芯片存储器阵列芯片DQS信号布线路径要短，即小于整个封装长度的一半。实现花费很少的时间即可完成内存芯片的全面重新设计，提高了存储装置内部逻辑芯片和存储芯片之间的数据传输速度，提高了存储器阵列芯片和外界环境(其它芯片)通信的可靠性。

Description

一种存储装置
技术领域
本发明涉及半导体集成领域，特别是一种存储装置。
背景技术
动态随机存取存储器DRAM和闪存Flash存储器技术已发展多年，DRAM和Flash的基本技术基本上保持不变，只是接口随时间变化不断更新，例如快速页面模式(FPM)，扩展数据输出(EDO)，同步DRAM(SDRAM)，双倍数据速率1-4(DDR1，DDR2，DDR3，DDR4)等。
图1显示了DRAM的基本架构。外部提供的行地址被解码并导致字线WL的激活，例如，连接到8192个单独的存储单元的门。这将会开始一个感测过程，放大那些微弱的信号，如8192个单独的存储单元，并将它们保存在读出放大器SA中。
之后，将通过相同的外部地址线在行地址之后顺序提供列地址。该列地址通过选择WL的子集的列解码器提供，即，例如8192个选定的位的子集。在我们的例子中，1：128解码选择8192个感测位中的64个被转发到次级读出放大器。当今最先进的DRAM技术通常执行所谓的预取，即在内部访问更多的数据，而不是转发到外部引脚。在我们的例子中，我们预取了64位，然后通过一个序列发生器顺序地将其转发到外部I/O驱动器(例如4个16位依次被16个I/O驱动器驱动)。
图2显示了典型DRAM架构实现的具体例子。为了最低功耗和最低成本，这种DRAM通常以低成本和低性能的CMOS或类似技术完成。实际的存储单元被分成几个，例如，4个独立的内存块。通过用于外部连接的焊盘行访问DRAM。在大多数标准设计中，如图所示采用中央焊盘排列设计，但也有分布在芯片四周的设计。用于从内部存储器单元到外部焊盘的信号处理的逻辑电路部分位于深内存阵列芯片之外。不幸的是，由于在同一芯片上，这个信号处理电路必须以相同的差的CMOS技术来实现，以折中性能参数，如速度和功耗。
图3显示了一个标准FBGA(Fine Ball Grid Array，细间距球栅阵列封装)78(管脚)元件，其中DRAM芯片301面朝下地连接在衬底302材料上。通过线303键合，它通过衬底底部的信号线连接到外部封装球上。其他配置也可能是芯片正面朝上或多个芯片彼此并排或堆叠放置(参见例如图4)。
基板实现一个，两个或多个布线层级以将引线键合或以其他方式连接的芯片信号连接到外部封装连接器(通常为焊球)。图5作为例子示出了单层基板的布线。此外，还可以通过在芯片之上提供一个或多个导电布线层的技术在芯片上连接信号。其中一种最先进的技术就是RDL--再分配层技术。图6示出了在芯片上应用单层RDL技术以将芯片焊盘布线和连接到芯片上的不同位置的示例。为了完整起见，我们在图7中列出了JEDEC标准定义的DRAM操作的最重要的信号，这些名称在一些权利要求和其他相关专利中被引用。
发明内容
本发明的目的是提供一种存储装置，旨在解决提供一种新型的存储器的封装技术，实现花费很少的时间即可完成内存芯片的全面重新设计，提高了存储装置内部逻辑芯片和存储芯片之间的数据传输速度，提高了内存阵列芯片和外界环境(其它芯片)通信的可靠性。
为了达到上述目的，本发明提供一种存储装置，包括：
逻辑芯片，以及一个或多个存储芯片；所述逻辑芯片采用第一种工艺技术，所述存储芯片采用第二种工艺技术，第一种工艺技术不同于第二种工艺技术；
存储装置中采用连接或键合逻辑和存储器芯片的封装，以实现芯片间传导电信号；
存储装置中设置在封装内的互连网络，用于提供多个路径的电连接(i)封装外部连接器和逻辑芯片之间的DQ和DQS信号的多个导电路径，以及(ii)将内部DQ和/或连接逻辑芯片内存阵列芯片DQS信号电分离，其中内部DQ和/或连接逻辑芯片内存阵列芯片DQS信号布线路径要短，即小于整个封装长度的一半。
优选地，所述存储装置还包括：
设置在封装内的互连网络，用于提供多个路径的电连接(i)封装外部连接器和逻辑芯片之间的地址信号的多个导电路径，以及(i i)逻辑芯片和内存阵列芯片之间的电相同或电隔离的地址信号，以及(iii)封装外部连接器与逻辑芯片之间的命令信号，以及(iv)逻辑芯片与内存阵列芯片之间的内部命令信号。
优选地，所述逻辑芯片的任务是将数据从内部DQ信号未改变地传送到封装外部DQ连接器，逻辑芯片采用第一种工艺技术，该工艺技术为芯片或晶圆技术，所述第一种工艺技术为双极技术，该双极技术高泄漏和高功耗，具有数据传输速率快的特点。
优选地，所述存储芯片采用第二工艺技术，该工艺技术为芯片或晶圆技术，所述存储器芯片采用符合JEDEC标准的BGA-78封装，或者采用符合JEDEC标准的BGA-96封装，或者采用符合JEDEC标准的BGA-136封装，或者采用符合JEDEC标准的BGA-144封装。
优先地，所述存储装置中的无源网络组件还包括一个或多个电容器，至少有一个端子电连接到VDDQ，一个或多个电容器，至少有一个端子电连接到VSSQ。
优先地，所述封装外部的连接器和逻辑芯片之间的多个内部DQ和DQS信号，其与逻辑芯片和内存阵列之间的内部DQ和DQS内部信号不同。
优先地，所述存储装置中，从逻辑芯片到内存阵列的内部DQ信号的数量是从逻辑芯片到封装外部连接器的DQ信号的整数倍，所述整数倍为2,4,8,16,32和64的倍数。
优先地，所述存储装置中，设置在封装内的互连网络，提供多个导电路径，用于将(i)封装外部VDDQ和VDDS信号的大部分(大于50％)电连接到逻辑芯片。
优先地，所述存储阵列芯片为JEDEC标准SDR DRAM，或JEDEC标准DDR DRAM，或JEDEC标准DDR-2DRAM，或JEDEC标准DDR-3DRAM，或JEDEC标准DDR-或者JEDEC标准的NORFlash，或者JEDEC标准的NAND Flash。
所述存储器装置是JEDEC DDR-4，或DDR-3，或DDR-2，或DDR-1，或SDR，或Nor-Flash，或Nand-Flash除了I/O电容和功耗规范之外的闪存兼容，以及符合JEDEC标准的DRAM或Nor-Flash或Nand-Flash封装。
所述逻辑芯片实现了任何JEDEC定义的标准DRAM接口，如FPM(快速寻呼模式)，EDO(扩展数据输出)，SDR(同步数据速率)，DDR-1，DDR-2，DDR-3，DDR-4(DDR＝双倍数据速率)，或任何JEDEC标准的NOR闪存或Nand-Flash接口；至少有一个内存芯片可以实现任何JEDEC定义的标准DRAM接口，如FPM(快速页面模式)，EDO(扩展数据输出)，SDR(同步数据速率)，DDR-1，DDR-2，DDR-3，DDR-4(DDR＝双倍数据速率)或任何JEDEC标准的NOR闪存或Nand-Flash接口。
本发明实施例提供的一种存储装置，由内存芯片和逻辑芯片组成，芯片采用两种不同的技术实现，但封装在一起，并且刚好满足标准的DRAM封装尺寸。在具体实现过程中，将内存阵列大部分与逻辑电路分开，并在两个不同的单独芯片上以两种不同的技术来实现，将逻辑芯片与一个或几个内存阵列芯片(以下称为Cell DRAM，即内存阵列芯片)组合在一个单独的元件封装包中。具体而言，在标准FBGA存储器封装中实现它们，例如，FBGA-78或FBGA-96。新的封装技术可以有效地实现这种存储系统。表面上，这似乎增加了产品成本，然而，采用这种方式可以实现具体许多好处的革命性的不同存储系统，比如：
(1)逻辑接口芯片的更换可以通过快速而廉价的重新设计和制造工艺来完成。这可以花费很少的时间完成内存芯片的全面重新设计。
(2)由于芯片制造工艺不同，逻辑芯片可以实现比存储芯片更高的接口速度(例如双极vs.CMOS工艺)。
(3)如果逻辑芯片与闪存或其他非易失性存储技术相结合，则可以在完成产品测试后用于存储芯片修复。
(4)内存阵列芯片始终通过逻辑芯片与外界环境(其它芯片)进行通信。这将极大地提高可靠性，良率并简化测试，因为不再有数千种具有不同信号时序和形式的不同应用直接访问存储器芯片。
附图说明
图1为DRAM的基本架构；
图2为典型的DRAM架构实现的具体例子；
图3为标准的FBGA 78元件；
图4为两个管芯的多芯片封装结构图；
图5为单层基板的布线图；
图6为单层RDL布线图；
图7为JEDEC标准定义的DRAM操作的最重要的信号；
图8为本发明采用晶圆级封装技术来实现的封装结构图；
图9为本发明采用晶圆级封装技术来实现的布线图；
图10为本发明采用标准的JEDEC DRAM来实现的布线图。
具体实施方式
为了能清楚说明本方案的技术特点，下面通过具体实施方式，并结合其附图，对本发明进行详细阐述。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面结合附图对本发明实施例所提供的一种存储装置进行详细说明。
如图8所示，其示出了本发明应用晶圆级封装技术来实现的可行性。在这种技术中，芯片面朝下安装在载体上，而背面被封装。在从载体移除之后，正面可以通过单层或多层钝化，刻蚀和金属化工艺来布线。此外，被动或其他组件可以被集成到封装中。最后植上锡球来完成产品封装，分离后可以使用单独的存储器或系统组件。
在图9中，存储装置包括逻辑芯片和存储芯片，逻辑芯片采用第一种工艺技术，第一种工艺技术为双极技术，该双极技术其特点是高泄漏和高功耗，具有数据传输速率快的特点，存储芯片采用第二种工艺技术，现有的DRAM器件都是用CMOS技术(互补金属氧化物半导体)实现的，这些技术提供了低泄漏，低功耗，与此同时，它们具有相对较低的性能(由于小晶体管不能驱动非常高的电流，所以总体电路速度很低)，对DRAM而言，采用低泄漏技术是关键所在，.所述存储芯片采用第二种工艺技术，所述存储芯片采用的芯片技术对晶体管器件针对低漏电流进行了优化。比如采用符合JEDEC标准的BGA-78封装，或者采用符合JEDEC标准的BGA-96封装，或者采用符合JEDEC标准的BGA-136封装，或者符合JEDEC标准的BGA-144封装。为了实现芯片间导电信号的传导，采用一个封装包用于连接和键合逻辑芯片和存储芯片，在封装包中设置的互连网络用于提供多个电性连接，具体地，将外部连接器和逻辑芯片之间设置多个路径的DQ信号和DQS信号，将内部的DQ和/或连接逻辑芯片和内存阵列芯片的DQS电分离，其中，内部的DQ信号和/或连接DQ和/或连接内存阵列芯片的DQS信号布线路径要短，所述路径要小于封装长度的一半。外部连接器和逻辑芯片之间许多内部DQ和DQS信号，与逻辑芯片和内存阵列之间的内部DQ和DQS内部信号不同，从逻辑芯片到内存阵列的内部DQ信号的数量是从逻辑芯片到封装外部连接器的DQ信号的整数倍，优选地，所述整数倍为2,4,8,16,32和64的倍数。在封装包中设置的互连网络用于提供多个电性连接，还包括，外部连接器和逻辑芯片之间设置多个路径的地址信号903，将逻辑芯片和内存阵列芯片之间的地址信号903进行电相同或电隔离处理，在外部连接器和逻辑芯片之间设置命令信号904，在逻辑芯片和内存阵列芯片之间设置内部命令信号902。存储装置中还包括无源网络组件，该无源网络组件包括一个或多个电容器，至少有一个端子电连接到VDDQ，至少有一个端子电连接到VSSQ，并且超过50％的封装在外部的VDDQ和VDDS信号电连接到逻辑芯片。
存储装置中的内存阵列芯片为符合JEDEC标准的SDR DRAM，或JEDEC标准DDRDRAM，或JEDEC标准DDR-2DRAM，或JEDEC标准DDR-3DRAM，或JEDEC标准DDR-或者JEDEC标准的NOR Flash，或者JEDEC标准的NAND Flash。
存储器装置是JEDEC DDR-4，或DDR-3，或DDR-2，或DDR-1，或SDR，或Nor-Flash，或Nand-Flash除了I/O电容和功耗规范之外的闪存兼容，以及符合JEDEC标准的DRAM或Nor-Flash或Nand-Flash封装。
所述逻辑芯片实现了任何JEDEC定义的标准DRAM接口，如FPM(快速寻呼模式)，EDO(扩展数据输出)，SDR(同步数据速率)，DDR-1，DDR-2，DDR-3，DDR-4(DDR＝双倍数据速率)，或任何JEDEC标准的NOR闪存或Nand-Flash接口。至少有一个内存芯片可以实现任何JEDEC定义的标准DRAM接口，如FPM(快速页面模式)，EDO(扩展数据输出)，SDR(同步数据速率)，DDR-1，DDR-2，DDR-3，DDR-4(DDR＝双倍数据速率)或任何JEDEC标准的NOR闪存或Nand-Flash接口。
图9示出由逻辑芯片和单个存储器芯片组成的优选具体方案，例如，x16数据I/O配置的4Gb DDR3芯片。我们选择这个产品来证明单层金属化足以实现产品。
在此方案中，我们将来自外部封装球/连接器的地址信号线903连接到逻辑芯片。这不是必须的，但是是首选的，因为它减少了地址负载并且允许逻辑芯片上的冗余处理。
外部命令信号904也被路由到逻辑芯片。在我们的方法中，只需要将内部命令信号902连接回存储单元阵列(称为单元存储器)进行控制。通过尽可能短的数据线901来传送往返于单元存储器的存储数据。外部封装球/连接器的数据通过数据线901传输到逻辑芯片或从逻辑芯片传输。其中与VDDQ或VSSQ连接的线(典型地，如线905)代表电源连接。
从图9中可以看出，有可能在没有交叉的情况下进行路由，即单级金属化就足够了。大约60个外部封装信号将跨越单元存储器和逻辑芯片之间的边界。此外，在逻辑芯片的同一区域至少需要实现16个I/O和20个地址/命令焊盘。今天的标准晶圆级封装技术已经提供了10um的线路/空间和50um的焊盘间距。这意味着，如果以单排形式实现，则以直接简单的解决方案将总共需要60×20μm+36×50μm＝3000μm。可以看出，这样的实施有足够的地方。
图10示出了本发明的一个特例.Cell DRAM已经被市场上可用的标准DRAM取代。在需要支持传统市场的情况下，这是有利的，但是产品不再可用，或者需要较小数量的密度来进行设备升级。例如，大多数公司现在停止供应SDR DRAM，因为随着时间的推移，DRAM接口从SDR迁移到DDR-1，DDR-2，DDR-3，现在正在向DDR-4过渡。一些罕见的512SDR或1G SDR仍在市场上。然而，利用所提出的方法，可以使用市场上可用的4G DDR-3芯片来实现例如一个2GSDR通过适当设计逻辑芯片的功能。由于目前大多数标准的DRAM芯片设计使用了中心焊盘排，因此该图显示了中心焊盘排。在这种情况下，单个金属化解决方案在理论上是可能的，但实际上不可行。为了向DRAM芯片提供足够的电源(特别是VSSQ和VDDQ)，可能需要2级金属化。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种存储装置，其特征在于，包括逻辑芯片，以及一个或多个存储芯片；所述逻辑芯片采用第一种工艺技术，所述存储芯片采用第二种工艺技术，第一种工艺技术不同于第二种工艺技术；
存储装置中采用连接或键合逻辑和存储器芯片的封装，以实现芯片间的导电信号的传输；
存储装置中提供多个导电通道的电连接的设置在封装包内的互连网络包括(i)在封装外部连接器和逻辑芯片之间的DQ和DQS信号，以及(ii)内部的DQ和/或内部的DQS信号电分离，内部DQ和/或内部的DQS信号连接逻辑芯片与内存阵列芯片，其中内部DQ和/或内部的DQS信号连接逻辑芯片与内存阵列芯片是短的，即少于封装包的长度的一半；
封装外部连接器和逻辑芯片之间的多个内部DQ和DQS信号，其与逻辑芯片和内存阵列芯片之间的内部DQ和DQS内部信号不同，从逻辑芯片到内存阵列芯片的内部DQ信号的数量是从逻辑芯片到封装外部连接器的DQ信号的整数倍；
用于提供多个导电通道的电连接的设置在封装包内的互连网络还包括(i)在封装外部连接器和逻辑芯片之间的地址信号，以及(ii)在逻辑芯片和内存阵列芯片之间使用相同或电分离的地址信号，以及(iii)封装外部连接器与逻辑芯片之间的命令信号，以及(iv)逻辑芯片与内存阵列芯片之间的内部命令信号；
所述第一种工艺技术为双极技术；第二种工艺技术为芯片或晶圆技术；逻辑芯片实现JEDEC定义的标准DRAM接口，包括FPM，EDO，SDR，DDR-1，DDR-2，DDR-3，DDR-4，JEDEC标准的NOR闪存或Nand-Flash接口；至少有一个内存芯片实现JEDEC定义的标准DRAM接口，包括FPM，EDO，SDR，DDR-1，DDR-2，DDR-3，DDR-4，JEDEC标准的NOR闪存或Nand-Flash接口；
所述DQ信号为数据信号，信号类型为输入/输出数据信号，所述DQS信号为数据片选信号，信号类型为输入/输出控制信号。
2.根据权利要求1所述的一种存储装置，其特征在于，存储器芯片采用符合JEDEC标准的BGA-78封装，或者采用符合JEDEC标准的BGA-96封装，或者采用符合JEDEC标准的BGA-136封装，或者采用符合JEDEC标准的BGA-144封装。
3.根据权利要求1所述的一种存储装置，其特征在于，还包括以下无源网络组件：
一个或多个电容器，至少有一个端子电连接到VDDQ；
一个或多个电容器，至少有一个端子电连接到VSSQ。
4.根据权利要求1所述的一种存储装置，其特征在于，还包括：
用于提供多个导电通道的电连接的设置在封装包内的互连网络还包括，用于将封装外部VDDQ和VDDS信号的大部分(大于50％)电连接到逻辑芯片。
5.根据权利要求1所述的一种存储装置，其特征在于，所述存储芯片为JEDEC标准SDRDRAM，或JEDEC标准DDR DRAM，或JEDEC标准DDR-2DRAM，或JEDEC标准DDR-3DRAM，或JEDEC标准DDR-或者JEDEC标准的NOR Flash，或者JEDEC标准的NAND Flash。
6.根据权利要求1所述的一种存储装置，其特征在于，所述存储器装置是JEDEC DDR-4，或DDR-3，或DDR-2，或DDR-1，或SDR，或Nor-Flash，或Nand-Flash除了I/O电容和功耗规范之外的闪存兼容，以及符合JEDEC标准的DRAM或Nor-Flash或Nand-Flash封装。
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