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WO2019214093A1 - 一种驱动电路 - Google Patents

一种驱动电路 Download PDF

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Publication number
WO2019214093A1
WO2019214093A1 PCT/CN2018/098215 CN2018098215W WO2019214093A1 WO 2019214093 A1 WO2019214093 A1 WO 2019214093A1 CN 2018098215 W CN2018098215 W CN 2018098215W WO 2019214093 A1 WO2019214093 A1 WO 2019214093A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
voltage
clock signal
capacitor
Prior art date
Application number
PCT/CN2018/098215
Other languages
English (en)
French (fr)
Inventor
川岛进吾
李光
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/094,477 priority Critical patent/US10777149B2/en
Publication of WO2019214093A1 publication Critical patent/WO2019214093A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit.
  • the driving circuit of the liquid crystal display panel is more and more widely applied to display devices, and it is becoming more and more important to improve the reliability of the output signal of the driving circuit of the liquid crystal display panel.
  • the driving circuit structure of the existing liquid crystal display panel is relatively complicated.
  • the invention provides a driving circuit capable of simplifying the structure of the driving circuit under the premise of ensuring the normal operation of the liquid crystal display panel.
  • the invention provides a driving circuit, comprising: an input module, a first control module, a second control module, a third control module, an output module and a reset module;
  • the input module is connected to the level signal input end, the first clock signal end, the low level end, the first node and the third node, and is configured to be under the control of the first clock signal of the first clock signal end a voltage of the first node is aligned with a voltage of the low-level end, and a voltage of the third node is aligned with a voltage of the signal-transmitting end;
  • the first control module is connected to the third node, the fourth node, and the second clock signal end, and is configured to, under the control of the voltage of the third node, the voltage of the fourth node and the second The voltage at the clock signal terminal is aligned;
  • the second control module is connected to the fourth node, the first node, and the high level end, and is configured to, under the control of the voltage of the fourth node, the voltage of the first node and the high power Flat end voltage pulls;
  • the third control module is connected to the low level end, the third node and the second node, and is configured to, under the control of the voltage of the low level end, the voltage of the second node and the third The voltage of the node is aligned;
  • the output module is connected to the second node, the second clock signal end, and the output signal end, for controlling the second clock signal of the second clock signal end under the control of the voltage of the second node
  • the output signal terminal outputs
  • the reset module is connected to the first node, the high level end, and the output signal end, for controlling the voltage of the output signal end and the high level end under the control of the voltage of the first node Voltage pull
  • the input module includes: a first transistor and a second transistor;
  • the first end of the first transistor is connected to the low level end, the second end of the first transistor is connected to the first node, and the gate of the first transistor is connected to the first clock signal end;
  • the first end of the second transistor is connected to the signal transmitting end, the second end of the second transistor is connected to the third node, and the gate of the second transistor is connected to the first clock signal end;
  • the first control module includes: a third transistor
  • the first end of the third transistor is connected to the second clock signal end, the second end of the third transistor is connected to the fourth node, and the gate of the third transistor is connected to the third node.
  • the second control module includes: a fourth transistor and a first capacitor;
  • the first end of the fourth transistor is connected to the high level end, the second end of the fourth transistor is connected to the first node, and the gate of the fourth transistor is connected to the fourth node;
  • the first pole of the first capacitor is connected to the high level end, and the second pole of the first capacitor is connected to the fourth node.
  • the first capacitor is a tunable capacitor.
  • the third control module includes: a fifth transistor
  • the first end of the fifth transistor is connected to the third node, the second end of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to the low level end.
  • the output module includes: a sixth transistor and a third capacitor;
  • a first end of the sixth transistor is connected to the second clock signal end, a second end of the sixth transistor is connected to an output signal end, and a gate of the sixth transistor is connected to the second node;
  • the first pole of the third capacitor is connected to the second node, and the second pole of the third capacitor is connected to the output signal end.
  • the reset module includes: a seventh transistor and a second capacitor;
  • a first end of the seventh transistor is connected to the high level end, a second end of the seventh transistor is connected to the output signal end, and a gate of the seventh transistor is connected to the first node;
  • the first pole of the second capacitor is connected to the high level end, and the second pole of the second capacitor is connected to the first node.
  • the invention also provides a driving circuit, comprising: an input module, a first control module, a second control module, a third control module, an output module and a reset module;
  • the input module is connected to the level signal input end, the first clock signal end, the low level end, the first node and the third node, and is configured to be under the control of the first clock signal of the first clock signal end a voltage of the first node is aligned with a voltage of the low-level end, and a voltage of the third node is aligned with a voltage of the signal-transmitting end;
  • the first control module is connected to the third node, the fourth node, and the second clock signal end, and is configured to, under the control of the voltage of the third node, the voltage of the fourth node and the second The voltage at the clock signal terminal is aligned;
  • the second control module is connected to the fourth node, the first node, and the high level end, and is configured to, under the control of the voltage of the fourth node, the voltage of the first node and the high power Flat end voltage pulls;
  • the third control module is connected to the low level end, the third node and the second node, and is configured to, under the control of the voltage of the low level end, the voltage of the second node and the third The voltage of the node is aligned;
  • the first output module is connected to the second node, the second clock signal end, and the output signal end, for controlling the second clock of the second clock signal end under the control of the voltage of the second node a signal is output at the output signal end;
  • the reset module is connected to the first node, the high level end, and the output signal end, for controlling the voltage of the output signal end and the high level end under the control of the voltage of the first node The voltage is pulled.
  • the input module includes: a first transistor and a second transistor;
  • the first end of the first transistor is connected to the low level end, the second end of the first transistor is connected to the first node, and the gate of the first transistor is connected to the first clock signal end;
  • the first end of the second transistor is connected to the signal transmitting end, the second end of the second transistor is connected to the third node, and the gate of the second transistor is connected to the first clock signal end.
  • the first control module includes: a third transistor
  • the first end of the third transistor is connected to the second clock signal end, the second end of the third transistor is connected to the fourth node, and the gate of the third transistor is connected to the third node.
  • the second control module includes: a fourth transistor and a first capacitor;
  • the first end of the fourth transistor is connected to the high level end, the second end of the fourth transistor is connected to the first node, and the gate of the fourth transistor is connected to the fourth node;
  • the first pole of the first capacitor is connected to the high level end, and the second pole of the first capacitor is connected to the fourth node.
  • the first capacitor is a tunable capacitor.
  • the third control module includes: a fifth transistor
  • the first end of the fifth transistor is connected to the third node, the second end of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to the low level end.
  • the output module includes: a sixth transistor and a third capacitor;
  • a first end of the sixth transistor is connected to the second clock signal end, a second end of the sixth transistor is connected to an output signal end, and a gate of the sixth transistor is connected to the second node;
  • the first pole of the third capacitor is connected to the second node, and the second pole of the third capacitor is connected to the output signal end.
  • the reset module includes: a seventh transistor and a second capacitor;
  • a first end of the seventh transistor is connected to the high level end, a second end of the seventh transistor is connected to the output signal end, and a gate of the seventh transistor is connected to the first node;
  • the first pole of the second capacitor is connected to the high level end, and the second pole of the second capacitor is connected to the first node.
  • each of the transistors is a PMOS transistor.
  • the present invention also provides a driving circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a first Three capacitors;
  • the first end of the first transistor is connected to the low level end, the second end of the first transistor is connected to the first node, and the gate of the first transistor is connected to the first clock signal end;
  • the first end of the second transistor is connected to the signal transmitting end, the second end of the second transistor is connected to the third node, and the gate of the second transistor is connected to the first clock signal end;
  • the first end of the third transistor is connected to the second clock signal end, the second end of the third transistor is connected to the fourth node, and the gate of the third transistor is connected to the third node;
  • the first end of the fourth transistor is connected to the high level end, the second end of the fourth transistor is connected to the first node, and the gate of the fourth transistor is connected to the fourth node;
  • a first pole of the first capacitor is connected to the high level end, and a second pole of the first capacitor is connected to the fourth node;
  • the first end of the fifth transistor is connected to the third node, the second end of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to the low level end;
  • a first end of the sixth transistor is connected to the second clock signal end, a second end of the sixth transistor is connected to an output signal end, and a gate of the sixth transistor is connected to the second node;
  • a first pole of the third capacitor is connected to the second node, and a second pole of the third capacitor is connected to the output signal end;
  • a first end of the seventh transistor is connected to the high level end, a second end of the seventh transistor is connected to the output signal end, and a gate of the seventh transistor is connected to the first node;
  • the first pole of the second capacitor is connected to the high level end, and the second pole of the second capacitor is connected to the first node.
  • the invention has the beneficial effects that the driving circuit provided by the invention comprises an input module, a first control module, a second control module, a third control module, an output module and a reset module, which can ensure the normal operation of the liquid crystal display panel. , simplifying the structure of the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a driving timing diagram of a driving circuit provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention.
  • the transistors employed in all embodiments of the present invention may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present invention are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, the source is referred to as a first end, and the drain is referred to as a second end. According to the form in the drawing, the middle end of the transistor is the gate, the input signal terminal is the source, and the output signal terminal is the drain. In addition, the switching transistor used in the embodiment of the present invention is turned on when the gate is at a high level, and turned off when the gate is at a low level.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • an embodiment of the present invention provides a driving circuit, including: an input module 101, a first control module 102, a second control module 103, a third control module 104, an output module 105, and a reset module 106;
  • the input module 101 is connected to the level signal input terminal STV, the first clock signal terminal CK, the low level terminal VL, the first node A and the third node C for controlling the first clock signal of the first clock signal terminal CK. , the voltage of the first node A is aligned with the voltage of the low-level terminal VL, and the voltage of the third node C is aligned with the voltage of the signal-transmitting terminal;
  • the first control module 102 is connected to the third node C, the fourth node D, and the second clock signal terminal XCK for controlling the voltage of the fourth node D and the second clock signal terminal XCK under the control of the voltage of the third node C. Voltage pull
  • the second control module 103 is connected to the fourth node D, the first node A and the high level terminal VH for aligning the voltage of the first node A with the voltage of the high level terminal VH under the control of the voltage of the fourth node D. ;
  • the third control module 104 is connected to the low-level terminal VL, the third node C, and the second node B for aligning the voltage of the second node B with the voltage of the third node C under the control of the voltage of the low-level terminal VL. ;
  • the output module 105 is connected to the second node B, the second clock signal terminal XCK and the output signal terminal for controlling the second clock signal of the second clock signal terminal XCK at the output signal terminal under the control of the voltage of the second node B.
  • the reset module 106 is connected to the first node A, the high level terminal VH and the output signal terminal OUT for aligning the voltage of the output signal terminal OUT with the voltage of the high level terminal VH under the control of the voltage of the first node A.
  • multiple modules share one signal end (for example, the first control module 102 and the output module 105 share the second clock signal end XCK), which can reduce the number of signal terminals in the liquid crystal display panel.
  • the module can also be connected to different signal terminals, as long as the signal terminal can provide a similar signal.
  • FIG. 2 is a circuit diagram of a driving circuit according to an embodiment of the present invention.
  • the input module 101 includes: a first transistor T1 and a second transistor T2; a first end of the first transistor T1 is connected to the low-level terminal VL, and a second end of the first transistor T1 is connected to the first node A, and the first transistor T1
  • the gate of the second transistor T2 is connected to the signal transmitting terminal STV, the second terminal of the second transistor T2 is connected to the third node C, and the gate of the second transistor T2 is connected to the first terminal.
  • Clock signal terminal CK is a circuit diagram of a driving circuit according to an embodiment of the present invention.
  • the input module 101 includes: a first transistor T1 and a second transistor T2; a first end of the first transistor T1 is connected to the low-level terminal VL, and a second end of the first transistor T1 is connected to the first node A, and the first transistor T1
  • the gate of the second transistor T2 is connected
  • the first control module 102 includes: a third transistor T3; a first terminal of the third transistor T3 is connected to the second clock signal terminal XCK, a second terminal of the third transistor T3 is connected to the fourth node D, and a gate of the third transistor T3 is connected. Third node C.
  • the second control module 103 includes: a fourth transistor T4 and a first capacitor C1; a first end of the fourth transistor T4 is connected to the high level terminal VH, and a second end of the fourth transistor T4 is connected to the first node A, the fourth transistor T4 The gate is connected to the fourth node D; the first pole of the first capacitor C1 is connected to the high level terminal VH, and the second pole of the first capacitor C1 is connected to the fourth node D.
  • the first capacitor C1 is a tunable capacitor.
  • the third control module 104 includes: a fifth transistor T5; a first end of the fifth transistor T5 is connected to the third node C, a second end of the fifth transistor T5 is connected to the second node B, and a gate of the fifth transistor T5 is connected to the low battery Flat end VL.
  • the output module 105 includes: a sixth transistor T6 and a third capacitor C3; a first end of the sixth transistor T6 is connected to the second clock signal terminal XCK, and a second end of the sixth transistor T6 is connected to the output signal terminal OUT, and the sixth transistor T6 is The gate is connected to the second node B; the first pole of the third capacitor C3 is connected to the second node B, and the second pole of the third capacitor C3 is connected to the output signal terminal OUT.
  • the reset module 106 includes a seventh transistor T7 and a second capacitor C2.
  • the first end of the seventh transistor T7 is connected to the high level terminal VH, and the second end of the seventh transistor T7 is connected to the output signal terminal OUT, and the gate of the seventh transistor T7.
  • the first node A is connected; the first pole of the second capacitor C2 is connected to the high level terminal VH, and the second pole of the second capacitor C2 is connected to the first node A.
  • each of the transistors in the embodiment of the present invention is a PMOS transistor, that is, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh
  • the transistor T7 is a PMOS transistor, and the PMOS transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • FIG. 3 is a timing diagram of driving of a driving circuit according to an embodiment of the present invention.
  • the driving sequence of the driving circuit provided by the embodiment of the present invention includes: a first time period t1, a second time period t2, and a third time period t3.
  • the level signal of the level signal input terminal STV is a low level
  • the first clock signal of the first clock signal terminal CK is a low level
  • the second clock signal end is a second of a XCK signal.
  • the clock signal is at a high level
  • the first transistor T1 and the second transistor T2 are turned on, and the low level of the low-level terminal VL is transmitted to the first node A through the first transistor T1, and the voltage and the low-level end of the first node A are The voltage of the VL is pulled.
  • the low level of the level signal of the STV signal input terminal is transmitted to the third node C via the second transistor T2, and the voltage of the third node C and the voltage of the signal input terminal STV are transmitted.
  • the fifth transistor T5 is turned on by the low level of the low level terminal VL, so that the voltage of the second node B is aligned with the voltage of the third node C.
  • the level signal of the level signal input terminal STV is high level
  • the first clock signal of the first clock signal terminal CK is high level
  • the second clock signal of the second clock signal terminal XCK is Low level
  • the fifth transistor T5 is turned on under the action of the low level of the low level terminal VL, and at the same time, the voltage of the second node B and the third node C is kept low by the action of the third capacitor C3.
  • the sixth transistor T6 is connected to the second node B, so that the sixth transistor T6 is turned on, and the low level of the second clock signal of the second clock signal terminal XCK is output to the output signal terminal OUT via the sixth transistor T6;
  • the gate of the third transistor T3 is connected to the third node C, so that the third transistor T3 is turned on, the second clock signal of the second clock signal terminal XCK is transmitted to the fourth node D via the third transistor T3.
  • the fourth transistor T4 is turned on, and the high level of the high level terminal VH is transmitted to the first node A via the fourth transistor T4, thereby turning off the seventh transistor T7.
  • the level signal of the level signal input terminal STV is a high level
  • the first clock signal of the first clock signal terminal CK is a low level
  • the second clock signal of the second clock signal terminal XCK is a second clock signal.
  • the high level of the level signal of the level signal input terminal STV is transmitted to the third node C via the second transistor T2, and the fifth transistor T5 is guided by the low level of the low level terminal VL.
  • the third node C and the second node B are turned on, and the sixth transistor T6 is turned off.
  • the driving circuit provided by the embodiment of the invention can simplify the structure of the driving circuit under the premise of ensuring the normal operation of the liquid crystal display panel.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention. As shown in FIG. 4, the liquid crystal display panel includes at least two cascaded driving circuits.
  • the level signal input end of the first stage driving circuit is connected to the frame start signal end, and the output signal end of the first stage driving circuit is connected to the level signal input end of the second stage driving circuit; the level transmitting signal input of the nth stage driving circuit
  • the terminal is connected to the output signal end of the n-1th stage driving circuit, and the output signal end of the nth stage driving circuit is connected to the level signal input end of the n+1th stage driving circuit; wherein n is a positive integer.
  • the liquid crystal display panel comprises a plurality of cascaded driving circuits, wherein the level signal input end of the first stage driving circuit is connected to the frame start signal end, and the output signal end of the first level driving circuit is connected to the second level driving The level signal input end of the circuit and the gate line G1; the level signal input end of the second stage driving circuit is connected to the output signal end of the first stage driving circuit, and the output signal end of the second stage driving circuit is connected to the third stage driving circuit The signal input terminal and the gate line G2 are connected, and the other driving circuits of the liquid crystal display panel are connected in accordance with the second stage driving circuit.
  • Each of the driving circuits has a first clock signal terminal CK, a second clock signal terminal XCK, a high level terminal VH and a low level terminal VL.
  • the driving circuit provided by the invention can simplify the structure of the driving circuit under the premise of ensuring the normal operation of the liquid crystal display panel.

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Abstract

本发明提供一种驱动电路及液晶显示面板，包括输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块，能够在保证液晶显示面板正常工作的前提下，简化驱动电路结构。

Description

一种驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种驱动电路。
 背景技术
随着电子技术的发展，液晶显示面板的驱动电路越来越广泛的应用于显示设备，提高液晶显示面板的驱动电路的输出信号的可靠性变得越来越重要。然而，现有的液晶显示面板的驱动电路结构较为复杂。
 技术问题
本发明提供一种驱动电路，能够在保证液晶显示面板正常工作的前提下，简化驱动电路结构。
 技术解决方案
本发明提供一种驱动电路，其包括：输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块；
所述输入模块连接级传信号输入端、第一时钟信号端、低电平端、第一节点和第三节点，用于在所述第一时钟信号端的第一时钟信号的控制下，将所述第一节点的电压与所述低电平端的电压拉齐，以及将所述第三节点的电压与所述级传信号端的电压拉齐；
所述第一控制模块连接所述第三节点、第四节点和第二时钟信号端，用于在所述第三节点的电压的控制下，将所述第四节点的电压与所述第二时钟信号端的电压拉齐；
所述第二控制模块连接所述第四节点、所述第一节点和高电平端，用于在所述第四节点的电压的控制下，将所述第一节点的电压与所述高电平端的电压拉齐；
所述第三控制模块连接所述低电平端、所述第三节点和第二节点，用于在所述低电平端的电压的控制下，将所述第二节点的电压与所述第三节点的电压拉齐；
所述输出模块连接所述第二节点、所述第二时钟信号端和输出信号端，用于在所述第二节点的电压的控制下，将所述第二时钟信号端的第二时钟信号在所述输出信号端输出；
所述复位模块连接所述第一节点、所述高电平端和所述输出信号端，用于在所述第一节点的电压的控制下，将所述输出信号端的电压与所述高电平端的电压拉齐；
其中，所述输入模块包括：第一晶体管和第二晶体管；
所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端；
所述第一控制模块包括：第三晶体管；
所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点。
在本发明的驱动电路中，所述第二控制模块包括：第四晶体管和第一电容；
所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点。
在本发明的驱动电路中，所述第一电容为可调电容。
在本发明的驱动电路中，所述第三控制模块包括：第五晶体管；
所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端。
在本发明的驱动电路中，所述输出模块包括：第六晶体管和第三电容；
所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端。
在本发明的驱动电路中，所述复位模块包括：第七晶体管和第二电容；
所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
本发明还提供一种驱动电路，其包括：输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块；
所述输入模块连接级传信号输入端、第一时钟信号端、低电平端、第一节点和第三节点，用于在所述第一时钟信号端的第一时钟信号的控制下，将所述第一节点的电压与所述低电平端的电压拉齐，以及将所述第三节点的电压与所述级传信号端的电压拉齐；
所述第一控制模块连接所述第三节点、第四节点和第二时钟信号端，用于在所述第三节点的电压的控制下，将所述第四节点的电压与所述第二时钟信号端的电压拉齐；
所述第二控制模块连接所述第四节点、所述第一节点和高电平端，用于在所述第四节点的电压的控制下，将所述第一节点的电压与所述高电平端的电压拉齐；
所述第三控制模块连接所述低电平端、所述第三节点和第二节点，用于在所述低电平端的电压的控制下，将所述第二节点的电压与所述第三节点的电压拉齐；
所述第一输出模块连接所述第二节点、所述第二时钟信号端和输出信号端，用于在所述第二节点的电压的控制下，将所述第二时钟信号端的第二时钟信号在所述输出信号端输出；
所述复位模块连接所述第一节点、所述高电平端和所述输出信号端，用于在所述第一节点的电压的控制下，将所述输出信号端的电压与所述高电平端的电压拉齐。
在本发明的驱动电路中，所述输入模块包括：第一晶体管和第二晶体管；
所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端。
在本发明的驱动电路中，所述第一控制模块包括：第三晶体管；
所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点。
在本发明的驱动电路中，所述第二控制模块包括：第四晶体管和第一电容；
所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点。
在本发明的驱动电路中，所述第一电容为可调电容。
在本发明的驱动电路中，所述第三控制模块包括：第五晶体管；
所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端。
在本发明的驱动电路中，所述输出模块包括：第六晶体管和第三电容；
所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端。
在本发明的驱动电路中，所述复位模块包括：第七晶体管和第二电容；
所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
在本发明的驱动电路中，各个晶体管均为为PMOS管。
本发明还提供.一种驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容和第三电容；
所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端；
所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点；
所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点；
所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端；
所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端；
所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
 有益效果
本发明的有益效果为：本发明提供的驱动电路，包括输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块，能够在保证液晶显示面板正常工作的前提下，简化液晶显示面板结构。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的驱动电路的示意性结构图；
图2为本发明实施例提供的驱动电路的电路图；
图3为本发明实施提供的驱动电路的驱动时序图；
图4为本发明实施例提供的液晶显示面板的结构示意图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一端，漏极称为第二端。按附图中的形态规定晶体管的中间端为栅极、输入信号端为源极、输出信号端为漏极。此外本发明实施例所采用的开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
需要说明的是，需要说明的是，本申请中的“第一”、“第二”等字样仅仅是为了对功能和作用基本相同的相同项或相似项进行区分，“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
请参阅图1，图1为本发明实施例提供的驱动电路的示意性结构图。如图1所示，本发明实施例提供一种驱动电路，其包括：输入模块101、第一控制模块102、第二控制模块103、第三控制模块104、输出模块105和复位模块106；
输入模块101连接级传信号输入端STV、第一时钟信号端CK、低电平端VL、第一节点A和第三节点C，用于在第一时钟信号端CK的第一时钟信号的控制下，将第一节点A的电压与低电平端VL的电压拉齐，以及将第三节点C的电压与级传信号端的电压拉齐；
第一控制模块102连接第三节点C、第四节点D和第二时钟信号端XCK，用于在第三节点C的电压的控制下，将第四节点D的电压与第二时钟信号端XCK的电压拉齐；
第二控制模块103连接第四节点D、第一节点A和高电平端VH，用于在第四节点D的电压的控制下，将第一节点A的电压与高电平端VH的电压拉齐；
第三控制模块104连接低电平端VL、第三节点C和第二节点B，用于在低电平端VL的电压的控制下，将第二节点B的电压与第三节点C的电压拉齐；
输出模块105连接第二节点B、第二时钟信号端XCK和输出信号端，用于在第二节点B的电压的控制下，将第二时钟信号端XCK的第二时钟信号在输出信号端OUT输出；
复位模块106连接第一节点A、高电平端VH和输出信号端OUT，用于在第一节点A的电压的控制下，将输出信号端OUT的电压与高电平端VH的电压拉齐。
需要说明的是，上述实施例中，多个模块共用一个信号端(例如：第一控制模块102和输出模块105共用第二时钟信号端XCK )可以减少液晶显示面板中信号端的数量，当然，这些模块还可以分别连接不同的信号端，只要该信号端可以提供类似的信号即可。
请参阅图2，图2为本发明实施例提供的驱动电路的电路图。具体的，输入模块101包括：第一晶体管T1和第二晶体管T2；第一晶体管T1的第一端连接低电平端VL，第一晶体管T1的第二端连接第一节点A，第一晶体管T1的栅极连接第一时钟信号端CK；第二晶体管T2的第一端连接级传信号端STV，第二晶体管T2的第二端连接第三节点C，第二晶体管T2的栅极连接第一时钟信号端CK。
第一控制模块102包括：第三晶体管T3；第三晶体管T3的第一端连接第二时钟信号端XCK，第三晶体管T3的第二端连接第四节点D，第三晶体管T3的栅极连接第三节点C。
第二控制模块103包括：第四晶体管T4和第一电容C1；第四晶体管T4的第一端连接高电平端VH，第四晶体管T4的第二端连接第一节点A，第四晶体管T4的栅极连接第四节点D；第一电容C1的第一极连接高电平端VH，第一电容C1的第二极连接第四节点D。其中，该第一电容C1为可调电容。
第三控制模块104包括：第五晶体管T5；第五晶体管T5的第一端连接第三节点C，第五晶体管T5的第二端连接第二节点B，第五晶体管T5的栅极连接低电平端VL。
输出模块105包括：第六晶体管T6和第三电容C3；第六晶体管T6的第一端连接第二时钟信号端XCK，第六晶体管T6的第二端连接输出信号端OUT，第六晶体管T6的栅极连接第二节点B；第三电容C3的第一极连接第二节点B，第三电容C3的第二极连接输出信号端OUT。
复位模块106包括：第七晶体管T7和第二电容C2；第七晶体管T7的第一端连接高电平端VH，第七晶体管T7的第二端连接输出信号端OUT，第七晶体管T7的栅极连接第一节点A；第二电容C2的第一极连接高电平端VH，第二电容C2的第二极连接第一节点A。
进一步的，本发明实施例中的各个晶体管均为为PMOS管，即第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均为PMOS管，PMOS管在栅极为低电平时导通，在栅极为高电平时截止。
请参阅图3，图3为本发明实施提供的驱动电路的驱动时序图。如图3所示，本发明实施例提供的驱动电路的驱动时序包括：第一时间段t1、第二时间段t2和第三时间段t3。
具体的，在第一时间段t1，级传信号输入端STV的级传信号为低电平，第一时钟信号端CK的第一时钟信号为低电平，第二时钟信号端XCK的第二时钟信号为高电平，第一晶体管T1和第二晶体管T2导通，低电平端VL的低电平经第一晶体管T1传至第一节点A，将第一节点A的电压与低电平端VL的电压拉齐；同时，级传信号输入端STV的级传信号的低电平经第二晶体管T2传至第三节点C，将第三节点C的电压与级传信号输入端STV的电压拉齐，另外第五晶体管T5在低电平端VL的低电平的作用下处于导通，从而使第二节点B的电压与第三节点C的电压拉齐。
在第二时间段t2，级传信号输入端STV的级传信号为高电平，第一时钟信号端CK的第一时钟信号为高电平，第二时钟信号端XCK的第二时钟信号为低电平，另外第五晶体管T5在低电平端VL的低电平的作用下处于导通，同时在第三电容C3的作用下，使得第二节点B和第三节点C的电压保持低电位，由于第六晶体管T6的栅极连接第二节点B，从而第六晶体管T6导通，第二时钟信号端XCK的第二时钟信号的低电平经第六晶体管T6输出至输出信号端OUT；
与此此时，由于第三晶体管T3的栅极连接第三节点C，从而第三晶体管T3导通，第二时钟信号端XCK的第二时钟信号经第三晶体管T3传至第四节点D，使得第四晶体管T4导通，高电平端VH的高电平经第四晶体管T4传至第一节点A，从而使得第七晶体管T7截止。
在第三时间段t3，级传信号输入端STV的级传信号为高电平，第一时钟信号端CK的第一时钟信号为低电平，第二时钟信号端XCK的第二时钟信号为高电平，第一晶体管T1导通，低电平端VL的低电平经第一晶体管T1传至第一节点A，使得第七晶体管T7导通，高电平端VH的高电平经第七晶体管T7传至输出信号端OUT；
与此同时，级传信号输入端STV的级传信号的高电平经第二晶体管T2传至第三节点C，另外由于第五晶体管T5在低电平端VL的低电平的作用下处于导通，第三节点C与第二节点B导通，第六晶体管T6截止。
本发明实施例提供的驱动电路，能够在保证液晶显示面板正常工作的前提下，简化驱动电路结构。
请参阅图4，图4为本发明实施例提供的液晶显示面板的结构示意图。如图4所示，该液晶显示面板包括至少两个级联的驱动电路。
第1级驱动电路的级传信号输入端连接帧起始信号端，第1级驱动电路的输出信号端连接第2级驱动电路的级传信号输入端；第n级驱动电路的级传信号输入端连接第n-1级驱动电路的输出信号端，第n级驱动电路的输出信号端连接第n+1级驱动电路的级传信号输入端；其中，n为正整数。
具体的，该液晶显示面板包括若干个级联的驱动电路，其中，第1级驱动电路的级传信号输入端连接帧起始信号端，第1级驱动电路的输出信号端连接第2级驱动电路的级传信号输入端和栅线G1；第2级驱动电路的级传信号输入端连接第1级驱动电路的输出信号端，第2级驱动电路的输出信号端连接第3级驱动电路的级传信号输入端和栅线G2，该液晶显示面板的其他的驱动电路依照第2级驱动电路的方式连接。
每个驱动电路都有一个第一时钟信号端CK、一个第二时钟信号端XCK、一个高电平端VH和一个低电平端VL。
本发明提供的驱动电路，能够在保证液晶显示面板正常工作的前提下，简化驱动电路结构。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种驱动电路，其包括：输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块；
    所述输入模块连接级传信号输入端、第一时钟信号端、低电平端、第一节点和第三节点，用于在所述第一时钟信号端的第一时钟信号的控制下，将所述第一节点的电压与所述低电平端的电压拉齐，以及将所述第三节点的电压与所述级传信号端的电压拉齐；
    所述第一控制模块连接所述第三节点、第四节点和第二时钟信号端，用于在所述第三节点的电压的控制下，将所述第四节点的电压与所述第二时钟信号端的电压拉齐；
    所述第二控制模块连接所述第四节点、所述第一节点和高电平端，用于在所述第四节点的电压的控制下，将所述第一节点的电压与所述高电平端的电压拉齐；
    所述第三控制模块连接所述低电平端、所述第三节点和第二节点，用于在所述低电平端的电压的控制下，将所述第二节点的电压与所述第三节点的电压拉齐；
    所述输出模块连接所述第二节点、所述第二时钟信号端和输出信号端，用于在所述第二节点的电压的控制下，将所述第二时钟信号端的第二时钟信号在所述输出信号端输出；
    所述复位模块连接所述第一节点、所述高电平端和所述输出信号端，用于在所述第一节点的电压的控制下，将所述输出信号端的电压与所述高电平端的电压拉齐；
    其中，所述输入模块包括：第一晶体管和第二晶体管；
    所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
    所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端；
    所述第一控制模块包括：第三晶体管；
    所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点。
  2. 根据权利要求1所述的驱动电路，其中，所述第二控制模块包括：第四晶体管和第一电容；
    所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
    所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点。
  3. 根据权利要求2所述的驱动电路，其中，所述第一电容为可调电容。
  4. 根据权利要求1所述的驱动电路，其中，所述第三控制模块包括：第五晶体管；
    所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端。
  5. 根据权利要求1所述的驱动电路，其中，所述输出模块包括：第六晶体管和第三电容；
    所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
    所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端。
  6. 根据权利要求1所述的驱动电路，其中，所述复位模块包括：第七晶体管和第二电容；
    所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
    所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
  7. 一种驱动电路，其包括：输入模块、第一控制模块、第二控制模块、第三控制模块、输出模块和复位模块；
    所述输入模块连接级传信号输入端、第一时钟信号端、低电平端、第一节点和第三节点，用于在所述第一时钟信号端的第一时钟信号的控制下，将所述第一节点的电压与所述低电平端的电压拉齐，以及将所述第三节点的电压与所述级传信号端的电压拉齐；
    所述第一控制模块连接所述第三节点、第四节点和第二时钟信号端，用于在所述第三节点的电压的控制下，将所述第四节点的电压与所述第二时钟信号端的电压拉齐；
    所述第二控制模块连接所述第四节点、所述第一节点和高电平端，用于在所述第四节点的电压的控制下，将所述第一节点的电压与所述高电平端的电压拉齐；
    所述第三控制模块连接所述低电平端、所述第三节点和第二节点，用于在所述低电平端的电压的控制下，将所述第二节点的电压与所述第三节点的电压拉齐；
    所述输出模块连接所述第二节点、所述第二时钟信号端和输出信号端，用于在所述第二节点的电压的控制下，将所述第二时钟信号端的第二时钟信号在所述输出信号端输出；
    所述复位模块连接所述第一节点、所述高电平端和所述输出信号端，用于在所述第一节点的电压的控制下，将所述输出信号端的电压与所述高电平端的电压拉齐。
  8. 根据权利要求7所述的驱动电路，其中，所述输入模块包括：第一晶体管和第二晶体管；
    所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
    所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端。
  9. 根据权利要求7所述的驱动电路，其中，所述第一控制模块包括：第三晶体管；
    所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点。
  10. 根据权利要求7所述的驱动电路，其中，所述第二控制模块包括：第四晶体管和第一电容；
    所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
    所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点。
  11. 根据权利要求10所述的驱动电路，其中，所述第一电容为可调电容。
  12. 根据权利要求7所述的驱动电路，其中，所述第三控制模块包括：第五晶体管；
    所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端。
  13. 根据权利要求7所述的驱动电路，其中，所述输出模块包括：第六晶体管和第三电容；
    所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
    所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端。
  14. 根据权利要求7所述的驱动电路，其中，所述复位模块包括：第七晶体管和第二电容；
    所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
    所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
  15. 一种驱动电路，其包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容、第二电容和第三电容；
    所述第一晶体管的第一端连接低电平端，所述第一晶体管的第二端连接第一节点，所述第一晶体管的栅极连接第一时钟信号端；
    所述第二晶体管的第一端连接级传信号端，所述第二晶体管的第二端连接第三节点，所述第二晶体管的栅极连接所述第一时钟信号端；
    所述第三晶体管的第一端连接第二时钟信号端，所述第三晶体管的第二端连接第四节点，所述第三晶体管的栅极连接所述第三节点；
    所述第四晶体管的第一端连接高电平端，所述第四晶体管的第二端连接所述第一节点，所述第四晶体管的栅极连接所述第四节点；
    所述第一电容的第一极连接所述高电平端，所述第一电容的第二极连接所述第四节点；
    所述第五晶体管的第一端连接所述第三节点，所述第五晶体管的第二端连接第二节点，所述第五晶体管的栅极连接所述低电平端；
    所述第六晶体管的第一端连接所述第二时钟信号端，所述第六晶体管的第二端连接输出信号端，所述第六晶体管的栅极连接所述第二节点；
    所述第三电容的第一极连接所述第二节点，所述第三电容的第二极连接所述输出信号端；
    所述第七晶体管的第一端连接所述高电平端，所述第七晶体管的第二端连接所述输出信号端，所述第七晶体管的栅极连接所述第一节点；
    所述第二电容的第一极连接所述高电平端，所述第二电容的第二极连接所述第一节点。
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