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WO2017000852A1 - 一种晶圆级扇出封装的制作方法 - Google Patents

一种晶圆级扇出封装的制作方法 Download PDF

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Publication number
WO2017000852A1
WO2017000852A1 PCT/CN2016/087232 CN2016087232W WO2017000852A1 WO 2017000852 A1 WO2017000852 A1 WO 2017000852A1 CN 2016087232 W CN2016087232 W CN 2016087232W WO 2017000852 A1 WO2017000852 A1 WO 2017000852A1
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chip
layer
substrate
fabricating
wafer level
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PCT/CN2016/087232
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English (en)
French (fr)
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姜峰
陆原
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2017000852A1 publication Critical patent/WO2017000852A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1017—Shape being a sphere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the invention discloses a method for fabricating a wafer level fan-out package, and the invention belongs to the technical field of microelectronic package.
  • Fan-out WLP is the next-generation platform that supports future integration, especially for wireless devices.
  • the object of the present invention is to overcome the deficiencies in the prior art and provide a wafer level package structure. Packaging method.
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip is fixed at a set position by an adhesive containing the same area as the chip, and the input and output end of the chip faces upward;
  • the layer of plastic sealing material encapsulates the chip, and the input and output ends of the chip are exposed;
  • the material of the substrate is silicon, ceramic, sapphire or glass material, and the thickness of the substrate is 100 um - 1 mm.
  • the binder is made of a liquid or film-like material mainly composed of an epoxy resin or a silica material, and the binder has a thickness of 5 um to 50 um.
  • the material of the plastic sealing material layer is a resin mainly composed of epoxy resin, and the thickness of the plastic sealing material layer is flush with the upper surface of the chip.
  • the layer of molding material is completed by a conventional filling process, a spraying process, a lamination process or a printing process.
  • the dielectric layer is made of silicon dioxide, phenol resin or polyimide, and the dielectric layer has a thickness of 1 um to 20 ⁇ m.
  • the lead wires are formed by conventional electroplating, printing or deposition processes.
  • step c the upper surface of the dielectric layer is covered with a protective layer.
  • the protective layer is made of silica, silicon nitride, phenol resin or polyimide, and the protective layer has a thickness of 2 um to 20 ⁇ m.
  • the packaging method of the invention can greatly reduce the process steps of the fan-out packaging process, greatly reduce the packaging cost, avoid the use of temporary bonding and debonding processes, and fix the chip on the substrate through the adhesive.
  • the position of the chip is fixed after being attached to the substrate, the patch precision is high, and the reliability of the package is ensured.
  • FIG. 1 is a schematic view showing the structure of a package obtained in the step a of the present invention.
  • FIG. 2 is a schematic view showing the structure of a package obtained in the step b of the present invention.
  • Figure 3 is a schematic view showing the structure of the package obtained in the step c of the present invention.
  • Figure 4 is a schematic view showing the structure of the package obtained in the step d of the present invention.
  • Figure 5 is a schematic view showing the structure of the package obtained in the step e of the present invention.
  • Figure 6 is a schematic view showing the structure of the package obtained in the step f of the present invention.
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is silicon and the thickness is 100 um, and the material of the adhesive 7 is epoxy resin and thickness. 5um, as shown in Figure 1;
  • a conventional filling process on the upper surface of the substrate 6 forms a layer of the molding material 2
  • the layer of the molding material 2 encapsulates the chip 1, the input and output ends of the chip 1 are exposed, and the material of the layer 2 of the molding material is a resin mainly composed of epoxy resin. ,as shown in picture 2;
  • the dielectric layer 4 is made of silicon dioxide and having a thickness of 1 um, and the upper surface of the dielectric layer 4 is covered with a protective layer.
  • the protective layer 5 is made of silicon dioxide and has a thickness of 2 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, and the input and output ends of the chip 1 are facing
  • the material of the substrate 6 is ceramic and the thickness is 400 um
  • the material of the adhesive 7 is a liquid material mainly composed of silica material and has a thickness of 20 ⁇ m, as shown in FIG. 1;
  • the dielectric layer 4 is made of a phenol resin and having a thickness of 5 ⁇ m, and the upper surface of the dielectric layer 4 is covered with a protective layer 5
  • the protective layer 5 is made of silicon nitride and has a thickness of 5 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is sapphire and the thickness is 700 um, and the material of the adhesive 7 is made of silicon dioxide.
  • the main film material and thickness is 40um, as shown in Figure 1;
  • the dielectric layer 4 is made of polyimide and has a thickness of 15 um, and the upper surface of the dielectric layer 4 is covered with a layer of protection.
  • Layer 5 the protective layer 5 is made of phenol resin and has a thickness of 15 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is glass material and the thickness is 1 mm, and the material of the adhesive 7 is silica material. a predominantly membranous substance with a thickness of 50 um, as shown in Figure 1;
  • the dielectric layer 4 is made of polyimide and has a thickness of 20 um, and the upper surface of the dielectric layer 4 is covered with a layer of protection.
  • Layer 5 the material of the protective layer 5 is polyimide and the thickness is 20um, as shown in FIG. 3;

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种晶圆级扇出封装的制作方法，它包括以下步骤：在基板(6)的上表面通过粘结剂(7)贴装芯片(1)；在基板(6)的上表面进行塑封成型，塑封材料层(2)将芯片(1)封装；在塑封材料层(2)的上表面涂上介电材料，形成介电层(4)；去除对应芯片(1)的输入输出端位置的介电层(4)，再在去除部位形成引出线(3)和焊球(8)；沿着基板(6)的下表面进行减薄，将基板(6)、粘结剂(7)以及部分的塑封材料层(2)和芯片(1)的下表面去除，最终磨削面停留在芯片(1)的设定位置形成封装半成品；在封装半成品上沿着相邻两个芯片(1)之间的切割线将封装半成品切割成单个封装结构。能够极大地减少扇出式封装制程的工艺步骤，极大的减少了其封装成本，同时保证了封装的可靠性。

Description

一种晶圆级扇出封装的制作方法 技术领域
本发明公开了一种晶圆级扇出封装的制作方法，本发明属于微电子封装的技术领域。
背景技术
随着人们对电子产品的要求向小型化、多功能、环保型等方向的发展，人们努力寻求将电子系统越做越小，集成度越来越高，功能越做越多、越来越强，由此产生了许多新技术、新材料和新设计，其中扇出型封装技术就是这些技术的典型代表。
作为广泛应用的单颗芯片封装技术，传统封装目前已经逐渐呈现出封装效率低下和成本持续攀升的弊端。圆片级封装作为一种新型的封装方式，因能够较大地减少芯片封装尺寸，而被业界广泛采用。现有的BGA封装技术受到有机基板性能的限制。向扇出WLP的转移有助于克服这些限制，且能简化供应链。扇出WLP的主要优点是能很好地控制翘曲，这就能实现高装配良率。在封装自身上建立基板允许在较少的金属层中实现较高的集成和布线密度。扇出WLP是支撑未来集成(特别是对于无线器件)的下一代平台。
扇出WLP结构最著名的例子之一是由英飞凌公司(Infineon Technologies AG)开发的eWLB技术。该技术采用前后道制造技术结合并行加工晶圆上的全部芯片，能大大降低制造成本。其优点是：与常规的引线框架或叠层封装比较，封装面积较小、I/O数量从中等到高、连接密度最大化、以及能获得所需的电学和热性能。它也能为无线市场提供高性能和节能的解决方法。但是其缺点也比较明显，在其工艺技术设计时，只考虑了芯片功能面朝下的工艺方式，这个应用就很大程度上限制了功能面朝上的产品；另外该技术需要应用到临时键合和拆键合的工艺，所以在最终的扇出封装的成本计算上也有很大的难度，直接导致了该封装技术生产的成本高昂。
对扇出式封装技术研究仍在继续，由于这些工艺的方法的多种不利因素，对产品的成品率和可靠性，以及最终出货价格都造成极大的影响。各种新的封装结构和特殊工艺方法也逐步被提出和讨论。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种晶圆级封装结构 的封装方法。
按照本发明提供的技术方案，一种晶圆级扇出封装的制作方法包括以下步骤：
a、在基板的上表面将芯片通过含有与芯片同等面积的粘结剂固定在设定位置，芯片的输入输出端朝上；
b、在基板的上表面形成塑封材料层，塑封材料层将芯片封装，芯片的输入输出端露出；
c、在塑封材料层的上表面涂上介电材料，形成介电层；
d、去除对应芯片的输入输出端位置上方的介电层，再在去除部位形成引出线和焊球，引出线的一端与芯片的输入输出端相连；
e、沿着基板的下表面进行减薄，将基板、粘结剂以及部分的塑封材料层和芯片的下表面去除，最终磨削面停留在芯片的设定位置形成封装半成品；
f、在封装半成品上沿着相邻两个芯片之间的切割线将封装半成品切割成单个封装结构。
作为优选：所述基板的材质为硅、陶瓷、蓝宝石或者玻璃材料，且基板的厚度为100um-1mm。
作为优选：所述粘结剂的材质为环氧树脂或者二氧化硅材料为主的液状或者膜状物质，且粘结剂的厚度为5um-50um。
作为优选：所述塑封材料层的材质是由环氧树脂为主体的树脂，且塑封材料层的厚度与芯片上表面齐平。
作为优选：所述塑封材料层通过常规的填充工艺、喷涂工艺、压膜工艺或者印刷工艺完成。
作为优选：所述介电层的材质为二氧化硅、酚树脂或者聚酰亚胺，且介电层的厚度为1um-20um。
作为优选：所述引出线通过常规的电镀、印刷或者沉积工艺形成。
作为优选：步骤c中，在介电层的上表面覆盖一层保护层。
作为优选：所述保护层的材质二氧化硅、氮化硅、酚树脂或者聚酰亚胺，保护层的厚度为2um-20um。
本发明的封装方法能够极大地减少扇出式封装制程的工艺步骤，极大的减少了其封装成本支出，避免使用临时键合和拆键合工艺，而将芯片通过粘结剂固定在基板上，保证了芯片贴到基板上后位置固定，贴片精度高，同时保证了封装的可靠性。
附图说明
图1是本发明步骤a得到的封装体的结构示意图。
图2是本发明步骤b得到的封装体的结构示意图。
图3是本发明步骤c得到的封装体的结构示意图。
图4是本发明步骤d得到的封装体的结构示意图。
图5是本发明步骤e得到的封装体的结构示意图。
图6是本发明步骤f得到的封装体的结构示意图。
具体实施方式
下面结合具体实施例对本发明作进一步说明。
实施例1
一种晶圆级扇出封装的制作方法包括以下步骤：
a、在基板6的上表面通过粘结剂7贴装芯片1，芯片1的输入输出端朝上，基板6的材质为硅且厚度为100um，粘结剂7的材质为环氧树脂且厚度为5um，如图1所示；
b、在基板6的上表面常规的填充工艺形成塑封材料层2，塑封材料层2将芯片1封装，芯片1的输入输出端露出，塑封材料层2的材质是由环氧树脂为主体的树脂，如图2所示；
c、在塑封材料层2的上表面涂上介电材料，形成介电层4，介电层4的材质为二氧化硅且厚度为1um，在介电层4的上表面覆盖一层保护层5，保护层5的材质为二氧化硅且厚度为2um，如图3所示；
d、去除对应芯片1的输入输出端位置的介电层4，再在去除部位采用常规的电镀工艺形成引出线3和焊球8，引出线3的一端与芯片1的输入输出端相连，如图4所示；
e、沿着基板6的下表面进行减薄，将基板6、粘结剂7以及部分的塑封材料层2和芯片1的下表面去除，最终磨削面停留在芯片1的设定位置形成封装半成品，如图5所示；
f、在封装半成品上沿着相邻两个芯片1之间的切割线将封装半成品切割成单个封装结构，如图6所示。
实施例2
一种晶圆级扇出封装的制作方法包括以下步骤：
a、在基板6的上表面通过粘结剂7贴装芯片1，芯片1的输入输出端朝 上，基板6的材质为陶瓷且厚度为400um，粘结剂7的材质为二氧化硅材料为主的液状物质且厚度为20um，如图1所示；
b、在基板6的上表面通过常规的喷涂工艺形成塑封材料层2，塑封材料层2将芯片1封装，芯片1的输入输出端露出，如图2所示；
c、在塑封材料层2的上表面涂上介电材料，形成介电层4，介电层4的材质为酚树脂且厚度为5um，在介电层4的上表面覆盖一层保护层5，保护层5的材质为氮化硅且厚度为5um，如图3所示；
d、去除对应芯片1的输入输出端位置的介电层4，再在去除部位采用常规的沉积工艺形成引出线3和焊球8，引出线3的一端与芯片1的输入输出端相连，如图4所示；
e、沿着基板6的下表面进行减薄，将基板6、粘结剂7以及部分的塑封材料层2和芯片1的下表面去除，最终磨削面停留在芯片1的设定位置形成封装半成品，如图5所示；
f、在封装半成品上沿着相邻两个芯片1之间的切割线将封装半成品切割成单个封装结构，如图6所示。
实施例3
一种晶圆级扇出封装的制作方法包括以下步骤：
a、在基板6的上表面通过粘结剂7贴装芯片1，芯片1的输入输出端朝上，基板6的材质为蓝宝石且厚度为700um，粘结剂7的材质为二氧化硅材料为主的膜状物质且厚度为40um，如图1所示；
b、在基板6的上表面通过常规的压膜工艺形成塑封材料层2，塑封材料层2将芯片1封装，芯片1的输入输出端露出，如图2所示；
c、在塑封材料层2的上表面涂上介电材料，形成介电层4，介电层4的材质为聚酰亚胺且厚度为15um，在介电层4的上表面覆盖一层保护层5，保护层5的材质为酚树脂且厚度为15um，如图3所示；
d、去除对应芯片1的输入输出端位置的介电层4，再在去除部位采用常规的印刷工艺形成引出线3和焊球8，引出线3的一端与芯片1的输入输出端相连，如图4所示；
e、沿着基板6的下表面进行减薄，将基板6、粘结剂7以及部分的塑封材料层2和芯片1的下表面去除，最终磨削面停留在芯片1的设定位置形成封装半成品，如图5所示；
f、在封装半成品上沿着相邻两个芯片1之间的切割线将封装半成品切割成单个封装结构，如图6所示。
实施例4
一种晶圆级扇出封装的制作方法包括以下步骤：
a、在基板6的上表面通过粘结剂7贴装芯片1，芯片1的输入输出端朝上，基板6的材质为玻璃材料且厚度为1mm，粘结剂7的材质为二氧化硅材料为主的膜状物质且厚度为50um，如图1所示；
b、在基板6的上表面通过常规的印刷工艺形成塑封材料层2，塑封材料层2将芯片1封装，芯片1的输入输出端露出，如图2所示；
c、在塑封材料层2的上表面涂上介电材料，形成介电层4，介电层4的材质为聚酰亚胺且厚度为20um，在介电层4的上表面覆盖一层保护层5，保护层5的材质为聚酰亚胺且厚度为20um，如图3所示；
d、去除对应芯片1的输入输出端位置的介电层4，再在去除部位采用常规的印刷工艺形成引出线3和焊球8，引出线3的一端与芯片1的输入输出端相连，如图4所示；
f、沿着基板6的下表面进行减薄，将基板6、粘结剂7以及部分的塑封材料层2和芯片1的下表面去除，最终磨削面停留在芯片1的设定位置形成封装半成品，如图5所示；
g、在封装半成品上沿着相邻两个芯片1之间的切割线将封装半成品切割成单个封装结构，如图6所示。

Claims (9)

  1. 一种晶圆级扇出封装的制作方法，其特征是该封装方法包括以下步骤：
    a、在基板(6)的上表面将芯片(1)通过含有与芯片(1)同等面积的粘结剂(7)固定在设定位置，芯片(1)的输入输出端朝上；
    b、在基板(6)的上表面形成塑封材料层(2)，塑封材料层(2)将芯片(1)封装，芯片(1)的输入输出端露出；
    c、在塑封材料层(2)的上表面涂上介电材料，形成介电层(4)；
    d、去除对应芯片(1)的输入输出端位置上方的介电层(4)，再在去除部位形成引出线(3)和焊球(8)，引出线(3)的一端与芯片(1)的输入输出端相连；
    e、沿着基板(6)的下表面进行减薄，将基板(6)、粘结剂(7)以及部分的塑封材料层(2)和芯片(1)的下表面去除，最终磨削面停留在芯片(1)的设定位置形成封装半成品；
    f、在封装半成品上沿着相邻两个芯片(1)之间的切割线将封装半成品切割成单个封装结构。
  2. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述基板(6)的材质为硅、陶瓷、蓝宝石或者玻璃材料，且基板(6)的厚度为100um-1mm。
  3. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述粘结剂(7)的材质为环氧树脂或者二氧化硅材料为主的液状或者膜状物质，且粘结剂(7)的厚度为5um-50um。
  4. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述塑封材料层(2)的材质是由环氧树脂为主体的树脂，且塑封材料层(2)的厚度与芯片上表面齐平。
  5. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述塑封材料层(2)通过常规的填充工艺、喷涂工艺、压膜工艺或者印刷工艺完成。
  6. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述介电层(4)的材质为二氧化硅、酚树脂或者聚酰亚胺，且介电层(4)的厚度为1um-20um。
  7. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：所述引出线(3)通过常规的电镀、印刷或者沉积工艺形成。
  8. 根据权利要求1所述的一种晶圆级扇出封装的制作方法，其特征是：步骤c中，在介电层(4)的上表面覆盖一层保护层(5)。
  9. 根据权利要求8所述的一种晶圆级扇出封装的制作方法，其特征是：所述保护层(5)的材质为二氧化硅、氮化硅、酚树脂或者聚酰亚胺，保护层(5)的厚度为2um-20um。
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CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法
CN106876291B (zh) * 2016-12-30 2020-04-10 清华大学 一种薄芯片柔性扇出封装方法及所制备的封装结构
CN107300807A (zh) * 2017-06-01 2017-10-27 武汉华星光电技术有限公司 一种光学元件、液晶显示模组及蛾眼微结构的制备方法
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108108681A (zh) * 2017-12-14 2018-06-01 江西合力泰科技有限公司 具有高抵抗外力能力的生物识别模组及其制备方法
CN108321215B (zh) * 2018-03-07 2024-09-13 苏州晶方半导体科技股份有限公司 光学指纹识别芯片的封装结构及其制作方法
CN109659278A (zh) * 2018-12-26 2019-04-19 合肥矽迈微电子科技有限公司 多芯片堆叠封装方法及多芯片堆叠封装体
CN111128918B (zh) * 2019-12-31 2021-10-26 山东盛品电子技术有限公司 一种芯片封装方法及芯片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887251A (zh) * 2014-04-02 2014-06-25 华进半导体封装先导技术研发中心有限公司 扇出型晶圆级封装结构及制造工艺
CN104538375A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种扇出PoP封装结构及其制造方法
CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI364793B (en) * 2007-05-08 2012-05-21 Mutual Pak Technology Co Ltd Package structure for integrated circuit device and method of the same
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
CN202003990U (zh) * 2011-01-31 2011-10-05 江阴长电先进封装有限公司 低成本芯片扇出结构
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887251A (zh) * 2014-04-02 2014-06-25 华进半导体封装先导技术研发中心有限公司 扇出型晶圆级封装结构及制造工艺
CN104538375A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种扇出PoP封装结构及其制造方法
CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法

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