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WO2009153129A3 - Verfahren zur herstellung einer elektronischen baugruppe - Google Patents

Verfahren zur herstellung einer elektronischen baugruppe Download PDF

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Publication number
WO2009153129A3
WO2009153129A3 PCT/EP2009/056286 EP2009056286W WO2009153129A3 WO 2009153129 A3 WO2009153129 A3 WO 2009153129A3 EP 2009056286 W EP2009056286 W EP 2009056286W WO 2009153129 A3 WO2009153129 A3 WO 2009153129A3
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
manufacture
fitted
electronic assembly
conductor track
Prior art date
Application number
PCT/EP2009/056286
Other languages
English (en)
French (fr)
Other versions
WO2009153129A2 (de
Inventor
Ulrich Schaaf
Andreas Kugler
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to EP09765709A priority Critical patent/EP2289100A2/de
Priority to US12/999,834 priority patent/US8505198B2/en
Priority to JP2011513971A priority patent/JP2011524645A/ja
Priority to CN200980132214.1A priority patent/CN102124560B/zh
Publication of WO2009153129A2 publication Critical patent/WO2009153129A2/de
Publication of WO2009153129A3 publication Critical patent/WO2009153129A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2924/0001—Technical content checked by a classifier
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
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    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung einer elektronischen Baugruppe, umfassend mindestens ein elektronisches Bauelement (9) sowie eine Leiterbahnstruktur (7), mit der das mindestens eine elektronische Bauelement (9) kontaktiert wird. Bei dem Verfahren wird in einem ersten Schritt eine leitfähige Folie (1) zum Ausbilden der Leiterbahnstruktur (7) strukturiert. In einem zweiten Schritt wird die Leiterbahnstruktur (7) mit dem mindestens einen elektronischen Bauelement (9) bestückt. In einem abschließenden Schritt wird eine weitere Folie auf die mit dem mindestens ein elektronischen Bauelement (9) bestückte leitfähige Folie (1) auf der Seite, auf der die leitfähige Folie (1) mit dem mindestens ein elektronischen Bauelement (9) bestückt ist, auflaminiert.
PCT/EP2009/056286 2008-06-19 2009-05-25 Verfahren zur herstellung einer elektronischen baugruppe WO2009153129A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP09765709A EP2289100A2 (de) 2008-06-19 2009-05-25 Verfahren zur herstellung einer elektronischen baugruppe
US12/999,834 US8505198B2 (en) 2008-06-19 2009-05-25 Method for manufacturing an electronic assembly
JP2011513971A JP2011524645A (ja) 2008-06-19 2009-05-25 電子モジュールを製造するための方法
CN200980132214.1A CN102124560B (zh) 2008-06-19 2009-05-25 用于制造电子组件的方法

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DE102017203381A1 (de) * 2017-03-02 2018-04-05 Robert Bosch Gmbh Mikroelektronische Bauelementanordnung und entsprechendes Herstellungsverfahren
CN114946168B (zh) * 2020-01-24 2024-04-09 华为技术有限公司 用于电子设备的功能外壳结构
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WO2009153129A2 (de) 2009-12-23
DE102008002532A1 (de) 2009-12-24
CN102124560B (zh) 2014-05-07
CN102124560A (zh) 2011-07-13
EP2289100A2 (de) 2011-03-02
US8505198B2 (en) 2013-08-13
JP2011524645A (ja) 2011-09-01
US20110138620A1 (en) 2011-06-16

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