Nothing Special   »   [go: up one dir, main page]

WO2000049652A1 - Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique - Google Patents

Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique Download PDF

Info

Publication number
WO2000049652A1
WO2000049652A1 PCT/JP2000/000710 JP0000710W WO0049652A1 WO 2000049652 A1 WO2000049652 A1 WO 2000049652A1 JP 0000710 W JP0000710 W JP 0000710W WO 0049652 A1 WO0049652 A1 WO 0049652A1
Authority
WO
WIPO (PCT)
Prior art keywords
resin
adhesive member
semiconductor device
layer
manufacturing
Prior art date
Application number
PCT/JP2000/000710
Other languages
English (en)
Japanese (ja)
Other versions
WO2000049652A8 (fr
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to JP2000600302A priority Critical patent/JP4029255B2/ja
Publication of WO2000049652A1 publication Critical patent/WO2000049652A1/fr
Publication of WO2000049652A8 publication Critical patent/WO2000049652A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to an adhesive member, a semiconductor device and a method for manufacturing the same, a circuit board, and an electronic device.
  • the semiconductor chip and the substrate often differ greatly in thermal expansion coefficient.
  • stress caused by the difference in thermal expansion coefficient is applied to the adhesive member, and the adhesive member may peel off. was there.
  • an anisotropic conductive adhesive member when used as the adhesive member, when the anisotropic conductive film is pressed by the semiconductor chip and the substrate, the bumps of the semiconductor chip and the wiring pattern formed on the substrate are formed. In some cases, it is difficult to flow out the insulating resin while leaving the conductive particles between them.
  • An object of the present invention is to solve the above-described problems, and an object of the present invention is to provide an adhesive member capable of responding to requirements of different properties on both sides, a semiconductor device using the same, a method of manufacturing the same, a circuit board, and an electronic device. To provide.
  • the bonding member according to the present invention is used for bonding electronic components, and has different physical properties in the thickness direction.
  • the adhesive member since the physical properties are different on both surfaces of the adhesive member, it can be configured to be suitable for the material bonded to each surface.
  • the adhesive member may be an anisotropic conductive film.
  • anisotropic conductive films can be configured to be suitable for the material adhered to each surface.
  • the adhesive member has a two-layer structure of: a first layer having a first resin as a base material; and a second layer having a second resin as a base material. And the second resin may have different physical properties.
  • the first resin forming the first layer and the second resin forming the second layer have different physical properties. Therefore, the first resin and the second resin can be selected so as to have physical properties suitable for those of the member that adheres to the first layer and the member that adheres to the second layer.
  • the thermal expansion coefficient of the first resin may be smaller than the thermal expansion coefficient of the second resin.
  • the first and second resins respectively have heat corresponding thereto. Due to its expansion coefficient, peeling is less likely to occur.
  • the silica-based filler may be mixed only in the first resin.
  • the thermal expansion coefficient of the first resin can be reduced, more specifically, close to the thermal expansion coefficient of silicon.
  • Silica-based filler is mixed into the first resin and the second resin, and the mixing ratio of the silica-based filler into the first resin is determined by mixing the silica-based filler into the second resin. It may be greater than the rate.
  • the second resin may have a lower elasticity than the first resin.
  • the second resin may be a modified epoxy resin.
  • the first resin is an epoxy resin
  • the second resin may be a biphenyl resin.
  • the second resin has lower elasticity than the first resin.
  • Conductive particles may be dispersed only in the second resin.
  • Conductive particles are dispersed only in the second resin,
  • the second layer may be thinner than the first layer, and the second resin may have a higher viscosity when melted than the first resin.
  • the conductive particles are dispersed only in the second resin, the surface of the member that is in close contact with the first layer does not come into contact with the conductive particles, so that an electrical short circuit does not occur. Further, since the second layer is thinner than the first layer, the number of conductive particles can be reduced to prevent an electric short circuit. Furthermore, despite the small number of conductive particles, the high melt viscosity of the second resin allows the conductive particles to remain reliably. On the other hand, the first resin having a lower melt viscosity than the second resin is easy to flow out.
  • the silica-based filler may be mixed only in the second resin.
  • the melt viscosity of the second resin can be increased.
  • the first resin and the second resin are mixed with a silica-based filler, and the mixing ratio of the silica-based filler in the second resin is determined by the silica-based filler in the first resin. May be higher than the mixing ratio of
  • the melt viscosity of the second resin can be increased.
  • the second resin may have a higher molecular weight than the first resin.
  • the melt viscosity of the second resin can be increased.
  • a semiconductor device includes: a semiconductor chip; a substrate on which a wiring pattern is formed; and an adhesive member that electrically connects the semiconductor chip and the wiring pattern.
  • the adhesive members have different physical properties in the thickness direction.
  • the adhesive member since the physical properties are different on both surfaces of the adhesive member, it can be configured to be suitable for the material bonded to each surface.
  • the adhesive member may be an anisotropic conductive film.
  • anisotropic conductive films can be configured to be suitable for the material adhered to each surface.
  • the first resin and the second resin may have a layered structure and have different physical properties.
  • the first resin forming the first layer of the adhesive member and the second resin forming the second layer have different physical properties. Therefore, the first resin and the second resin can be selected so that the semiconductor chip adhered to the first layer and the substrate adhered to the second layer have properties suitable for those of the semiconductor chip. .
  • the bonding member may be the bonding member described above.
  • the semiconductor device is mounted on a circuit board according to the present invention.
  • An electronic apparatus includes the above semiconductor device.
  • the adhesive member has different physical properties in the thickness direction.
  • the adhesive member since the physical properties are different between the two surfaces of the adhesive member, it can be configured to be suitable for the material to be bonded to each surface.
  • the adhesive member may be an anisotropic conductive film.
  • anisotropic conductive films can be configured to be suitable for the material adhered to each surface.
  • a two-layer structure comprising: a first layer having a first resin as a base material; and a second layer having a second resin as a base material having different physical properties from the first resin. May be provided.
  • the first resin forming the first layer of the adhesive member and the second resin forming the second layer have different physical properties. Therefore, the first resin and the second resin can be selected so as to have physical properties suitable for being adhered to the semiconductor chip and the substrate.c (24) In this method of manufacturing a semiconductor device,
  • the first and second layers may be provided in order.
  • the first layer may be arranged on the semiconductor chip side, and the second layer may be arranged on the substrate side.
  • the bonding member may be the bonding member described above.
  • FIGS. 1A to 1C are diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a circuit board according to the embodiment of the present invention.
  • FIG. 3 is a diagram showing an electronic apparatus including a semiconductor device manufactured by applying the method according to the present invention.
  • FIG. 1C shows a semiconductor device 1 completed by the manufacturing method.
  • the semiconductor device 1 includes a semiconductor chip 10 and a substrate 20.
  • one surface (active surface) of the semiconductor chip 10 extends along at least one side (including two opposing sides or all sides).
  • a plurality of electrodes 12 are formed on the substrate. Alternatively, a plurality of electrodes 12 may be formed at the center of one surface of the semiconductor chip 10. Electrodes 12 are often provided with bumps 14 by means of solder balls, gold wire balls, gold plating, etc., but this is not essential.
  • the electrode 12 itself may be in the form of a bump. Nickel, chromium, titanium or the like may be added between the electrode 12 and the bump 14 as a diffusion preventing layer for the bump metal.
  • the overall shape of the substrate 20 is not particularly limited, and may be a rectangle, a polygon, or a combination of a plurality of rectangles, but may be similar to the planar shape of the semiconductor chip 10. it can.
  • the thickness of the substrate 20 is often determined by its material, but is not limited thereto.
  • the substrate 20 may be formed of any of an organic or inorganic material, and may be formed of a composite structure thereof, but is preferably punched through.
  • the substrate 20 can be formed by punching out a tape-shaped flexible substrate formed from an organic material.
  • a multilayer substrate ⁇ a build-up substrate may be used.
  • a build-up type substrate or multi-layer substrate if a wiring pattern is formed on a ground plane layer that spreads out in a plane, a microstrip structure without extra wiring pattern is obtained, Transmission physical properties can be improved.
  • a plurality of wirings are formed on one surface of the substrate 20 to form a wiring pattern 22. At least one or all of the plurality of wirings are not electrically connected to other wirings and are electrically independent. Alternatively, among the plurality of wirings, those connected to a common place such as the power supply and the ground of the semiconductor chip 10 may be connected to each other. Lands are formed at both ends of each wiring. In many cases, the lands are formed to have a larger width than a portion connecting between the lands. One land may be formed on the substrate 20 at a position near the end of the semiconductor device as a final product, and the other land may be formed at a position near the center of the substrate 20. A bump may be formed in a portion (for example, a land portion) of the wiring pattern 22 that is joined to the electrode 12 of the semiconductor chip 10. In that case, the bumps 14 of the semiconductor chip 10 can be omitted.
  • a plurality of through holes 24 are formed in the substrate 20.
  • the wiring pattern 22 is formed so that any of the wirings passes through the through hole 24.
  • the end of the wiring may be located on the through hole 24. If a land is formed at the end of the wiring, the land is located on the through hole 24.
  • an external terminal 40 is provided on the substrate 20.
  • the solder balls may be used as the external terminals 40.
  • the external terminal 40 is electrically connected to the wiring pattern 22.
  • the external terminal 40 can be electrically connected to the wiring pattern 22 by providing a conductive member with a plating or the like in the through hole 24 or by providing solder in the through hole.
  • the wiring pattern 22 is plated.
  • the wiring pattern 22 may be formed of copper and plated with nickel, gold, solder or tin. Conducting the plating ensures the conductivity. Specifically, good soldering with the external terminals 40 is possible, oxidation of the wiring surface is prevented, and the electrical connection resistance with the bumps is reduced.
  • the semiconductor chip 10 is mounted face down on the substrate 20.
  • the bumps 14 of the semiconductor chip 10 and the wiring patterns 22 formed on the substrate 20 are electrically connected.
  • the above-described external terminal 40 is not always necessary.
  • At least semi-conductive Any structure may be used as long as there is a body chip 10 and a substrate 20 on which opposing wiring patterns 22 are formed, and an adhesive member 30 exists between them.
  • At least the adhesive member 30 may be any resin having an insulating property and at least a resin (underfill resin), and may be a resin having anisotropic conductivity.
  • the face-down bonding between the bumps 14 of the semiconductor chip 10 and the wiring patterns 22 of the substrate 20 is performed by a metal-to-metal bonding method using a brazing material such as solder, or a mechanical bonding strength utilizing resin shrinkage.
  • a brazing material such as solder
  • a mechanical bonding strength utilizing resin shrinkage are known, such as a method of heating and pressurizing a semiconductor chip with gold bumps (ultrasonic bonding if necessary), and a method of using an anisotropic conductive film. Good.
  • the bonding member 30 has a two-layer structure of a first layer 32 and a second layer 34.
  • the first layer 32 is made of a first resin
  • the second layer 34 is made of a second resin.
  • the first resin and the second resin have different physical properties.
  • FIG. 1A shows an example in which an anisotropic conductive film is used as the bonding member 30.
  • the bonding member 30 is formed by dispersing conductive particles 36 in a binder.
  • Thermal expansion coefficient of the first resin is the thermal expansion coefficient of the second resin (e.g., 4 0 ⁇ 2 0 0 (1 0 _ 6 / ° C)).
  • the first layer 32 made of the first resin is in close contact with the semiconductor chip 10
  • the second layer 34 made of the second resin is in close contact with the substrate 20.
  • the semiconductor chip 10 is often made of a material having a small coefficient of thermal expansion (eg, silicon)
  • the substrate 20 is made of a material having a large coefficient of thermal expansion (eg, polyimide resin). Often.
  • a silica-based filler may be mixed into the first resin at a mixing rate of, for example, 30 to 60%. In that case, it is preferable not to mix the silica-based filler in the second resin.
  • the mixing ratio of the silica-based filler in the first resin is lower than that of the silica-based filler in the second resin. The ratio should be larger than the mixing ratio. In that case, the difference in the mixing ratio of the silica-based filler should be about 30 to 60%. Is preferred.
  • the bonding member 30 Difficult to peel.
  • the conductive particles 36 may be dispersed only in one of them. Specifically, it is preferable to disperse the conductive particles 36 only in the second layer 34 that is in close contact with the wiring pattern 22 having a larger electrical connection area than the bumps 14 of the semiconductor chip 10. By doing so, when the bumps 14 sink into the adhesive member 30 (anisotropic conductive film), the probability that the conductive particles 36 remain under the bumps 14 increases, and the reliability of the electrical connection is improved. The nature increases. In addition, since the conductive particles 36 are not dispersed in the first layer 32 that is in close contact with the semiconductor chip 10, a short circuit between the electrodes 12 of the semiconductor chip 10 is prevented.
  • the second resin may have a lower elasticity than the first tree.
  • the elastic modulus of the first resin may be about 3 to 10 (GPa), and the elastic modulus of the second resin may be about 1 to 3 GPa.
  • the epoxy resin may be denatured to be used as the second resin.
  • the first resin may be an epoxy resin and the second resin may be a biphenyl resin.
  • the conductive particles 36 may be dispersed only in one of them. More specifically, the conductive particles 3 are applied only to the second resin constituting the second layer 34 that adheres to the wiring pattern 22 having a larger electrical connection area than the bumps 14 of the semiconductor chip 10. Preferably, 6- is dispersed. By doing so, when the bumps 14 sink into the adhesive member 30, the probability that the conductive particles 36 remain under the bumps 14 increases, and the reliability of the electrical connection increases.
  • the first resin constituting the first layer 32 that is in close contact with the semiconductor chip 0 has conductive particles 3 Since 6 is not dispersed, a short circuit between the electrodes 12 of the semiconductor chip 10 is prevented. (If melt viscosity is different)
  • the second resin may have a higher viscosity when melted than the first resin.
  • the first resin with low melt viscosity is easy to flow out, and the second resin with high melt viscosity is hard to flow out.
  • the conductive particles 36 easily remain on the wiring 2.
  • the conductive particles 36 may be dispersed only in the second resin constituting the second layer 34 that is in close contact with the wiring pattern 22. Since the conductive particles 36 are not dispersed in the first resin constituting the first layer 32 adhered to the chip 10, short circuit between the electrodes 12 of the semiconductor chip 10 is prevented.
  • the second layer 32 may be thinner than the first layer 34.
  • the number of conductive particles 36 can be reduced to prevent an electrical short circuit, and despite the small number of conductive particles 36, the melt viscosity of the second resin is high, so that the conductive The particles 36 can be reliably left on the wiring pattern 22.
  • a silica-based filler may be mixed only with the second resin.
  • the silica-based filler is mixed into the first resin and the second resin, and the mixing ratio of the silica-based filler into the second resin is determined by mixing the silica-based filler into the first resin. It may be higher than the rate.
  • the molecular weight of the second resin may be larger than the molecular weight of the first resin.
  • the resin having different physical properties of the two layers has been described. More preferably, the physical property difference between the layers is not stepwise but changes continuously, and the physical property difference in the thickness direction is more preferable. It is beneficial because it does not exist. This is because peeling due to a difference in physical properties at the interface between the two layers is unlikely to occur. Therefore, specifically, a resin composed of multiple layers having different physical properties with a small difference or a resin whose physical properties continuously change in the thickness direction can be used.
  • a single layer of anisotropic conductive film is formed in a sheet shape, and then another anisotropic conductive film having another physical property is formed in a sheet shape on the layer. It can be obtained by creating. Subsequent handling is the same as that of the one-layer anisotropic conductive film. In the case of multiple layers, Repeat the work. To continuously form anisotropic conductive films having different physical properties in the thickness direction, it is necessary to use a solvent used for forming a two-layer or multi-layer anisotropic conductive film, or use a slight heating method. This causes interdiffusion between layers. Thereby, a continuous layer can be obtained.
  • the semiconductor device according to the present embodiment is configured as described above, and a manufacturing method thereof will be described below.
  • the surface of the semiconductor chip 10 on which the electrodes 12 (or the bumps 14) are formed and the surface of the substrate 20 on which the wiring patterns 22 are formed are arranged to face each other.
  • an adhesive member 30 is arranged between the semiconductor chip 10 and the substrate 20.
  • the adhesive member 30 is provided with the first layer 32 facing the semiconductor chip 10 and the second layer 34 facing the substrate 20. Note that the adhesive member 30 is preferably attached to one of the semiconductor chip 10 and the substrate 20.
  • each layer of the plurality of layers is provided in order. Is also good. More specifically, each layer may be provided on one of the semiconductor chip 10 and the substrate 20 in order, or one of the layers (for example, the first layer 32) may be provided on the semiconductor chip 10 and the other layer ( For example, a second layer 34) may be provided.
  • FIG. 1B the semiconductor chip 10 and the substrate 20 are brought into close contact with each other via an adhesive member 30. Specifically, the semiconductor chip 10 and the substrate 20 are pressed in a direction in which the distance between the two becomes smaller. As a result, the conductive particles 36 are interposed between the electrodes 12 (or bumps 14) of the semiconductor chip 10 and the wiring patterns 22 so that electrical connection between them can be achieved. As shown, by providing the external terminals 40 on the substrate 20, the semiconductor device 1 can be obtained.
  • FIG. 1C shows a FAN-IN type semiconductor device in which the external terminal 40 is provided only in the mounting area of the semiconductor chip 10, but the present invention is not limited to this.
  • the present invention is applied to a FAN-OUT type semiconductor device in which the external terminals 40 are provided only outside the mounting area of the semiconductor chip 10 and a FAN-IN / OUT type semiconductor device in which the FAN-IN type is combined.
  • the invention can be applied.
  • a semiconductor chip is formed by an anisotropic conductive film.
  • a stiffener may be attached to the outside of the top.
  • the adhesive member 30 including the first and second layers 32 and 34 is used, the above effects can be achieved.
  • FIG. 2 shows a circuit board 50 on which the semiconductor device 1 according to the present embodiment is mounted. It is common to use an organic substrate such as a glass epoxy substrate for the circuit board 50. Wiring patterns 52 made of, for example, copper are formed on the circuit board 50 so as to form a desired circuit, and these wiring patterns and the external terminals 40 of the semiconductor device 1 are mechanically connected. The electrical conduction between them is achieved.
  • FIG. 3 shows a notebook personal combination as an electronic apparatus 60 having the semiconductor device 1 to which the present invention is applied.
  • the constituent element "semiconductor chip” of the present invention is replaced with “electronic element”, and the electronic element (whether active element or passive element) is mounted on a substrate in the same manner as the semiconductor chip. Can also be manufactured. Electronic components manufactured using such electronic elements include, for example, a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a ballister, a volume or a fuse.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention concerne un dispositif semi-conducteur (1) comprenant un microcircuit semi-conducteur (10), un substrat (20) pourvu de réseaux de câblage (22), et un matériau de liaison (30) qui relie électriquement le microcircuit semi-conducteur (10) et les réseaux de câblage (22). Le matériau de liaison (30) présente une structure bi-couche. En l'occurrence, la première couche (32), qui comporte une première base en résine, est tournée vers le microcircuit semi-conducteur (10), la seconde couche (34) qui comporte une seconde base en résine, est tournée vers le substrat (20). Les deux couches de résine présentent des propriétés physiques différentes telles que le coefficient de dilatation.
PCT/JP2000/000710 1999-02-18 2000-02-09 Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique WO2000049652A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000600302A JP4029255B2 (ja) 1999-02-18 2000-02-09 接着部材

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/39625 1999-02-18
JP3962599 1999-02-18

Publications (2)

Publication Number Publication Date
WO2000049652A1 true WO2000049652A1 (fr) 2000-08-24
WO2000049652A8 WO2000049652A8 (fr) 2000-10-26

Family

ID=12558298

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/000710 WO2000049652A1 (fr) 1999-02-18 2000-02-09 Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique

Country Status (4)

Country Link
JP (1) JP4029255B2 (fr)
KR (1) KR100514425B1 (fr)
TW (1) TW550714B (fr)
WO (1) WO2000049652A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007514310A (ja) * 2003-12-12 2007-05-31 コミサリア、ア、レネルジ、アトミク 可塑的に変形可能な不可逆的ストレージ媒体と、このような一媒体を製造する方法
CN114023704A (zh) * 2022-01-05 2022-02-08 长鑫存储技术有限公司 非导电膜及其形成方法、芯片封装结构及方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100752A (ja) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd 回路装置およびその製造方法
KR102492533B1 (ko) 2017-09-21 2023-01-30 삼성전자주식회사 지지 기판, 이를 이용한 반도체 패키지의 제조방법 및 이를 이용한 전자 장치의 제조 방법
TWI714905B (zh) * 2018-11-08 2021-01-01 瑞昱半導體股份有限公司 電路裝置與電路設計及組裝方法
CN114374101A (zh) * 2022-01-12 2022-04-19 业成科技（成都）有限公司 连接结构和形成连接结构的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513119A (ja) * 1991-07-04 1993-01-22 Sharp Corp 電子部品接続用テープコネクタ
JPH1013002A (ja) * 1996-06-20 1998-01-16 Matsushita Electric Ind Co Ltd 半導体素子の実装方法
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JPH10199930A (ja) * 1996-12-28 1998-07-31 Casio Comput Co Ltd 電子部品の接続構造および接続方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2930186B2 (ja) * 1996-03-28 1999-08-03 松下電器産業株式会社 半導体装置の実装方法および半導体装置の実装体

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513119A (ja) * 1991-07-04 1993-01-22 Sharp Corp 電子部品接続用テープコネクタ
JPH1013002A (ja) * 1996-06-20 1998-01-16 Matsushita Electric Ind Co Ltd 半導体素子の実装方法
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JPH10199930A (ja) * 1996-12-28 1998-07-31 Casio Comput Co Ltd 電子部品の接続構造および接続方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007514310A (ja) * 2003-12-12 2007-05-31 コミサリア、ア、レネルジ、アトミク 可塑的に変形可能な不可逆的ストレージ媒体と、このような一媒体を製造する方法
CN114023704A (zh) * 2022-01-05 2022-02-08 长鑫存储技术有限公司 非导电膜及其形成方法、芯片封装结构及方法
CN114023704B (zh) * 2022-01-05 2022-04-01 长鑫存储技术有限公司 非导电膜及其形成方法、芯片封装结构及方法

Also Published As

Publication number Publication date
KR100514425B1 (ko) 2005-09-14
TW550714B (en) 2003-09-01
KR20010042822A (ko) 2001-05-25
JP4029255B2 (ja) 2008-01-09
WO2000049652A8 (fr) 2000-10-26

Similar Documents

Publication Publication Date Title
US8030137B2 (en) Flexible interposer for stacking semiconductor chips and connecting same to substrate
JP3994262B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP3838331B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US10083887B2 (en) Chip component-embedded resin multilayer substrate and manufacturing method thereof
WO2001026155A1 (fr) Dispositif a semi-conducteur, procede et dispositif permettant d'obtenir ce dernier, carte de circuit imprime et equipement electronique
JPWO2007043639A1 (ja) プリント配線基板及びプリント配線基板の製造方法
JPH10256429A (ja) 半導体パッケージ
JP3565090B2 (ja) 半導体装置の製造方法
JP2005191156A (ja) 電気部品内蔵配線板およびその製造方法
JP3654116B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US10398026B2 (en) Laminated substrate and method of manufacturing laminated substrate
JP2000243864A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
WO2000049652A1 (fr) Materiau de liaison, dispositif semi-conducteur et procede de fabrication, carte et dispositif electronique
JP2001223243A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP4849926B2 (ja) 半導体装置及び半導体装置の製造方法
JP3552701B2 (ja) 接着部材、半導体装置及びその製造方法、回路基板並びに電子機器
JPH10335528A (ja) 半導体パッケージおよび半導体パッケージの製造方法
JP2001111209A (ja) プリント配線板の接続方法および接続構造
JP2001203229A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JPH10125725A (ja) 半導体装置およびその製造方法
JP2008024941A (ja) 半導体装置
JPH11135567A (ja) 異方性導電膜、半導体装置の製造方法
JP2005045228A (ja) 光学情報記録媒体とその製造方法
JPH0951018A (ja) 半導体装置およびその製造方法
JP2001068604A (ja) 固定樹脂、異方性導電樹脂、半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 09673479

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020007011579

Country of ref document: KR

AK Designated states

Kind code of ref document: C1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: C1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WRT Later publication of a revised version of an international search report translation
WWP Wipo information: published in national office

Ref document number: 1020007011579

Country of ref document: KR

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020007011579

Country of ref document: KR