TWI846345B - Memory device - Google Patents

Abstract

A memory device, such as a three-dimensional AND or NOR flash memory, includes a memory cell block a plurality of bit line switches, a first switch and a second switch. The memory cell block is divided into a first sub memory cell block and a second sub memory cell block. The first bit line switches are respectively coupled to a plurality of first local bit lines, and commonly coupled to a first sub global bit line. The second bit line switches are respectively coupled to a plurality of second local bit lines, and commonly coupled to a second sub global bit line. The first switch is coupled between the first sub global bit line and a global bit line, and controlled by a first control signal. The second switch is coupled between the second sub global bit line and the global bit line, and controlled by a second control signal.

Description

Memory device

The present invention relates to a memory device, and in particular to a memory device capable of improving the repair efficiency of a memory.

In conventional memory devices, in order to ensure the memory performance of the memory device, the memory device is tested after the memory device is manufactured. For example, the test may be performed to determine whether a short circuit occurs between a local bit line and a local source line of a memory cell block in the memory device.

In a conventional memory device, a memory cell block has a plurality of regional bit lines and regional source lines arranged in an interlaced manner. In order to improve the production yield of the memory device, when a short circuit occurs between a regional bit line and a regional source line in a memory cell block, the entire memory cell block needs to be abandoned and replaced by a spare memory cell block. Such a repair method reduces the hardware performance of the memory device and easily causes a large amount of circuit area to be wasted.

The present invention provides a memory device which can improve the repair efficiency of the memory.

The memory device of the present invention includes a memory cell block, a plurality of first bit line switches, a plurality of second bit line switches, a first switch and a second switch. The memory cell block is divided into a first sub-memory cell block and a second sub-memory cell block. The first bit line switches are respectively coupled to a plurality of first regional bit lines in the first sub-memory cell block, and the first bit line switches are also commonly coupled to the first sub-common bit line. The second bit line switches are respectively coupled to a plurality of second regional bit lines in the second sub-memory cell block, and the second bit line switches are also commonly coupled to the second sub-common bit line. The first switch is coupled between the first sub-common bit line and the common bit line, and is controlled by a first control signal. The second switch is coupled between the second sub-common bit line and the common bit line, and is controlled by a second control signal.

Based on the above, in the memory device of the present invention, a memory block is divided into two sub-memory cell blocks. And a plurality of switches are respectively set between the two sub-memory cell blocks and the common bit line. The memory device can make the corresponding sub-memory cell block maintain normal operation or stop working by controlling the on or off state of the above-mentioned switches. When an abnormal phenomenon occurs in a sub-memory cell block, the corresponding switch can be cut off to stop working, and a backup memory cell block can be effectively provided to replace the abnormal sub-memory cell block. In this way, in the memory device of the present invention, when an abnormal phenomenon occurs, the memory cell block does not need to be completely replaced. By turning off the switch corresponding to the sub-memory cell block, the memory device can be repaired by replacing part of the memory cell block.

Please refer to FIG. 1, which is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 20 includes a plurality of memory cell blocks, wherein the memory cells in the memory cell block GP1 share a common bit line GBLi and a common source line GSLi, and the memory cells in the memory cell block GP2 share a common bit line GBLj and a common source line GSLj. The common bit line GBLi is coupled to the sense amplifier SA1, and the common bit line GBLj is coupled to the sense amplifier SA2. On the other hand, taking the memory cell block GP1 as an example, the memory cell block GP1 has a plurality of regional bit lines and is respectively coupled to a plurality of bit line switches BLT. These bit line switches BLT are divided into two groups, one of which is coupled to the switch SW1, and the other is coupled to the switch SW2. The terminal of the switch SW1 not coupled to the bit line switch BLT and the terminal of the switch SW2 not coupled to the bit line switch BLT are mutually coupled to the sense amplifier SA1 and mutually coupled to the common bit line GBLi.

In this embodiment, taking a single memory cell block GP1 having eight bit line switches BLT as an example, the switch SW1 may be coupled to four of the bit line switches BLT, and the switch SW2 may be coupled to the other four bit line switches BLT.

In the present embodiment, if a short circuit occurs between the regional bit line BL1 and the regional source line SL1, the switch SW1 can be cut off accordingly, while the switch SW2 remains turned on. In this way, the memory cells on the regional bit line corresponding to the bit line switch BLT coupled to the switch SW1 can be isolated so as not to be coupled to the sense amplifier SA1 and be disabled. On the other hand, since the switch SW2 remains turned on, the memory cells on the regional bit line corresponding to the bit line switch BLT coupled to the switch SW2 can still maintain normal operation. In other words, the memory cells on some regional bit lines in the same memory cell block GP1 can still maintain normal operation when a short circuit occurs between the regional bit line BL1 and the regional source line SL1.

Compared with the memory devices of the prior art, the following table shows: Architecture Number of bit line switches Repair efficiency Distance between GBLi and GBLj Prior Art 8 Poor normal Figure 1 8 + 2 (SW1, SW2) Better normal

The sense amplifier SA1 is used to compare a reference signal with the electrical signal on the common bit line GBLi to generate a sensing result.

Please refer to Fig. 2, which shows a circuit diagram of a memory device according to an embodiment of the present invention. The memory device 100 includes a memory cell block 110, bit line switches BLT1-BLT4, bit line switches BLT5-BLT8, switch SW1, switch SW2, source line switches SLT1-SLT4 and source line switches SLT5-SLT8.

In the present embodiment, the memory cell block 110 can be divided into a first sub-memory cell block 111 and a second sub-memory cell block 112. The first sub-memory cell block 111 and the second sub-memory cell block 112 each include a plurality of memory cells MC. The first sub-memory cell block 111 has a plurality of regional bit lines BL1-BL4 and a plurality of regional source lines SL1-SL4. In addition, each of the bit line switches BLT1-BLT4 has a first end and a second end. The first ends of the bit line switches BLT1-BLT4 are respectively coupled to the regional bit lines BL1-BL4, and the second ends of the bit line switches BLT1-BLT4 are commonly coupled to the first sub-common bit line SGBL1. Each of the source line switches SLT1 - SLT4 has a first end and a second end. The first ends of the source line switches SLT1 - SLT4 are respectively coupled to the local source lines SL1 - SL4 , and the second ends of the source line switches SLT1 - SLT4 are commonly coupled to the common source line CSL.

The second sub-memory cell block 112 has a plurality of regional bit lines BL5-BL8 and a plurality of regional source lines SL5-SL8. In addition, each of the bit line switches BLT5-BLT8 has a first end and a second end. The first ends of the bit line switches BLT5-BLT8 are respectively coupled to the regional bit lines BL5-BL8, and the second ends of the bit line switches BLT5-BLT8 are commonly coupled to the second sub-common bit line SGBL2. Each of the source line switches SLT5-SLT8 has a first end and a second end, the first ends of the source line switches SLT5-SLT8 are respectively coupled to the regional source lines SL5-SL8, and the second ends of the source line switches SLT5-SLT8 are commonly coupled to the common source line CSL.

On the other hand, the switch SW1 is coupled between the first sub-common bit line SGBL1 and the common bit line GBL. The switch SW1 is controlled by the control signal CT1 to be turned on or off. The switch SW2 is coupled between the second sub-common bit line SGBL2 and the common bit line GBL. The switch SW2 is controlled by the control signal CT2 to be turned on or off.

The first sub-memory cell block 111 and the second sub-memory cell block 112 share a plurality of word lines WL1-WLN.

In the present embodiment, the switch SW1 is used to control the path for any memory cell MC in the first sub-memory cell block 111 to transmit a signal to the common bit line GBL. When the switch SW1 is turned on, the first sub-memory cell block 111 can operate normally. In contrast, when the switch SW1 is turned off, any memory cell MC in the first sub-memory cell block 111 cannot transmit a signal to the common bit line GBL. Moreover, the sense amplifier (not shown) in the memory device 100 cannot sense the information stored in any memory cell MC in the first sub-memory cell block 111 by receiving the signal on the common bit line GBL. That is, when the switch SW1 is turned off, the operation of the first sub-memory cell block 111 can be stopped.

Similarly, the switch SW2 is used to control the path for any memory cell MC in the second memory cell block 112 to transmit a signal to the common bit line GBL. When the switch SW2 is turned on, the second memory cell block 112 can operate normally. Conversely, when the switch SW2 is turned off, the operation of the second memory cell block 112 can be stopped.

In this embodiment, by performing a test operation on the memory device 100, it can be known whether the first sub-memory cell block 111 and the second sub-memory cell block 112 have any abnormality. For example, through the test operation, it can be known whether any of the regional bit lines BL1 to BL4 in the first sub-memory cell block 111 has a short circuit with any of the regional source lines SL1 to SL4. It can also be known whether any of the regional bit lines BL5 to BL8 in the second sub-memory cell block 112 has a short circuit with any of the regional source lines SL5 to SL8. According to the test results of the above test operations, the memory device 100 can generate control signals CT1 and CT2. When any of the local bit lines BL1-BL4 in the first sub-memory cell block 111 is short-circuited with any of the local source lines SL1-SL4, a corresponding control signal CT1 is generated to turn off the switch SW1. When any of the local bit lines BL5-BL8 in the second sub-memory cell block 112 is short-circuited with any of the local source lines SL5-SL8, the memory device 100 may generate a corresponding control signal CT2 to turn off the switch SW2.

Incidentally, if the test result indicates that the first sub-memory cell block 111 has no abnormality, the memory device 100 may generate a corresponding control signal CT1 to turn on the switch SW1. If the test result indicates that the second sub-memory cell block 112 has no abnormality, the memory device 100 may generate a corresponding control signal CT2 to turn on the switch SW2.

For example, when the switch SW1 is turned off, the memory device 100 can enable the backup memory cell block to replace the abnormal first sub-memory cell block 111. In other words, if only one of the sub-memory cell blocks (e.g., the first sub-memory cell block 111) in the memory cell block 100 is abnormal, the replacement action of part of the memory cell block 100 can be performed by only turning off the switch SW1 (keeping the switch SW2 turned on). In this way, the second sub-memory cell block 112 without abnormal state can maintain normal operation, which can improve the repair efficiency of the memory device 100.

In this embodiment, switches SW1, SW2, bit line switches BLT1-BLT8, and source line switches SLT1-SLT8 can all be transistor switches. Memory cells MC in the memory cell block 100 can be AND flash memory cells or NOR flash memory cells, and can be constructed in a two-dimensional or three-dimensional manner.

Please refer to FIG. 3 below, which is a schematic diagram of a memory device according to another embodiment of the present invention. The memory device 200 includes a memory cell block 210 and spare memory cell blocks 220 and 230. The memory cell block 210 can be divided into a first memory cell sub-block 211 and a second memory cell sub-block 212. The multiple regional bit lines of the first memory cell sub-block 211 are coupled to the first sub-common bit line SGBL1 through bit line switches BLT1 to BLT4, respectively. The multiple regional bit lines of the second memory cell sub-block 212 are coupled to the second sub-common bit line SGBL2 through bit line switches BLT5 to BLT8, respectively. The switch SW1 is coupled between the first sub-common bit line SGBL1 and the common bit line GBL, and the switch SW2 is coupled between the second sub-common bit line SGBL2 and the common bit line GBL. In addition, the multiple regional source lines of the first memory cell block 211 are coupled to the common source line CSL through the source line switches SLT1-SLT4. The multiple regional source lines of the second memory cell block 212 are coupled to the common source line CSL through the source line switches SLT5-SLT8.

On the other hand, a plurality of regional bit lines of the backup memory cell block 220 are respectively coupled to the bit line switches BLTB1~BLTB4. A plurality of regional source lines of the backup memory cell block 220 are respectively coupled to the source line switches SLTB1~SLTB4, and the source line switches SLTB1~SLTB4 are also commonly coupled to the common source line CSL. The bit line switches BLTB1~BLTB4 are also commonly coupled to the sub-common bit line SGBL3. The switch SW3 is coupled between the sub-common bit line SGBL3 and the common bit line GBL. A plurality of regional bit lines of the backup memory cell block 230 are respectively coupled to the bit line switches BLTB5~BLTB8. The multiple regional source lines of the backup memory cell block 230 are respectively coupled to the source line switches SLTB5-SLTB8, and the source line switches SLTB5-SLTB8 are also commonly coupled to the common source line CSL. The bit line switches BLTB5-BLTB8 are also commonly coupled to the sub-common bit line SGBL4. The switch SW4 is coupled between the sub-common bit line SGBL4 and the common bit line GBL.

In this embodiment, the switches SW1-SW4 are controlled by control signals CT1-CT4 respectively. When one of the first memory cell block 211 and the second memory cell block 212 is detected to be in an abnormal state, one of the switches SW1 and SW2 (the switch corresponding to the memory cell block in the abnormal state) can be turned off, and the other of the switches SW1 and SW2 (the switch corresponding to the memory cell block in the normal state) can remain turned on. Correspondingly, the switch SW3 can be turned on according to the control signal CT3, and the spare memory cell block 220 is activated to replace the abnormal memory cell block (one of the first memory cell block 211 and the second memory cell block 212). At the same time, based on the fact that the other of the first memory cell block 211 and the second memory cell block 212 is in a normal state, the switch SW4 can be turned off according to the control signal CT4, so that the spare memory cell block 230 does not perform the replacement action of the memory cell block.

It should be noted that the circuit structure of any of the spare memory cell blocks 220 and 230 can be the same as that of any of the first memory cell sub-block 211 and the second memory cell sub-block 212. That is, taking the spare memory cell block 220 as an example, the number of memory cells in the spare memory cell block 220 can be the same as the number of memory cells in the first memory cell sub-block 211, and the first memory cell sub-block 211 and the second memory cell sub-block 212 have the same number of memory cells.

In addition, in this embodiment, the memory device 200 may have a larger number of spare memory cell blocks 220 and 230, and may perform replacement operations on a plurality of abnormal memory cell sub-blocks to ensure the normal operation of the memory device 200.

Please refer to FIG. 4 below, which shows a partial schematic diagram of the memory device of an embodiment of the present invention. Therein, the memory device 400 has a plurality of bit line switches BT1~BT8. The bit line switches BT1~BT8 are arranged in pairs. One end of the bit line switches BT1~BT4 is commonly coupled to the sub-common bit line SGBL1, and one end of the bit line switches BT5~BT8 is commonly coupled to the sub-common bit line SGBL2. The other ends of the bit line switches BT1~BT4 are respectively coupled to the regional bit lines BL1~BL4, and the other ends of the bit line switches BT5~BT8 can be respectively coupled to different multiple bit lines (such as the bit lines BL5~BL8 of the embodiment of FIG. 1).

In addition, switches SW1 and SW2 are arranged in pairs. Switch SW1 is coupled between sub-common bit line SGBL1 and common bit line GBL, and switch SW2 is coupled between sub-common bit line SGBL2 and common bit line GBL. Based on the three-dimensional stacking structure, common bit line GBL can be formed by the second top metal layer (top metal 2, TM2), for example. Switches SW1 and SW2 can be coupled to common bit line GBL through through-silicon vias (TSV). In addition, regional bit lines BL1~BL4 can be formed by the first top metal layer (top metal 1, TM1), and can be slightly lower in height than common bit line GBL. Incidentally, in this embodiment, the regional source lines SL1-SL4 may be formed on the first upper metal layer, and the common source line CSL may be formed on the second upper metal layer.

5 is a schematic diagram of a memory device according to another embodiment of the present invention. In the memory device 500, a memory cell block 510 can be divided into sub-memory cell blocks 511, 512, 513 and 514. The sub-memory cell block 511 is coupled to the switch SW51 through the bit line switches BLT1 and BLT2, and then coupled to the common bit line GBL through the switch SW51. The sub-memory cell block 511 is also coupled to the common source line CSL through the source line switches SLT1 and SLT2. The sub-memory cell block 512 is coupled to the switch SW52 through the bit line switches BLT3 and BLT4, and then coupled to the common bit line GBL through the switch SW52. The sub-memory cell block 512 is also coupled to the common source line CSL through the source line switches SLT3 and SLT4. The sub-memory cell block 513 is coupled to the switch SW53 through the bit line switches BLT5 and BLT6, and then coupled to the common bit line GBL through the switch SW53. The sub-memory cell block 513 is also coupled to the common source line CSL through the source line switches SLT5 and SLT6. The sub-memory cell block 514 is coupled to the switch SW54 through the bit line switches BLT7 and BLT8, and then coupled to the common bit line GBL through the switch SW54. The sub-memory cell block 514 is also coupled to the common source line CSL through the source line switches SLT7 and SLT8.

Compared to the memory device 100 of the embodiment of FIG. 1 , the memory device 500 of the present embodiment further divides the memory cell block 510 into a larger number of sub-memory cell blocks 511 to 514. Thus, when an abnormality occurs in one of the sub-memory cell blocks 511 to 514, a smaller portion of the memory cell block 510 can be replaced to complete the repair operation, thereby effectively improving the performance of the memory device 500.

Incidentally, in this embodiment, corresponding to the sub-memory cell blocks 511-514, one or more spare memory cell blocks with the same circuit structure and number of memory cells as the sub-memory cell blocks 511-514 can be set in the memory device 500. When an abnormality occurs in one of the sub-memory cell blocks 511-514, the spare memory cell block can be used to perform a replacement action.

The details of the operation of using the spare memory cell block to replace one of the sub-memory cell blocks 511-514 have been described in detail in the aforementioned embodiments and will not be elaborated here.

Please refer to FIG. 6 below, which shows a schematic diagram of the architecture of a memory cell of a memory device of an embodiment of the present invention. In the memory device of the embodiment of the present invention, multiple memory cells MCs in a memory cell block can be constructed in a stacked manner to form a memory cell string with a three-dimensional structure. Each memory cell can have a silicon oxide-silicon nitride-silicon oxide layer ONO as an insulating layer. And it has a channel structure CH and a gate structure GS. The regional bit line BL and the regional source line SL are connected to all the memory cells MCs in the memory cell string through conductive pins PG1 and PG2, respectively.

In this embodiment, the memory cells MCs may be NOR flash memory cells or AND flash memory cells.

It is worth mentioning that in other embodiments of the present invention, memory cells MCs can also be arranged in a two-dimensional manner without any specific limitation.

In summary, the present invention divides a memory cell block into multiple sub-memory cell blocks, and sets multiple switches between the sub-memory cell blocks and the common bit lines. When an abnormality occurs in a sub-memory cell block, the corresponding switch can be cut off, and the sub-memory cell block with the abnormality can be replaced by the backup memory cell block. In this way, when an abnormality occurs in a memory cell block, it is not necessary to completely replace the memory cell block, but the memory cell block can be repaired by replacing part of the sub-memory cell blocks, effectively improving the use efficiency of the hardware space of the memory device.

20, 100, 200, 300, 400, 500: memory device 110, 310, 510, GP1, GP2: memory cell block 111, 211, 311: first sub-memory cell block 112, 212, 312: second sub-memory cell block 220, 230: backup memory cell block 511~514: sub-memory cell block BL1~BL8, BL: regional bit line BLT1~BLT8, BLTB1~BLTB8, BLT: bit line switch CH: channel structure CSL, GSLi, GSLj: common source line CT1, CT2, CT3: control signal GBL, GBLi, GBLj: common bit line GS: Gate structure MC, MCs: Memory cells ONO: Silicon oxide-silicon nitride-silicon oxide layer PG1, PG2: Conductive pins SA1, SA2: Sense amplifiers SGBL1, SGBL2, SGBL3, SGBL4: Sub-common bit lines SL1~SL8, SL: Regional source lines SLT1~SLT8, SLTB1~SLTB8: Source line switches SW1, SW2, SW3, SW4, SW51~SW54: Switches WL1~WLN: Word lines

FIG1 is a schematic diagram of a memory device of an embodiment of the present invention. FIG2 is a circuit diagram of a memory device of an embodiment of the present invention. FIG3 is a schematic diagram of a memory device of another embodiment of the present invention. FIG4 is a schematic diagram of a partial structure of a memory device of an embodiment of the present invention. FIG5 is a schematic diagram of a memory device of another embodiment of the present invention. FIG6 is a schematic diagram of the structure of a memory cell of a memory device of an embodiment of the present invention.

100: Memory device

110: Memory cell block

111: First sub-memory cell block

112: Second sub-memory cell block

BL1~BL8: Regional bit lines

BLT1~BLT8: bit line switch

CSL: Common Source Line

CT1, CT2: control signal

GBL: Common Bit Line

MC: Memory Cell

SGBL1, SGBL2: sub-common bit lines

SL1~SL8: Regional source line

SLT1~SLT8: Source line switch

SW1, SW2: switch

WL1~WLN: character line

Claims (14)

A memory device includes: a memory cell block, divided into a first sub-memory cell block and a second sub-memory cell block; a plurality of first bit line switches, respectively coupled to a plurality of first regional bit lines in the first sub-memory cell block, and the first bit line switches are commonly coupled to a first sub-common bit line; a plurality of second bit line switches, respectively coupled to a plurality of second regional bit lines in the second sub-memory cell block, and the second bit line switches are commonly coupled to a first sub-common bit line. line switches and are commonly coupled to a second sub-common bit line; a first switch coupled between the first sub-common bit line and a common bit line, and controlled by a first control signal; and a second switch coupled between the second sub-common bit line and the common bit line, and controlled by a second control signal, wherein the first switch is turned on or off according to whether a short circuit occurs between the corresponding first regional bit line and the adjacent regional source line. The memory device as described in claim 1 further comprises: a plurality of first source line switches respectively coupled between a plurality of first regional source lines and a common source line of the first sub-memory cell block; and a plurality of second source line switches respectively coupled between a plurality of second regional source lines and the common source line of the second sub-memory cell block. The memory device as described in claim 2 further includes: at least one spare memory cell block; a plurality of third bit line switches respectively coupled to a plurality of third regional bit lines in the at least one spare memory cell block, and the third bit line switches are commonly coupled to a third sub-common bit line; and a third switch coupled between the third sub-common bit line and the common bit line, and controlled by a third control signal. A memory device as described in claim 3, wherein when a short circuit occurs between at least one of the first regional bit lines and at least one of the first regional source lines in the first sub-memory cell block, the first switch is disconnected according to the first control signal. A memory device as described in claim 4, wherein when at least one of the first regional bit lines in the first sub-memory cell block and at least one of the first regional source lines are short-circuited, the third switch is turned on to allow the at least one backup memory cell block to replace the first sub-memory cell block. A memory device as described in claim 3, wherein when at least one of the second regional bit lines in the second sub-memory cell block and at least one of the second regional source lines are short-circuited, the second switch is disconnected according to the second control signal. A memory device as described in claim 6, wherein when at least one of the second regional bit lines in the second sub-memory cell block and at least one of the second regional source lines are short-circuited, the third switch is turned on to allow the at least one backup memory cell block to replace the second sub-memory cell block. A memory device as described in claim 3, wherein the number of memory cells in each of the at least one spare memory cell block is the same as the number of memory cells in the first sub-memory cell block, and the number of memory cells in the first sub-memory cell block is the same as the number of memory cells in the second sub-memory cell block. A memory device as described in claim 1, wherein the plurality of memory cells in the memory cell block are AND or NOR flash memory cells. A memory device as described in claim 9, wherein the memory cells are arranged in two or three dimensions. A memory device as described in claim 1, wherein the memory cell block further comprises: at least one third memory cell sub-block coupled to at least one third sub-common bit line through a plurality of third bit line switches; and at least one third switch coupled between the at least one third sub-common bit line and the common bit line, and controlled by at least one third control signal. A memory device as described in claim 11, wherein the at least one third switch is turned on or off according to whether a short circuit occurs between each of the corresponding plurality of third regional bit lines and the adjacent regional source line. The memory device as described in claim 1 further includes: a sense amplifier coupled to the common bit line, so that a reference signal is compared with the electrical signal on the common bit line to generate a sense result. A memory device as described in claim 1, wherein the second switch is turned on or off according to whether a short circuit occurs between the corresponding second regional bit line and the adjacent regional source line.