TWI853398B - Memory device and test method thereof - Google Patents

Abstract

A memory device and a test method thereof are provided. The memory device, such as a 3D stack flash memory, includes a memory cell array, a first global bit line, a second global bit line and a switch component. The memory cell array is divided into a first memory cell group and a second memory cell group, the first memory cell group has a plurality of first local bit lines and a plurality of first local source lines, and the second memory cell group has a plurality of second local bit lines and a plurality of second local source lines. The switch component, during a plurality of different test modes, is configured to couple the first local source lines to a common source line, or couple the second local source lines to the common source line.

Description

Memory device and testing method thereof

The present invention relates to a memory device and a testing method thereof, and in particular to a memory device and a testing method for testing the short circuit state between source lines and bit lines.

With the advancement of electronic technology, the storage density of memory devices has also increased. In today's memory cell arrays, there are often a large number of regional bit lines and regional source lines. These regional bit lines and regional source lines are usually arranged in a staggered manner and may short-circuit with each other.

In a memory device, the short circuit between the local bit line and the local source line can occur in the same memory cell group or between adjacent memory cell groups. In the known testing technology, when a short circuit is detected between the local bit line and the local source line, it is often impossible to identify whether the short circuit occurs in the same memory cell group or between adjacent memory cell groups. Therefore, it is impossible to perform the correct repair action.

The present invention provides a memory device and a testing method thereof, which can effectively test the short circuit phenomenon between the regional bit lines and the regional source lines between adjacent groups.

The memory device of the present invention, for example, is a three-dimensional stacked and type flash memory, including a memory cell array, a first common bit line, a second common bit line and a switch element. The memory cell array is divided into a first memory cell group and a second memory cell group, the first memory cell group has a plurality of first regional bit lines and a plurality of first regional source lines, and the second memory cell group has a plurality of second regional bit lines and a plurality of second regional source lines. The first common bit line and a second common bit line are coupled to a first sense amplifier and a second sense amplifier, respectively. The first common bit line is coupled to the first regional bit line. The second common bit line is coupled to the second regional bit line. The switch element is coupled between the first regional source line, the second regional source line and the common source line. The switch element is used to couple the first regional source line to the common source line, or to couple the second regional source line to the common source line in different test modes.

The testing method of the present invention includes: dividing a memory cell array into a first memory cell group and a second memory cell group, wherein the first memory cell group has a plurality of first regional bit lines and a plurality of first regional source lines, and the second memory cell group has a plurality of second regional bit lines and a plurality of second regional source lines; coupling a first common bit line and a second common bit line to a first sense amplifier and a second sense amplifier respectively, wherein the first common bit line is coupled to the first regional bit line, and the second common bit line is coupled to the second regional bit line; setting a switch element between the first regional source line, the second regional source line and the common source line; and, in different multiple test modes, coupling the first regional source line to the common source line, or coupling the second regional source line to the common source line.

Based on the above, the memory device of the present invention couples the first regional source line or the second regional source line to the common source line through a switch element to test the short circuit phenomenon between the regional bit line and the regional source line in the same memory cell group, and to test the short circuit phenomenon between the regional bit line and the regional source line between adjacent memory cell groups. In this way, the short circuit phenomenon between the regional bit line and the regional source line in the memory cell array can be effectively tested, and the normal operation of the memory device can be maintained.

100, 200: Memory device

110: Memory cell array

120, 210: switch components

AC: memory cell area

BL11_1~BL22_8, BL: regional bit line

BLT111~BLT228, BLT: bit line switch

CH: Channel structure

CSL: Common Source Line

CT1, CT2: test mode signal

GBL11~GBL22, GBL_n, GBL_n+1, GBLi, GBLj: common bit lines

GP1, GP2: memory cell groups

GP11, GP12, GP21, GP22: memory cell groups

GS, GS1, GS2: Gate structure

GSL_n+1, GSL_n: source line

MC, MCs: memory cells

ONO: Silicon oxide-silicon nitride-silicon oxide layer

PG1, PG2: Conductive pins

S310~S330, S610~S640: Steps

SA1, SA2: sensor amplifier

SL11_1~SL22_8, SLi, SLj, SL: Regional source line

SLT111~SLT228, SLT: Source line switch

SSW11, SSW12, SSW21, SSW22: Select switch

WL1~WLN: character line

SW1, SW2: switch

FIG1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG2 is a schematic diagram showing the structure of a memory device according to an embodiment of the present invention.

FIG3 shows a test flow chart of a memory device according to an embodiment of the present invention.

Figures 4A to 4C are schematic diagrams showing the test actions of the memory device of an embodiment of the present invention.

FIG5 is a schematic diagram showing the memory cell architecture of a memory device according to an embodiment of the present invention.

FIG6 is a flow chart showing a method for testing a memory device according to an embodiment of the present invention.

Please refer to FIG. 1 , which shows a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 100 includes a memory cell array 110, first common bit lines GBL11, GBL21, second common bit lines GBL12, GBL22, sense amplifiers SA1, SA2, and a switch element 120. The memory cell array 110 has a plurality of flash memory cells MC. The memory cell array 110 is divided into a first memory cell group GP1 and a second memory cell group GP2, wherein the first memory cell group can be further divided into memory cell sub-groups GP11, GP12, and the second memory cell group can be further divided into memory cell sub-groups GP21, GP22. In this embodiment, the memory cell subgroup GP11 has regional source lines SL11_1~SL11_8 and regional bit lines BL11_1~BL11_8; the memory cell subgroup GP21 has regional source lines SL21_1~SL21_8 and regional bit lines BL21_1~BL21_8; the memory cell subgroup GP12 has regional source lines SL12_1~SL12_8 and regional bit lines BL12_1~BL12_8; the memory cell subgroup GP21 has regional source lines SL22_1~SL22_8 and regional bit lines BL22_1~BL22_8.

In addition, the regional source lines SL11_1 to SL11_8 and the regional source lines SL12_1 to SL12_8 are coupled to the switch element 120 through the source line switches SLT111 to SLT118 and SLT121 to SLT128, respectively. The regional source lines SL21_1 to SL21_8 and the regional source lines SL22_1 to SL22_8 are coupled to the switch element 120 through the source line switches SLT211 to SLT218 and SLT221 to SLT228, respectively. The regional bit lines BL11_1~BL11_8 are coupled to the common bit line GBL11 through the bit line switches BLT111~BLT118; the regional bit lines BL21_1~BL21_8 are coupled to the common bit line GBL21 through the bit line switches BLT211~BLT218; the regional bit lines BL12_1~BL12_8 are coupled to the common bit line GBL12 through the bit line switches BLT121~BLT128; the regional bit lines BL22_1~BL22_8 are coupled to the common bit line GBL22 through the bit line switches BLT221~BLT228.

The above-mentioned source line switches SLT111~SLT228 and bit line switches BLT111~BLT228 can all be transistor switches.

The sense amplifier SA1 is coupled to the common bit lines GBL11 and GBL21 respectively through the selection switches SSW11 and SSW21. The sense amplifier SA2 is coupled to the common bit lines GBL21 and GBL22 respectively through the selection switches SSW12 and SSW22.

On the other hand, the switch element 120 includes switches SW1 and SW2 constructed by transistors. The first end of the switch SW1 is coupled to the source line switches SLT111~SLT118 and SLT121~SLT128, and the second end of the switch SW1 is coupled to the common source line CSL. The first end of the switch SW2 is coupled to the source line switches SLT211~SLT218 and SLT221~SLT228, and the second end of the switch SW2 is coupled to the common source line CSL. The switches SW1 and SW2 are controlled by the test mode signals CT1 and CT2, respectively.

In the embodiment of the present invention, when the memory device 100 is tested for short circuit between the regional bit lines BL11_1~BL22_8 and the regional source lines SL11_1~SL22_8, all memory cells MC in the memory cell array 110 are turned off by the received word line voltages WL1~WLN. In addition, the regional bit lines and the regional source lines under test can be selected by the on or off state of each of the source line switches SLT111~SLT228 and the bit line switches BLT111~BLT228. The sense amplifiers SA1 and SA2 can obtain the test results by sensing whether leakage occurs on the common bit lines coupled thereto.

It is worth noting that in the above test action, the switch element 120 can use the on or off state of the switch SW1 to make the regional source lines SL11_1~SL11_8 and SL12_1~SL12_8 a common source line CSL voltage or a floating state. The switch element 120 can also use the on or off state of the switch SW2 to make the regional source lines SL21_1~SL21_8 and SL22_1~SL22_8 a common source voltage or a floating state. In this embodiment, the common source voltage can be any set voltage value, such as 0 volts.

In detail, when the switch element 120, in conjunction with the on and off states of the source line switches SLT111~SLT118 and SLT121~SLT128, makes one of the regional source lines SL11_1~SL11_8 and one of SL12_1~SL12_8 a common source voltage (0 volts), the switch element 120 can make the regional source lines SL21_1~SL21_8 and SL22_1~SL22_8 floating. At this time, in combination with the on and off states of the bit line switches BLT111~BLT118 and BLT121~BLT128 and the on states of the selection switches SSW11 and SSW12, one of the local bit lines BL11_1~BL11_8 and one of BL12_1~BL12_8 can be coupled to the common bit lines GBL11 and GBL12 respectively, and coupled to the sense amplifiers SA1 and SA2 respectively through the selection switches SSW11 and SSW12. In this way, the sense amplifier SA1 can detect whether there is a short circuit between the local bit lines BL11_1~BL11_8 and the local source lines SL11_1~SL11_8 in the memory cell group GP11 by sensing whether there is a leakage current on the common bit line GBL11, and the sense amplifier SA2 can detect whether there is a short circuit between the local bit lines BL12_1~BL12_8 and the local source lines SL12_1~SL12_8 in the memory cell group GP12 by sensing whether there is a leakage current on the common bit line GBL12.

It is worth mentioning that when the above test results indicate that a short circuit occurs between the regional bit lines BL11_1~BL11_8, BL12_1~BL12_8 and the regional source lines SL11_1~SL11_8, SL12_1~SL12_8, a replacement operation can be performed on the memory cell string where the short circuit occurs, and the error state can be effectively eliminated.

Next, the switch element 120 can be turned on and off by coordinating the on and off states of the source line switches SLT211~SLT218 and SLT221~SLT228, so that one of the regional source lines SL21_1~SL21_8 and one of SL22_1~SL22_8 are at a common source voltage (0 volts). The switch element 120 can also make the regional source lines SL11_1~SL11_8 and SL12_1~SL12_8 float. At this time, in combination with the on and off states of the bit line switches BLT211~BLT218 and BLT221~BLT228 and the on states of the selection switches SSW21 and SSW22, one of the local bit lines BL21_1~BL21_8 and one of BL22_1~BL22_8 can be coupled to the common bit lines GBL21 and GBL22 respectively, and coupled to the sense amplifiers SA1 and SA2 respectively through the selection switches SSW21 and SSW22. In this way, the sense amplifier SA1 can detect whether there is a short circuit between the local bit lines BL21_1~BL21_8 and the local source lines SL21_1~SL21_8 in the memory cell group GP21 by sensing whether there is a leakage current on the common bit line GBL21, and the sense amplifier SA2 can detect whether there is a short circuit between the local bit lines BL22_1~BL22_8 and the local source lines SL22_1~SL22_8 in the memory cell group GP22 by sensing whether there is a leakage current on the common bit line GBL22.

It is worth mentioning that when the above test results indicate that a short circuit occurs between the regional bit lines BL21_1~BL21_8, BL22_1~BL22_8 and the regional source lines SL21_1~SL21_8, SL22_1~SL22_8, a replacement operation can be performed on the memory cell string where the short circuit occurs, and the error state can be effectively eliminated.

Through the above test actions, the short circuit phenomenon in the same memory cell group GP1, GP2 can be effectively eliminated, and then the short circuit phenomenon between the memory cell groups GP1, GP2 can be tested. At this time, the switch element 120 can be combined with the on and off states of the source line switches SLT211~SLT218 and SLT221~SLT228 to make one of the regional source lines SL21_1~SL21_8 arranged at the edge of the memory cell subgroup GP21 a common source voltage (0 volts), and make one of the regional source lines SL22_1~SL22_8 arranged at the edge of the memory cell subgroup GP22 a common source voltage (0 volts). The switch element 120 can also make the regional source lines SL11_1 to SL11_8 and SL12_1 to SL12_8 be in a floating state. At this time, with the on and off states of the bit line switches BLT111~BLT118 and BLT121~BLT128 and the on states of the selection switches SSW11 and SSW12, one of the regional bit lines BL11_1~BL11_8 arranged at the edge of the memory cell group GP11 can be coupled to the common bit line GBL11, and one of the regional bit lines BL12_1~BL12_8 arranged at the edge of the memory cell group GP12 can be coupled to the common bit line GBL11, and coupled to the sense amplifiers SA1 and SA2 through the selection switches SSW11 and SSW12 respectively.

In this way, the sense amplifier SA1 can detect whether there is a short circuit between the regional bit lines BL11_1~BL11_8 in the memory cell subgroup GP11 and the regional source lines SL21_1~SL21_8 in the memory cell subgroup GP21 by sensing whether there is a leakage current on the common bit line GBL11. The sense amplifier SA2 can detect whether there is a short circuit between the regional bit lines BL12_1~BL12_8 in the memory cell subgroup GP12 and the regional source lines SL22_1~SL22_8 in the memory cell subgroup GP22 and the regional source lines SL21_1~SL21_8 in the memory cell subgroup GP21 by sensing whether there is a leakage current on the common bit line GBL12.

In other words, the short circuit between the adjacent memory cell groups GP1 and GP2 can also be effectively detected. And the memory cell string with the short circuit can be replaced to effectively eliminate the error state.

Please refer to Figure 2 below, which shows a schematic diagram of the architecture of the memory device of an embodiment of the present invention. The memory device 200 is a three-dimensional stacked memory, having a memory cell area AC, a bit line switch BLT, a source line switch SLT and a switching element 210. The memory cell area AC is used to set up a plurality of memory cells and form a memory cell array. The bit line switch BLT and the source line switch SLT are a plurality of transistor switches. The switching element 210 has switches SW1 and SW2, which are also transistor switches. Among them, the switch SW1 has a gate structure GS1, one end of the switch SW1 is coupled to the common bit line CSL, and the other end of the switch SW1 can be coupled to the source line GSL_n+1. The source line GSL_n+1 is coupled to a portion of the multiple source line switches SLT. The switch SW2 has a gate structure GS2, one end of the switch SW2 is coupled to the common bit line CSL, and the other end of the switch SW2 can be coupled to the source line GSL_n. The source line GSL_n is coupled to the remaining multiple source line switches SLT.

The gate structure GS1 receives the test mode signal CT1, and the gate structure GS2 receives the test mode signal CT2. The switches SW1 and SW2 can be turned on or off according to the test mode signals CT1 and CT2, respectively. When the switch SW1 is turned on, the source line GSL_n+1 can be coupled to the common source line CSL, and when the switch SW2 is turned on, the source line GSL_n can be coupled to the common source line CSL. In this embodiment, in the test mode, one of the switches SW1 and SW2 can be turned on, and the other can be turned off.

Incidentally, in the memory device 200, the common bit line GBL_n can be coupled to a portion of the multiple bit line switches BLT, and the common bit line GBL_n+1 can be coupled to the remaining multiple bit line switches BLT.

Please refer to FIG. 3 and FIG. 4A to FIG. 4C below, wherein FIG. 3 illustrates a test flow chart of a memory device according to an embodiment of the present invention, and FIG. 4A to FIG. 4C illustrate a test action schematic diagram of a memory device according to an embodiment of the present invention. In FIG. 3, in step S310, corresponding to FIG. 4A, the switch SW1 connected to the regional source line SLj is disconnected, and the regional source line SLj is floated. The regional source line SLj and the common bit line BLj are coupled to the same memory cell. The switch SW2 connected to the regional source line SLi is turned on, and the regional source line SLi is coupled to the common source line CSL to receive a common source voltage (e.g., 0 volts). The sense amplifier SA2 can perform a read test on the common bit line BLi, and when a leakage current is detected on the common bit line BLi, it indicates that the test has failed, and that there is a short circuit between the regional source line SLi and the bit line corresponding to the common bit line BLi.

When the test fails, the memory cell string of the short-circuited regional source line SLi can be replaced.

If the test result of step S310 is passed, step S320 can be executed.

In step S320, corresponding to FIG. 4B , the switch SW2 connected to the regional source line SLi is turned off, and the regional source line SLi is floated. The switch SW1 connected to the regional source line SLj is turned on, and the regional source line SLj is coupled to the common source line CSL to receive the common source voltage (e.g., 0 volts). The sense amplifier SA1 can perform a read test on the common bit line BLj, and when a leakage current is detected on the common bit line BLj, it indicates that the test fails, and indicates that there is a short circuit between the regional source line SLj and the bit line corresponding to the common bit line BLj.

When the test fails, the memory cell string with the short-circuited regional source line SLj can be replaced.

If the test result of step S320 is passed, step S330 can be executed.

In step S330, corresponding to FIG. 4C, the switch SW2 connected to the regional source line SLi is disconnected, and the regional source line SLi is floated. The switch SW1 connected to the regional source line SLj is turned on, and the regional source line SLj is coupled to the common source line CSL to receive the common source voltage (e.g., 0 volts). The sense amplifier SA2 can perform a read test on the common bit line BLi, and when a leakage current is detected on the common bit line BLi, it indicates that the test fails, and indicates that there is a short circuit between the regional source line SLj and the bit line corresponding to the common bit line BLi.

When the test fails, the memory cell string with the short-circuited regional source line SLi can be replaced.

If the result of step S330 is passed, it means that the circuit short circuit test of the memory device has passed.

Please refer to FIG. 5 below, which shows a schematic diagram of a memory cell structure of a memory device of an embodiment of the present invention. In the embodiment of the present invention, a plurality of memory cells MCS in the memory device are constructed in a stacked manner to form a memory cell string with a three-dimensional structure. Each memory cell may have a silicon oxide-silicon nitride-silicon oxide layer ONO as an insulating layer. It also has a channel structure CH and a gate structure GS. The regional bit line BL and the regional source line SL are connected to all memory cells MCS in the memory cell string through conductive pins PG1 and PG2, respectively.

Please refer to FIG. 6, which is a flow chart of a memory device testing method according to an embodiment of the present invention. In step S610, a memory cell array is divided into a first memory cell group and a second memory cell group, wherein the first memory cell group has a plurality of first regional bit lines and a plurality of first regional source lines, and the second memory cell group has a plurality of second regional bit lines and a plurality of second regional source lines. In step S620, a first common bit line and a second common bit line are coupled to a first sense amplifier and a second sense amplifier, respectively, wherein the first common bit line is coupled to the first regional bit line, and the second common bit line is coupled to the second regional bit line. Furthermore, in step S630, a switch element is set between the first regional source line, the second regional source line and the common source line. And, in step S640, in different multiple test modes, the first regional source line is coupled to the common source line, or the second regional source line is coupled to the common source line.

The details of the above steps have been described in detail in the aforementioned embodiments, so I will not elaborate on them here.

In summary, the memory device of the present invention sets a switch element between a common source line and a plurality of regional source lines. In the test mode, the switch element is used to float the regional source line in one memory cell group and couple the regional source line in another memory cell group to the common source line. In addition, by performing a read operation on the common bit line through the sense amplifier corresponding to different memory cell groups, it is possible to detect whether there is a short circuit between the regional source line and the regional bit line in the same or adjacent memory cell group according to whether there is leakage current on the common bit line, and maintain the normal operation of the memory cell array.

100: Memory device 110: Memory cell array 120: Switching element BL11_1~BL22_8: Regional bit line BLT111~BLT228: Bit line switch CSL: Common source line CT1, CT2: Test mode signal GBL11~GBL22: Common bit line GP1, GP2: Memory cell group GP1, GP12, GP21, GP22: Memory cell subgroup MC: Memory cell SA1, SA2: Sense amplifier SL11_1~SL22_8: Regional source line SLT111~SLT228: Source line switch SSW11, SSW12, SSW21, SSW22: Select switch SW1, SW2: switches WL1~WLN: character lines

Claims (16)

A memory device includes: a memory cell array, divided into a first memory cell group and a second memory cell group, the first memory cell group having a plurality of first regional bit lines and a plurality of first regional source lines, the second memory cell group having a plurality of second regional bit lines and a plurality of second regional source lines; a first common bit line and a second common bit line, respectively coupled to a first sense amplifier and a second sense amplifier, the first common bit line coupled to the first regional bit lines, the second common bit line coupled to the second regional source lines, The first regional source lines are coupled to the second regional bit lines; and a switch element is coupled between the first regional source lines, the second regional source lines and a common source line, and is used to couple the first regional source lines to the common source line or couple the second regional source lines to the common source line in different test modes, wherein in a first test mode, the switch element couples the first regional source lines to the common source line and cuts off the coupling relationship between the second regional source lines and the common source line. A memory device as described in claim 1, wherein in the first test mode, the first sense amplifier tests whether a short circuit occurs between each of the first regional source lines and each of the first regional bit lines. A memory device as described in claim 1, wherein in a second test mode, the switch element couples the second regional source lines to the common source line and cuts off the coupling relationship between the first regional source lines and the common source line. A memory device as described in claim 3, wherein in the second test mode, the second sense amplifier tests whether a short circuit occurs between each of the second regional source lines and each of the second regional bit lines. A memory device as described in claim 3, wherein in a third test mode, the switch element couples the second regional source lines to the common source line and cuts off the coupling relationship between the first regional source lines and the common source line, and the second sense amplifier tests whether a short circuit occurs between each of the first regional source lines and each of the second regional bit lines. A memory device as described in claim 1, wherein the switch element comprises: a first switch having a first end coupled to the first regional source lines, and a second end coupled to the common source line; and a second switch having a first end coupled to the second regional source lines, and a second end coupled to the common source line, wherein the first switch and the second switch are controlled by a first test mode signal and a second test mode signal, respectively. The memory device as described in claim 1 further comprises: a plurality of first bit line switches coupled between the first common bit line and the first regional bit lines; and a plurality of second bit line switches coupled between the second common bit line and the second regional bit lines. The memory device as described in claim 7 further includes: a first selection switch coupled between the first common bit line and the first sense amplifier; and a second selection switch coupled between the second common bit line and the second sense amplifier. The memory device as described in claim 1 further comprises: a plurality of first source line switches coupled between the switch element and the first regional source lines; and a plurality of second source line switches coupled between the switch element and the second regional source lines. A memory device as described in claim 1, wherein in the test modes, the first memory cell group and the plurality of memory cells in the second memory cell group are in an access-prohibited state. A test method for a memory device includes: dividing a memory cell array into a first memory cell group and a second memory cell group, wherein the first memory cell group has a plurality of first regional bit lines and a plurality of first regional source lines, and the second memory cell group has a plurality of second regional bit lines and a plurality of second regional source lines; coupling a first common bit line and a second common bit line to a first sense amplifier and a second sense amplifier, respectively, wherein the first common bit line is coupled to the first regional bit lines, The second common bit line is coupled to the second regional bit lines; a switch element is disposed between the first regional source lines, the second regional source lines and a common source line; in different test modes, the first regional source lines are coupled to the common source line, or the second regional source lines are coupled to the common source line; and in a first test mode, the switch element couples the first regional source lines to the common source line and cuts off the coupling relationship between the second regional source lines and the common source line. The test method as described in claim 11 further includes: in the first test mode, the first sense amplifier is used to test whether a short circuit occurs between each of the first regional source lines and each of the first regional bit lines. The test method as described in claim 11 further includes: in a second test mode, the switch element couples the second regional source lines to the common source line and cuts off the coupling relationship between the first regional source lines and the common source line. The test method as described in claim 13 further includes: in the second test mode, the second sense amplifier is used to test whether a short circuit occurs between each second regional source line and each second regional bit line. The test method as described in claim 13 further includes: In a third test mode, the switch element couples the second regional source lines to the common source line and cuts off the coupling relationship between the first regional source lines and the common source line; and the second sense amplifier tests whether there is a short circuit between each of the first regional source lines and each of the second regional bit lines. The test method as described in claim 11 further includes: in the test modes, the first memory cell group and the plurality of memory cells in the second memory cell group are all in a closed state.

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