JP2006512776A5

JP2006512776A5 -

Info

Publication number: JP2006512776A5
Application number: JP2004565772A
Authority: JP
Filing date: 2003-12-29
Publication date: 2007-02-22

Claims

An integrated circuit comprising a memory array having at least one surface of a memory cell formed above a substrate, the memory cell including a variable conductance switch device disposed in a plurality of series connected NAND strings. Integrated circuit.

The integrated circuit of claim 1, wherein the memory array comprises a three-dimensional memory array in which at least two sides of the memory cells are formed above the substrate.

The integrated circuit of claim 1, wherein the variable conductance switch device includes a transistor having a charge storage dielectric.

4. The integrated circuit of claim 3, wherein the charge storage dielectric of the memory cell transistor comprises an oxide-nitride-oxide (ONO) stack.

The integrated circuit of claim 1, wherein each column includes a first switch device for coupling the column to an associated global array line at a first end thereof.

6. The integrated circuit of claim 5, wherein two NAND columns having a common word line share a global array line.

6. The integrated circuit of claim 5, wherein each NAND string includes a second switch device for coupling the string to an associated bias node at a second end opposite the first end.

8. The NAND column pair is arranged such that a first control signal coupling one column of the pair to an associated global array line couples the other column of the pair to an associated bias node. An integrated circuit as described.

6. The integrated circuit of claim 5, wherein the first switch device in each column of memory cells includes a transistor having a charge storage dielectric.

The integrated circuit of claim 9, wherein the first switch device in each column of memory cells has a depletion mode threshold voltage.

6. The integrated circuit of claim 5, wherein the memory cell devices and switch devices forming each NAND string are substantially the same in structure.

The integrated circuit of claim 2, wherein NAND strings on two or more memory levels are each coupled to a global array line disposed on a level less than the two or more memory levels.

The integrated circuit of claim 2, wherein each of the plurality of NAND columns on each of the at least two memory levels is coupled to a global array line disposed on one level of the integrated circuit.

The integrated circuit of claim 13, wherein at least two NAND columns on each of the at least two memory planes contact an associated global array line by a shared thread.

Comprising a memory array in which at least one surface of a memory cell is arranged in a plurality of NAND columns connected in series;
Each NAND string includes, at one end thereof, a first switch device for coupling the respective NAND string to an associated global array line, and at the other end, each NAND string at an associated bias node. A second switch device for coupling
The first switch device for the first NAND string and the second switch device for the second NAND string are responsive to the first control signal and the second switch device and the second NAND for the first NAND string A first switch device for the column is responsive to the second control signal;
An integrated circuit in which the first and second NAND strings share a word line in common.

16. The integrated circuit of claim 15, wherein the memory array includes a three-dimensional memory array in which two or more faces of memory cells are formed above the substrate.

The integrated circuit of claim 15, wherein the memory cell includes a transistor having a charge storage dielectric.

The integrated circuit of claim 15, wherein the first and second switch devices of a given NAND string are substantially the same in structure as the memory cell transistors of the given NAND string.

The memory array is arranged in a plurality of blocks, and a first memory block of the plurality of memory blocks is:
A first bias node;
A second bias node;
A plurality of global bit lines across the first block in a first direction;
A plurality of word lines crossing the first block in a second direction different from the first direction;
A first block selection line that is substantially parallel to one side of the plurality of word lines and disposed on the one side and that crosses the first block;
A second block selection line across the first block and disposed substantially parallel to the other side of the plurality of word lines and on the other side;
A first block select device responsive to a first block select line, a plurality of memory cell devices each responsive to a respective one of the plurality of word lines, and a second responsive to a second block select line A plurality of series connected NAND strings including two block selection devices;
Each first block selection device of each of the first group of NAND columns is coupled to a respective one of the plurality of global bit lines, and each first block selection device of each of the second group of NAND columns is Each coupled to a first bias node;
Each second block selection device of each of the first group of NAND strings is coupled to a second bias node, respectively, and each second block selection device of each of the second group of NAND strings includes a plurality of global bits. The integrated circuit of claim 15, each coupled to a respective one of the lines.

A pair of NAND strings are coupled to the same global bit line, each of such pairs including a NAND string from each of the first and second groups of NAND strings, thereby globally half the pitch of the NAND string. 20. The integrated circuit of claim 19, wherein the integrated circuit defines a bit line pitch.

20. The integrated circuit of claim 19, wherein two or more physically adjacent NAND strings of the first memory block share a contact to the first or second bias node.

The memory array includes a three-dimensional memory array having two or more memory levels formed above the substrate, the integrated circuit further comprising:
A third memory block disposed on a level of a memory array different from the first memory block, wherein the first and third memory blocks include a plurality of global bit lines, a first bias node, and a first memory block; Each of the third memory blocks share two bias nodes.
A third plurality of word lines across the block in a second direction;
A fifth block select line across the block, substantially parallel to one side of the third plurality of word lines and disposed on the one side;
A sixth block selection line across the block, substantially parallel to the other side of the third plurality of word lines and disposed on the other side;
Responsive to a first block select device, each responsive to a fifth block select line, a plurality of memory cell devices each responsive to a respective one of a third plurality of word lines, and a sixth block select line A third plurality of series connected NAND strings each including a second block selection device that
Each of the first block selection devices of each of the first group of third plurality of NAND strings is coupled to a respective one of the plurality of global bit lines, respectively, and second group of third plurality of NANDs Each of the first block selection devices in each of the columns is respectively coupled to a first bias node;
Each of the second block selection devices in each of the first group of third plurality of NAND strings is coupled to a second bias node, respectively, and each of the second group of third plurality of NAND strings. The integrated circuit of claim 19, wherein each of the second block selection devices is coupled to a respective one of the plurality of global bit lines.

23. The integrated circuit of claim 22, wherein each NAND string of the first memory block contacts an associated global bit line by a via shared by a corresponding NAND string of the third memory block.

The integrated circuit of claim 19, wherein the memory cell device comprises a transistor having a charge storage dielectric.

25. The integrated circuit of claim 24, wherein the first and second block selection devices of a given NAND string are structurally the same as the memory cell transistors of the given NAND string.