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TWI762058B - 半導體封裝件 - Google Patents

半導體封裝件 Download PDF

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Publication number
TWI762058B
TWI762058B TW109142356A TW109142356A TWI762058B TW I762058 B TWI762058 B TW I762058B TW 109142356 A TW109142356 A TW 109142356A TW 109142356 A TW109142356 A TW 109142356A TW I762058 B TWI762058 B TW I762058B
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TW
Taiwan
Prior art keywords
chip
layer
flexible
back surface
carrier
Prior art date
Application number
TW109142356A
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English (en)
Other versions
TW202224507A (zh
Inventor
余俊賢
許詩濱
蔡憲銘
Original Assignee
恆勁科技股份有限公司
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Publication date
Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW109142356A priority Critical patent/TWI762058B/zh
Priority to US17/536,158 priority patent/US11749612B2/en
Priority to CN202111446925.5A priority patent/CN114582829A/zh
Application granted granted Critical
Publication of TWI762058B publication Critical patent/TWI762058B/zh
Publication of TW202224507A publication Critical patent/TW202224507A/zh

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Abstract

一種半導體封裝件包括一可撓式載板、一第一晶片、一第二晶片、一第一模封層、一第一黏合層以及一第二模封層。可撓式載板包括一具有圖案化增層線路且呈軟性之可撓折層，以及結合於該可撓折層部分表面上之剛性層。可撓折層結合有剛性層之部位形成為一第一承載部及一第二承載部，而該第一承載部及該第二承載部間未結合有剛性層之該可撓折層形成為一第一可撓折部。第一晶片係覆晶接置於第一承載部上，第二晶片係覆晶接置於第二承載部上。第一模封層包覆第一晶片，第二模封層包覆第二晶片。第一黏合層結合第一模封層與第二承載部。

Description

半導體封裝件
本發明是有關於一種半導體封裝件，且特別是有關於一種系統整合封裝件之封裝結構。
科技日新月異，半導體晶片(die)已廣泛使用於日常生活中。而隨著半導體製程以及封裝技術之演進，晶片之尺寸得以逐漸縮小，並且，由複數個晶片或其他元件所組成之系統得以整合於單一封裝之中，此即為「系統整合封裝」(system in package,SIP)。於現有技術之各式系統整合封裝件中，係具有不同態樣之封裝結構，例如：二維式(2-dimension,2D)封裝結構、二點五維式(2.5-dimension,2.5D)封裝結構、層疊式(package on package,POP)封裝結構以及三維式(3-dimenison,3D)封裝結構，等等。
第1A圖及第1B圖分別為現有技術之二維式封裝件1之封裝結構之俯視示意圖及剖面示意圖。如第1A圖所示，二維式封裝件1之中，以水平方向(沿著連接線AA’之方向)設置複數個晶片14-1~14-5。換言之，晶片14-1~14-5位於同一平面，並設置於同一載板10上；晶片14-1~14-5並連同載板10一併設置於電路板15(例如：印刷電路板)上。
更進一步而言，如第1B圖(沿第1A圖中連接線AA’之剖面圖)所示，晶片14-1及晶片14-2(連接線AA’之剖面未包含晶片14-3~14-5)經由錫球131設置於載板10上，而載板10設置於電路板15上。由於載板10必須同時承載晶片14-1~14-5(第1B圖僅圖示出晶片14-1及晶片14-2)，載板10於水平方向必須具有較大之長度w1，因而導致二維式封裝件1之封裝體積過大。此外，為了將晶片14-1~14-5之訊號進行跨晶片傳輸，載板10之導電層11之各部分於水平方向之長度(特別是導電層11之一部分111之長度w2)亦須增加， 而導致功耗上升。再者，由於同時承載兩個以上之晶片14-1~14-5，載板10容易產生翹曲而導致良率下降。上述為現有技術之二維式封裝件1之技術問題。
第2A圖及第2B圖分別為現有技術之二點五維式封裝件2之封裝結構之俯視示意圖及剖面示意圖。如第2A圖所示，二點五維式封裝件2更設置一矽中介層16以增加整體之剛性，其設置於晶片14-1~14-5與載板10之間。
更進一步而言，如第2B圖(沿第2A圖中連接線AA’之剖面圖)所示，矽中介層16設置於晶片14-1及晶片14-2(連接線AA’之剖面未包含晶片14-3~14-5)與載板10之間，並包含複數個導電柱17。
晶片14-1與晶片14-2經由錫球132設置於矽中介層16上，並電性連接於導電柱17，進而轉接至載板10。經由矽中介層16之轉接，能夠放大晶片14-1與晶片14-2之電性連接墊(pad)之等效面積，例如：將晶片14-2之電性連接墊142之寬度w3等效放大至寬度w4。然而，額外設置矽中介層16將導致額外之材料成本及封裝工序，此為現有技術之二點五維式封裝件2之技術問題。
第3A圖及第3B圖分別為現有技術之層疊式封裝件3之封裝結構之俯視示意圖及剖面示意圖。如第3A圖所示，層疊式封裝件3包含兩個載板10與18，並以垂直方向設置複數個晶片14-1~14-3。其中，晶片14-2與14-3層疊設置於載板18上；而晶片14-1則設置於載板10上，並位於載板18下方。
更進一步而言，如第3B圖(沿第3A圖中連接線AA’之剖面圖)所示，晶片14-1與晶片14-2皆以覆晶(flip-chip)方式而分別設置於載板10與載板18上；其中，晶片14-1之電性連接墊141經由錫球133而電性連接至載板10上，而晶片14-2之電性連接墊142則經由錫球134而電性連接至載板18上。另一方面，晶片14-3經由黏合層19而設置於晶片14-2上，並且晶片14-3之電性連接墊143以打線工序而經由引線20電性連接至載板18上。經由上述方式，晶片14-1~14-3於垂直方向層疊設置；然而，上述之層疊設置方式將導 致晶片14-1~14-3散熱困難而產生高溫。
此外，由於晶片14-1佔據了載板18下方之部分空間，致使載板18必須增加額外寬度w5以設置錫球135，以利載板18之輸入/輸出埠(I/O)之導出，進而電性連接至載板10。然而，錫球135之尺寸遠大於錫球133與錫球134，其增加了封裝之困難度；並可能因載板18及載板10之不當翹曲，而導致錫球135與載板18及載板10之接點136發生斷裂或分離。上述為現有技術之層疊式封裝件3之技術問題。
另一方面，第3C圖為現有技術之另一種態樣之層疊式封裝件3a之封裝結構之剖面示意圖。如第3C圖所示，於層疊式封裝件3a之中，係以導電柱137(例如：銅柱)取代錫球135而作為載板18與載板10之間的電性連接路徑。然而，導電柱137亦無可避免的增加了層疊式封裝件3a之橫向面積(水平方向之面積)，此為現有技術之層疊式封裝件3a之技術問題。
第4A圖及第4B圖分別為現有技術之三維式封裝件4之封裝結構之俯視示意圖及剖面示意圖。如第4A圖所示，三維式封裝件4之中，先於矽中介層16上以水平方向設置晶片14-1與晶片14-2。而後，以相對於晶片14-1之垂直方向設置晶片14-3，並以相對於晶片14-2之垂直方向分別設置晶片14-4與晶片14-5。
更進一步而言，如第4B圖(沿第4A圖中連接線AA’之剖面圖)所示，於晶片14-1與晶片14-2之中分別以矽穿孔工序(through-silicon via,TSV)設置或形成導電柱21，以使晶片14-3經由導電柱21直接電性連接於晶片14-1，並使晶片14-4與晶片14-5經由導電柱21直接電性連接於晶片14-2。經由上述方式，上層晶片14-3、14-4與14-5得以直接層疊設置於下層晶片14-1與14-2上，因而無需設置第3B圖所示之載板18。然而，因應於矽穿孔工序以設置導電柱21，晶片14-1與晶片14-2之內部電路布局必須重新設計；此舉增加了晶圓製程之工序與成本，亦增加了封裝流程之複雜度而影響良率。上述為現有技術之三維式封裝件4之技術問題。
有鑑於現有技術中各式封裝件所存在之上述技術問 題，需提出一種改良之封裝結構，其能具備三維層疊設置方式之空間利用度，亦能兼顧封裝件之整體剛性與封裝流程之精簡度，係為本發明之目的。
因此，本發明之目的係提供一種具有改良式層疊封裝結構的封裝件，其能兼備空間利用度、整體結構剛性以及封裝流程精簡度。
為達上述目的，本發明提供一種半導體封裝件，包含一可撓式載板、一第一晶片、一第二晶片、一第一模封層、一第一黏合層以及一第二模封層。可撓式載板係包括一具有圖案化增層線路且呈軟性之可撓折層，以及結合於該可撓折層部分表面上之剛性層；該可撓折層結合有剛性層之部位形成為一第一承載部及一第二承載部，而該第一承載部及該第二承載部間未結合有剛性層之該可撓折層形成為一第一可撓折部。第一晶片係具有一主動面以及相對之一背面，且以該主動面側覆晶接置於該第一承載部上。第一模封層係設置於該第一承載部上，並包覆該第一承載部及該第一晶片。第一黏合層係設置於該第一模封層上，以供該第二承載部結合於該第一模封層上，其中連接該第二承載部及該第一承載部之第一可撓折部至少彎折180°。第二晶片具有一主動面以及相對之一背面，且以該主動面側覆晶接置於該第二承載部上。第二模封層係設置於該第二承載部上，並包覆該第二承載部及該第二晶片。
於一實施例中，第一承載部及第二承載部係藉由載板內之圖案化增層線路而電性連接。
於一實施例中，第一承載部之下方係電性連接於一電路板。
於一實施例中，半導體封裝件更包含一第六晶片，其係嵌埋於第一模封層內，且具有一主動面以及相對之一背面。第六晶片以該背面經由一第四黏合層結合於第一晶片之背面，其中第六晶片之主動面以引線電性連接於第一承載部。
於一實施例中，半導體封裝件更包含一第三晶片，其係嵌埋於該第二模封層內，且具有一主動面以及相對之一背面，該第三晶片以該背面經由一第二黏合層結合於該第二晶片之背面，其中該第三晶片之該主動面係以引線電性連接於該第二承載部。
於一實施例中，半導體封裝件之該可撓式載板更包括有一第二可撓折部及一第三承載部。第二可撓折部僅具有可撓折層，第三承載部具有可撓折層及剛性層。第三承載部係經由第二可撓折部連接於第二承載部，並且第三承載部與第一承載部係設置於同一平面。另外，半導體封裝件更包括一第四晶片以及一第三模封層。第四晶片係具有一主動面以及相對之一背面，且以該主動面覆晶接置於該第三承載部上。第三模封層係設置於第三承載部上，並包覆該第三承載部及該第四晶片。
於一實施例中，第一承載部、第二承載部及第三承載部係藉由該可撓式載板內之該圖案化增層線路而電性連接。
於一實施例中，第三承載部之下方係電性連接於一電路板。
於一實施例中，半導體封裝件更包含一第五晶片，其係嵌埋於該第三模封層內，且具有一主動面以及相對之一背面。第五晶片係以該背面經由一第三黏合層結合於該第四晶片之該背面。並且第五晶片之該主動面係以引線電性連接於該第三承載部。
1~4:封裝件
5,6,6a:半導體封裝件
10,18:載板
30,30a:可撓式載板
11,W01~W04:導電層
111:導電層之一部分
131~135,361~365:錫球
136:接點
14-1~14-5,37-1~37-6:晶片
141~143,371~375:電性連接墊
3711,3721,3731,3741,3751:主動面
3722,3732:背面
15,45,45a:電路板
16:矽中介層
17,21,137,P01~P06:導電柱
19,40,41,55:黏合層
20,38,56:引線
31:可撓折層
311:圖案化增層線路
32:剛性層
321:第一剛性層
322:第二剛性層
33:第一承載部
331:第一承載部之第一側
332:第一承載部之第二側
34:第二承載部
341:第二承載部之第一側
342:第二承載部之第二側
35:第一可撓折部
42,43,48,48a:模封層
46:第二可撓折部
47:第三承載部
471:第三承載部之第一側
51:底層封裝部
52:上層封裝部
53,53a:側向封裝部
w1,w2,w6,w7:長度
w3,w4,w5:寬度
AA’:連接線
〔第1A圖〕及〔第1B圖〕分別為現有技術之二維式封裝件之封裝結構之俯視示意圖及剖面示意圖。
〔第2A圖〕及〔第2B圖〕分別為現有技術之二點五維式封裝件之封裝結構之俯視示意圖及剖面示意圖。
〔第3A圖〕及〔第3B圖〕分別為現有技術之層疊式封裝件之封裝結構之俯視示意圖及剖面示意圖。
〔第3C圖〕為現有技術之另一種態樣之層疊式封裝件之封裝結構之剖面示意圖。
〔第4A圖〕及〔第4B圖〕分別為現有技術之三維式封裝件之封裝結構之俯視示意圖及剖面示意圖。
〔第5A圖〕為本發明之第一實施例之半導體封裝件之俯視示意圖。
〔第5B圖〕為本發明之第一實施例之半導體封裝件之可撓式載板之剖面示意圖。
〔第5C圖〕為本發明之第一實施例之半導體封裝件之剖面示意圖。
〔第5D圖〕為本發明之第一實施例之半導體封裝件，於底層封裝部及上層封裝部皆以背對背方式設置兩個晶片之剖面示意圖。
〔第6A圖〕為本發明之第二實施例之半導體封裝件之俯視示意圖。
〔第6B圖〕為本發明之第二實施例之半導體封裝件之可撓式載板之剖面示意圖。
〔第6C圖〕為本發明之第二實施例之半導體封裝件之剖面示意圖。
〔第6D圖〕為本發明之第二實施例之另一實施態樣之半導體封裝件之剖面示意圖。
為了使所屬技術領域中具有通常知識者能瞭解本發明的內容，並可據以實現本發明的內容，茲配合適當實施例及圖式說明如下。
第5A圖至第5C圖分別為本發明之第一實施例之半導體封裝件5之封裝結構之俯視示意圖及剖面示意圖。如第5A圖所示，半導體封裝件5係設置於一電路板45上，並以可撓折或可彎曲之可撓式載板30取代現有技術之硬式載板(例如：取代第3A圖所示之載板10與載板18)。
如第5B圖所示，該可撓式載板30主要係包括一具有圖案化增層線路311且呈軟性之可撓折層31、及結合於該可撓折層 31部分表面上之剛性層32；其中該可撓折層31結合有剛性層32的部位可形成為一第一承載部33及一第二承載部34，而該第一承載部33及該第二承載部34間未結合有剛性層32之該可撓折層31形成為一第一可撓折部35。再進一步說明，剛性層32還包括一第一剛性層321以及一第二剛性層322，其係分別設置於可撓折層31相對之表面。
於本實施例中，第一承載部33及第二承載部34為不可撓折而具有相當的剛性，使能於水平方向呈現平坦之態樣，以利於晶片之覆晶結合。第一可撓折部35則呈現180度之彎折，以使第二承載部34能翻轉設於第一承載部33之上方，並使第二承載部34平行於第一承載部33。同時參照第5A圖，第二承載部34經由第一可撓折部35而連接於第一承載部33，且第二承載部34係位於第一承載部33之上方。
第一承載部33具有對向設置之一第一側331與一第二側332，並且第二承載部34亦具有對向設置之一第一側341與一第二側342。經由第一可撓折部35之反向撓折，以使第二承載部34之第二側342面向第一承載部33之第一側331。
圖案化增層線路311包括有複數層導電層W01~W04以及複數個導電柱P01~P04。導電層W01~W04為具有預定電路圖案之圖案化(patterned)導電層，其作為水平方向之電性連接路徑與訊號傳輸路徑。導電柱P01~P04則作為垂直方向之電性連接路徑與訊號傳輸路徑。
第一剛性層321與第二剛性層322之材質例如為FR4玻璃纖維之介電質材料，其可具有傳統硬式電路板之基板之功能，以提供足夠的支撐力以承載包括晶片的主、被動電子元件。
再同時參閱第5C圖所示(沿第5A圖中連接線AA’之剖面圖)，半導體封裝件5還包括第一晶片37-1、第二晶片37-2、第三晶片37-3、複數模封層42及43、以及複數黏合層40及41。
第一晶片37-1、第二晶片37-2以及第三晶片37-3係分別設置於可撓式載板30之不同部位或不同之相對位置。採用本實 施例之可撓式載板30，其亦能以層疊方式於三維方向對於第一晶片37-1、第二晶片37-2以及第三晶片37-3進行設置，而能夠有效利用空間。第一晶片37-1設置於可撓式載板30之第一承載部33與第二承載部34之間。詳言之，第一晶片37-1之主動面3711朝下，而以覆晶方式接置於第一承載部33之第一側331。其中，設置於主動面3711之電性連接墊(pad)371(或稱金屬墊或金屬電極墊)經由錫球(solder bump)361(或稱錫鉛凸塊)而固定設置於第一剛性層321上，並進一步電性連接至第一承載部33內部之導電柱P01，進而電性連接至第一承載部33內部之導電層W01~W04。
模封層42設置於第一承載部33之上，該模封層42形成於第一承載部33之第一側331之第一剛性層321上，並完整包覆第一晶片37-1以及錫球361。模封層42可經由鑄模工序(molding)而形成，其材質為鑄模化合物(molding compound)，例如：酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)。此外，黏合層40設置或形成於模封層42之上，以供該第二承載部34能以其第二側342而結合於模封層42上。
承上，可撓式載板30之第一承載部33、第一晶片37-1及模封層42組成半導體封裝件5之底層封裝部51。底層封裝部51並經由錫球363而設置於電路板45上。意即，底層封裝部51係由第一承載部33之第二側332經由錫球363連接於電路板45。
另一方面，第二晶片37-2與第三晶片37-3於垂直方向以層疊方式設置於第二承載部34上。其中，第二晶片37-2之主動面3721朝下，而以覆晶方式接置於第二承載部34之第一側341。設置於主動面3721之電性連接墊372係經由錫球362而電性連接至第二承載部34內部之導電柱P02，進而電性連接至第二承載部34內部之導電層W01~W04。換言之，第二晶片37-2之主動面3721以覆晶方式電性連接於第二承載部34之第一側341。
此外，第三晶片37-3之主動面3731朝上，並且其背面3732經由黏合層41而結合於第二晶片37-2之背面3722。換言之，第 二晶片37-2與第三晶片37-3係以背對背(back to back)方式於垂直方向進行層疊設置。設置於第三晶片37-3之主動面3731之電性連接墊373更以打線方式而經由引線38電性連接至第二承載部34內部之導電柱P03，進而電性連接至第二承載部34內部之導電層W01~W04。換言之，第三晶片37-3之主動面3731以打線方式電性連接於第二承載部34之第一側341。
模封層43經由鑄模工序而形成，其材質亦為鑄模化合物。模封層43形成於第二承載部34之第一側341之第二剛性層322上，並完整包覆第二晶片37-2、第三晶片37-3、引線38以及錫球362。
承上，可撓式載板30之第二承載部34、第二晶片37-2、第三晶片37-3及模封層43組成半導體封裝件5之上層封裝部52。上層封裝部52經由第一可撓折部35而電性連接於底層封裝部51。因此，上層封裝部52與底層封裝部51之間的訊號傳遞可經由第一可撓折部35內部之導電層W2、W3而完成，也相當於係經由圖案化增層線路311而完成。換言之，於本實施例中，係以可撓式載板30之第一可撓折部35取代現有技術之錫球或導電柱(例如：取代第3B圖所示之錫球135，或第3C圖所示之導電柱137)，而作為上層封裝部52與底層封裝部51之間的電性連接路徑及訊號傳輸路徑。
由於第二承載部34與第一承載部33之間的空間無須設置錫球或導電柱(該空間可完全提供予晶片37-1之設置)，而能夠縮小可撓式載板30於水平方向之長度w6，進而縮小半導體封裝件5之封裝體積。此外，本實施例係以黏合層40將上層封裝部52穩固地連接於底層封裝部51，因而能夠提高半導體封裝件5之整體結構強度。上述為本發明之第一實施例之技術功效。
此外，值得一提的是，於第5C圖中，底層封裝部51係設置一個第一晶片37-1，並且上層封裝部52係設置第二晶片37-2及第三晶片37-3。然而於其他實施態樣中，亦可設置其他數量之晶片，例如：底層封裝部51於第一晶片37-1上更以背對背方式設置另一第六晶片37-6，而上層封裝部52僅設置一個第二晶片37-2。或者 如第5D圖所示，於底層封裝部51及上層封裝部52皆以背對背方式設置兩個晶片。
第6A圖至第6C圖分別為本發明之第二實施例之半導體封裝件6之封裝結構之俯視示意圖及剖面示意圖。如第6A圖所示，相較於第一實施例之半導體封裝件5，除了第一承載部33、第一可撓折部35以及第二承載部34之外，本實施例之半導體封裝件6之可撓式載板30a更包含一第二可撓折部46以及一第三承載部47。此外，除了第一晶片37-1、第二晶片37-2以及第三晶片37-3之外，本實施例之半導體封裝件6更包含一第四晶片37-4，其設置於第三承載部47上。
如第6B圖所示，可撓式載板30a係進一步延伸而形成第二可撓折部46以及第三承載部47，因此，相較於第一實施例之可撓式載板30，本實施例之可撓式載板30a於水平方向具有較大之長度w7。其中，第二可撓折部46僅具有可撓折層31，而第三承載部47則具有可撓折層31以及剛性層32。並且，第三承載部47經由第二可撓折部46而連接至第二承載部34；並且第二可撓折部46呈現任意撓折，以使第三承載部47與第一承載部33設置於相同/或不相同平面之電路板(本實施例為如圖6C所示之相同平面之電路板45a)。
再如第6C圖(沿第6A圖中連接線AA’之剖面圖)所示，於本實施例之半導體封裝件6之中，如同第一晶片37-1及第二晶片37-2，第四晶片37-4亦以覆晶方式設置於第三承載部47之第一側471。詳言之，第四晶片37-4之主動面3741朝下，並且由設置於主動面3741之電性連接墊374，經由錫球364而電性連接至第三承載部47內部之導電柱P05，再進而電性連接至第三承載部47內部之導電層W01~W04。換言之，第四晶片37-4之主動面3741係以覆晶方式電性連接於第三承載部47之第一側471。
此外，如同模封層42及模封層43，半導體封裝件6更包含一模封層48，其亦經由鑄模工序設置或形成於第三承載部47之第一側471之第二剛性層322上。模封層48並完整包覆第四晶片37-4以及錫球364。
承上，可撓式載板30a之第三承載部47、第四晶片37-4及模封層48係組成半導體封裝件6之側向封裝部53，其係經由可撓式載板30a之第二可撓折部46而連接於上層封裝部52。因此，側向封裝部53與上層封裝部52之間的訊號傳輸可經由第二可撓折部46內部之導電層W02、W03而完成。
於本實施例中，係直接經由可撓式載板30a之撓折(即：第二可撓折部46呈現任意撓折)而克服不同元件之垂直設置位置之高度差，以完成側向封裝部53與上層封裝部52之間的電性連接。進一步而言，側向封裝部53與上層封裝部52之間的連接無需藉由任何中介層(特別是硬式之矽中介層)之轉接，亦無需藉由任何導電柱(銅柱)或錫球之電性連接。因此，本實施例能簡化封裝流程，並提高半導體封裝件6之結構強度與可靠度以及封裝設計的彈性。
此外，由於可撓式載板30a之第二可撓折部46可向下撓折，以使得側向封裝部53能夠與底層封裝部51設置於同一平面之適當位置，並通過錫球365而電性連接於電路板45a，進而使得側向封裝部53上方之空間得以容納其他元件，而大幅提升了空間利用度以及封裝設計的彈性。換言之，本實施例之可撓式載板30a於水平方向及垂直方向皆具有更大之設置彈性及空間利用度，以使半導體封裝件6於水平方向及垂直方向之封裝尺寸皆能縮小。上述為本發明之第二實施例之技術功效。
承上所述，由於側向封裝部53上方仍具有充裕空間，因而於第四晶片37-4之上能夠進一步層疊設置另一第五晶片37-5，以形成如第6D圖所示之半導體封裝件6a。
第6D圖為本發明之第二實施例之另一實施態樣之半導體封裝件6a之封裝結構之剖面示意圖。如第6D圖所示，第五晶片37-5經由黏合層55而以背對背方式設置於第四晶片37-4上。第五晶片37-5之主動面3751朝上，並且設置於主動面3751之電性連接墊375經由引線56而電性連接於第三承載部47內部之導電柱P06，再進而電性連接至第三承載部47內部之導電層W01~W04。換言之， 第五晶片37-5之主動面3751以打線方式電性連接於第三承載部47之第一側471。
此外，模封層48a完整包覆第四晶片37-4、第五晶片37-5、引線56及錫球364。可撓式載板30a之第三承載部47、第四晶片37-4、第五晶片37-5、引線56以及模封層48a組成半導體封裝件6a之側向封裝部53a。
綜上所述，本發明揭露之一種半導體封裝件利用至少可呈180度彎折之可撓折部，可連結不同高度的晶片、模組或散熱片，而不必透過電路板或中介層進行電路連結，大幅提高封裝設計的自由度，並可縮減電路板的尺寸，與減少採用矽中介層所增加的成本。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包括於後附之申請專利範圍中。
5:半導體封裝件
32:剛性層
321:第一剛性層
322:第二剛性層
361~363:錫球
371~373:電性連接墊
37-1~37-3:晶片
3711,3721,3731:主動面
3722,3732:背面
38:引線
40:第一黏合層
41:第二黏合層
42:第一模封層
43:第二模封層
45:電路板
51:底層封裝部
52:上層封裝部
w6:長度
W01~W04:導電層

Claims (10)

  1. 一種半導體封裝件，包含：一可撓式載板，係包括一具有圖案化增層線路且呈軟性之可撓折層，以及結合於該可撓折層部分表面上之剛性層；該可撓折層結合有剛性層之部位形成為一第一承載部及一第二承載部，而該第一承載部及該第二承載部間未結合有剛性層之該可撓折層形成為一第一可撓折部；一第一晶片，係具有一主動面以及相對之一背面，且以該主動面側覆晶接置於該第一承載部上；一第一模封層，係設置於該第一承載部上，並包覆該第一承載部及該第一晶片；一第一黏合層，係設置於該第一模封層上，以供該第二承載部結合於該第一模封層上，其中連接該第二承載部及該第一承載部之第一可撓折部至少彎折180°；一第二晶片，係具有一主動面以及相對之一背面，且以該主動面側覆晶接置於該第二承載部上；以及一第二模封層，係設置於該第二承載部上，並包覆該第二承載部及該第二晶片；其中，該第一承載部及該第二承載部藉由該可撓式載板內之該圖案化增層線路電性連接。
  2. 如請求項1之半導體封裝件，其中，該第一承載部之下方係電性連接於一電路板。
  3. 如請求項1之半導體封裝件，更包含：一第六晶片，係嵌埋於該第一模封層內，且具有一主動面以及相對之一背面，該第六晶片以該背面經由一第四黏合層結合於該第一晶片之該背面，其中該第六晶片之該主動面以引線電性連接於該第一承載部。
  4. 如請求項1之半導體封裝件，更包含：一第三晶片，係嵌埋於該第二模封層內，且具有一主動面以及相對之一背面，該第三晶片以該背面經由一第二黏合層結合於該 二晶片之該背面，其中該第三晶片之該主動面以引線電性連接於該第二承載部。
  5. 如請求項1之半導體封裝件，更包含：
    一第六晶片，係嵌埋於該第一模封層內，且具有一主動面以及相對之一背面，該第六晶片以該背面經由一第四黏合層結合於該第一晶片之該背面，其中該第六晶片之該主動面以引線電性連接於該第一承載部；以及
    一第三晶片，係嵌埋於該第二模封層內，且具有一主動面以及相對之一背面，該第三晶片以該背面經由一第二黏合層結合於該第二晶片之該背面，其中該第三晶片之該主動面以引線電性連接於該第二承載部。
  6. 如請求項1之半導體封裝件，其中：
    該可撓式載板更包含有一僅具有可撓折層之第二可撓折部，以及
    一具有可撓折層及剛性層之第三承載部，其中該第三承載部經由該第二可撓折部連接於該第二承載部，並且該第三承載部與該第一承載部設置於同一平面；
    一第四晶片，係具有一主動面以及相對之一背面，且以該主動面覆晶接置於該第三承載部上；以及
    一第三模封層，係設置於該第三承載部上，並包覆該第三承載部及該第四晶片；
    其中，該第一承載部及該第二承載部及該第三承載部藉由該可撓式載板內之該圖案化增層線路電性連接。
  7. 如請求項6之半導體封裝件，其中，該第三承載部之下方係電性連接於一電路板。
  8. 如請求項6之半導體封裝件，更包含：
    一第五晶片，係嵌埋於該第三模封層內，且具有一主動面以及相對之一背面，該第五晶片以該背面經由一第三黏合層結合於該第四晶片之該背面，其中該第五晶片之該主動面以引線電性連接於該第三承載部。
  9. 如請求項6之半導體封裝件，更包含：
    一第五晶片，係嵌埋於該第三模封層內，且具有一主動面以及相對之一背面，該第五晶片以該背面經由一第三黏合層結合於該第四晶片之該背面，其中該第五晶片之該主動面以引線電性連接於該第三承載部；以及
    一第三晶片，係嵌埋於該第二模封層內，且具有一主動面以及相對之一背面，該第三晶片以該背面經由一第二黏合層結合於該第二晶片之該背面，其中該第三晶片之該主動面以引線電性連接於該第二承載部。
  10. 如請求項6之半導體封裝件，更包含：
    一第五晶片，係嵌埋於該第三模封層內，且具有一主動面以及相對之一背面，該第五晶片以該背面經由一第三黏合層結合於該第四晶片之該背面，其中該第五晶片之該主動面以引線電性連接於該第三承載部；
    一第六晶片，係嵌埋於該第一模封層內，且具有一主動面以及相對之一背面，該第六晶片以該背面經由一第四黏合層結合於該第一晶片之該背面，其中該第六晶片之該主動面以引線電性連接於該第一承載部；以及
    一第三晶片，係嵌埋於該第二模封層內，且具有一主動面以及相對之一背面，該第三晶片以該背面經由一第二黏合層結合於該第二晶片之該背面，其中該第三晶片之該主動面以引線電性連接於該第二承載部。
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