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TWI473217B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI473217B
TWI473217B TW101125979A TW101125979A TWI473217B TW I473217 B TWI473217 B TW I473217B TW 101125979 A TW101125979 A TW 101125979A TW 101125979 A TW101125979 A TW 101125979A TW I473217 B TWI473217 B TW I473217B
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Taiwan
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semiconductor
encapsulant
build
semiconductor package
conductive
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TW101125979A
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English (en)
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TW201405732A (zh
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張江城
李孟宗
黃榮邦
邱世冠
黃富堂
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矽品精密工業股份有限公司
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Priority to TW101125979A priority Critical patent/TWI473217B/zh
Priority to CN201210270391.XA priority patent/CN103579134B/zh
Priority to US13/654,754 priority patent/US9324585B2/en
Publication of TW201405732A publication Critical patent/TW201405732A/zh
Application granted granted Critical
Publication of TWI473217B publication Critical patent/TWI473217B/zh
Priority to US15/074,110 priority patent/US9812340B2/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

半導體封裝件及其製法
本發明係關於半導體封裝件，特別是關於一種覆晶式半導體封裝件及其製法。
隨著電子產業的蓬勃發展，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展。例如，隨著前端半導體晶片製程的集積化，半導體晶片之主動面上形成有密集的電極墊，以提供訊號的輸入/輸出(I/O)。為了配合此一發展趨勢，後端半導體業者則積極研發能順利用互連結構將該等電極墊傳輸之訊號扇出的半導體封裝件，例如扇出式晶圓級晶片規模封裝件。
在是種封裝件中，如晶片之半導體元件通常係藉由一封裝膠體鑲嵌至一承載件。之後，該承載件會被移除，並在該半導體元件上形成互連結構。如第3A圖所示之封裝膠體形成過程中，係於承載件30整表面上形成黏著層32，接著，於該黏著層32上之預定位置A設置半導體元件36。之後，如第3B圖所使示，於該黏著層32上形成封裝膠體37，以包覆該半導體元件36。然而，因進行模壓時之溫度變化，使得黏著層32發生伸縮，導致半導體元件36偏離預定位置A，影響模壓以及後續製程之對位精準度，例如，形成於該半導體元件上的增層線路無法電性連接該半導體元件，使產品良率降低。
因此，如何克服上述習知技術之種種問題，實已成目 前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：封裝膠體，係具有相對之頂面和底面；嵌設於該封裝膠體中之至少一半導體元件，係具有相對之第一表面與第二表面，且該第一表面外露出該封裝膠體；聚合物層，係形成於該半導體元件與封裝膠體之間，並延伸至該封裝膠體底面上；以及線路增層結構，係形成於該半導體元件之第一表面上。
本發明復提供一種半導體封裝件之製法，係包括：提供一表面上設有至少一半導體元件之承載件，其中，該半導體元件係藉由黏著層貼附於該承載件上，俾使該承載件的部份表面係顯露於外；形成封裝膠體，以包覆該半導體元件，其中，該封裝膠體具有相對之頂面和與該黏著層同側之底面；移除該黏著層和承載件，以外露出該半導體元件；以及於該外露之半導體元件上形成線路增層結構。
於一具體實施例中，前述半導體封裝件之製法復包括於形成該封裝膠體之前，於該顯露之承載件表面及半導體元件表面上形成聚合物層，則該封裝膠體係形成於該聚合物層上。
前述半導體封裝件之製法中，該半導體元件之設置係包括下列步驟：於承載件之整表面上形成黏著層；於該黏著層上設置至少一半導體元件，並外露出部分該黏著層；以及移除外露之該黏著層。
此外，於一具體實施例中，於設置該至少一半導體元件之前，以遮罩遮蓋住部分該黏著層，以外露出該半導體元件的設置位置；以及對該半導體元件的設置位置照光。
相較於習知技術，本發明利用感光性的黏著層，使其形成複數個分離的黏著層單元，避免溫度變化時伸縮而相互影響，再於該顯露之承載件表面及半導體元件表面上形成聚合物層，以固定該半導體元件，避免進行封裝模壓時造成半導體元件的偏移，俾提升後續製程之對位精準度，改善製程良率。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“前”、“後”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。例如，本發明中， 第一表面之“第一”係指形成電極墊之表面，而非限定所有半導體元件之第一表面皆為相同之用途。
請參閱第1A至1I圖，係為本發明之半導體封裝件之第一實施例之製法之剖面示意圖。
請參閱第1A至1D圖，係說明於承載件表面上設置半導體元件之方法，其中，該半導體元件係藉由黏著層貼附於該承載件上，且該承載件的部份表面係顯露於外。
如第1A圖所示，於例如基板之承載件10之整表面上形成黏著層12。
接著，如第1B圖所示，以遮罩14遮蓋住部分該黏著層12，以外露出該半導體元件的設置位置，以及對該半導體元件的設置位置照光。在本實施例中，該黏著層之材質為感光性黏著劑，例如照UV光可聚合之材料，使得未照光的部份可利用清洗液或顯影液移除。
如第1C圖所示，於該黏著層12上設置至少一半導體元件16，並外露出部分該黏著層12。在本實施例中，係設置三個半導體晶片，但不以此為限。此外，如圖所示，該半導體元件16具有相對之第一表面16a與第二表面16b，該第一表面16a上具有複數電極墊161。
如第1D圖所示，移除外露之該黏著層12，使該黏著層12(此時為複數個黏著層12)僅形成於該半導體元件16與承載件10之間。
如第1E圖所示，於該顯露之承載件10表面及半導體元件16表面上形成例如聚醯亞胺之聚合物層18。
如第1F圖所示，於該聚合物層18上模壓形成封裝膠體20，以包覆該半導體元件16，其中，該封裝膠體20具有相對之頂面20a和底面20b，該底面20b係接觸該聚合物層18。由於相鄰半導體元件16之間的黏著層12被移除，且於該顯露之承載件10表面及半導體元件16表面(包括側面及第二表面16b)形成聚合物層18，可固定該半導體元件16於承載件10上，避免進行封裝模壓時造成半導體元件16的偏移，俾提升後續製程之對位精準度，改善製程良率。
於第1F’圖所示之另一實施例中，該封裝膠體20可直接形成於如第1D圖所示結構之承載件10表面上，由於該黏著層12僅形成於該半導體元件16與承載件10之間，可避免製程期間兩半導體元件16之間的黏著層12收縮，使半導體元件16的偏離原本位置，亦可提升後續製程之對位精準度。
如第1G圖所示，以機械方式及/或化學物質移除的方式，移除該黏著層12和承載件10，以外露出該半導體元件16，其中，該半導體元件16之第一表面16a外露出該聚合物層18。
如第1G’圖所示，該半導體元件16之第一表面16a外露出該封裝膠體20。
如第1H圖所示，於該外露之半導體元件16上及封裝膠體20底面20b上及聚合物層18上形成線路增層結構21。該線路增層結構21係形成於該半導體元件16之第一 表面16a上，且該線路增層結構21具有至少一介電層211、形成於該介電層211上之增層線路212、及形成於該介電層211中之導電盲孔213以電性連接該增層線路212和電極墊161。
此外，該線路增層結構21復具有外露之電性連接墊214，其係電性連接該最外層之增層線路212，且前述之製法復包括於該電性連接墊214上形成如銲球之導電元件22。
接著，進行切單製程，切割該封裝膠體20、聚合物層18和線路增層結構21，即可得到如第1I圖所示之半導體封裝件。
如第1H’和1I’圖所示，係顯示未形成有聚合物層18之半導體封裝件。
請參閱第2A至2F圖，係為本發明之半導體封裝件之第二實施例之剖面示意圖。
如第2A圖所示，係接續第1F圖的步驟，於移除該黏著層12和承載件10之前，形成複數個貫穿該封裝膠體20和聚合物層18之穿孔201於該半導體元件16旁。若依據第1F’圖之步驟，該穿孔201則僅貫穿該封裝膠體。
如第2B及2C圖所示，於該穿孔201中形成導電柱23，再於該封裝膠體20之頂面20a上形成電性連接該導電柱23之導電跡線24。具體而言，該導電柱的形成係可於該封裝膠體20表面和穿孔201內壁面形成晶種層(未圖示)，再利用電鍍法於該穿孔201中形成導電柱23。同樣地，於封 裝膠體20之頂面20a上電鍍形成導電跡線24。
如第2C圖所示，於該封裝膠體20之頂面20a及導電跡線24上形成絕緣層25，其中，該絕緣層25外露部分導電跡線24。
如第2D圖所示，移除該黏著層12和承載件10，以外露出該半導體元件16，其中，該半導體元件16具有相對之第一表面16a與第二表面16b，該第一表面16a上具有複數電極墊161，且該第一表面16a外露出該聚合物層18。
如第2E圖所示，翻轉該封裝膠體20，於該外露之半導體元件16上形成線路增層結構21。該線路增層結構21係形成於該半導體元件16之第一表面16a上，且該線路增層結構21具有至少一介電層211、形成於該介電層211上之增層線路212、及形成於該介電層211中之複數導電盲孔213以電性連接該增層線路212、電極墊161和導電柱23。
如第2F圖所示，該線路增層結構21復具有外露之電性連接墊214，且該製法復包括於該電性連接墊214上形成導電元件22。
接著，進行切單製程，即可得到具有導電柱23的半導體封裝件，並可藉由該外露之部分導電跡線24接至其他電子元件，例如其他半導體封裝件。
本發明提供一種半導體封裝件，係包括：封裝膠體20、嵌設於該封裝膠體20中之至少一半導體元件16、聚合物層18、以及線路增層結構21。
所述之封裝膠體20係具有相對之頂面20a和底面20b。
所述之半導體元件16係具有相對之第一表面16a與第二表面16b，且該第一表面16a外露出該封裝膠體20。
所述之聚合物層18係形成於該半導體元件16與封裝膠體20之間，並延伸至該封裝膠體20底面20b上，且該半導體元件16之第一表面16a與該聚合物層18形成一段差結構。
所述之線路增層結構21係形成於該半導體元件16之第一表面16a上，其中，該半導體元件16之第一表面16a上具有複數電極墊161，且該線路增層結構21具有至少一介電層211、形成於該介電層211上之增層線路212、及形成於該介電層211中之導電盲孔213以電性連接該增層線路212和電極墊161。此外，該線路增層結構21復可具有外露之電性連接墊214，且該半導體封裝件復包括導電元件22，係形成於該電性連接墊214上。
於一具體實施例中，該半導體封裝件復包括複數個貫穿該封裝膠體20和聚合物層18之穿孔201，且該穿孔201係形成於該半導體元件16旁；形成於該穿孔201中之導電柱23；形成於該封裝膠體20之頂面20a上且電性連接該導電柱23之導電跡線24；以及形成於該封裝膠體20之頂面20a及導電跡線24上之絕緣層25。此實施例中，該半導體元件16之第一表面16a上具有複數電極墊161，且該線路增層結構21具有至少一介電層211、形成於該介電層 211上之增層線路212、及形成於該介電層211中之複數導電盲孔213以電性連接該增層線路212、電極墊161和導電柱23。
綜上所述，本發明利用感光性的黏著層，使其形成複數個分離的黏著層單元，避免溫度變化時伸縮而相互影響，再於該顯露之承載件表面及半導體元件表面上形成聚合物層，以固定該半導體元件，避免進行封裝模壓時造成半導體元件的偏移，俾提升後續製程之對位精準度，改善製程良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10,30‧‧‧承載件
12,32‧‧‧黏著層
14‧‧‧遮罩
16,36‧‧‧半導體元件
16a‧‧‧第一表面
16b‧‧‧第二表面
161‧‧‧電極墊
18‧‧‧聚合物層
20,37‧‧‧封裝膠體
20a‧‧‧頂面
20b‧‧‧底面
21‧‧‧線路增層結構
211‧‧‧介電層
212‧‧‧增層線路
213‧‧‧導電盲孔
214‧‧‧電性連接墊
22‧‧‧導電元件
201‧‧‧穿孔
23‧‧‧導電柱
24‧‧‧導電跡線
25‧‧‧絕緣層
A‧‧‧預定位置
第1A至1I圖，係為本發明之半導體封裝件之第一實施例之製法之剖面示意圖，其中，第1A至1D圖，係說明於承載件表面上設置半導體元件之方法；第1F’至1I’圖係說明無聚合物層之半導體封裝件之製法；第2A至2F圖，係為本發明之半導體封裝件之第二實施例之剖面示意圖；以及第3A及3B圖係為習知半導體封裝件之製法之剖面示意圖。
16‧‧‧半導體元件
18‧‧‧聚合物層
20‧‧‧封裝膠體
21‧‧‧線路增層結構
211‧‧‧介電層
212‧‧‧增層線路
213‧‧‧導電盲孔
22‧‧‧導電元件

Claims (18)

  1. 一種半導體封裝件，係包括：封裝膠體，係具有相對之頂面和底面；嵌設於該封裝膠體中之至少一半導體元件，係具有相對之第一表面與第二表面，且該第一表面外露出該封裝膠體底面；聚合物層，係形成於該半導體元件與封裝膠體之間，並延伸至該封裝膠體底面上方；以及線路增層結構，係形成於該半導體元件之第一表面上。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之第一表面上具有複數電極墊，且該線路增層結構具有至少一介電層、形成於該介電層上之增層線路、及形成於該介電層中之導電盲孔以電性連接該增層線路和電極墊。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路增層結構復具有外露之電性連接墊，且該半導體封裝件復包括導電元件，係形成於該電性連接墊上。
  4. 如申請專利範圍第1項所述之半導體封裝件，復包括複數個貫穿該封裝膠體和聚合物層之穿孔，且該穿孔係形成於該半導體元件旁；形成於該穿孔中之導電柱；形成於該封裝膠體之頂面上且電性連接該導電柱之導電跡線；以及形成於該封裝膠體之頂面及導電跡線上之絕緣層。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中，該半導體元件之第一表面上具有複數電極墊，且該線路增層結構具有至少一介電層、形成於該介電層上之增層線路、及形成於該介電層中之複數導電盲孔以電性連接該增層線路、電極墊和導電柱。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之第一表面與該聚合物層形成一段差結構。
  7. 一種半導體封裝件之製法，係包括：提供一表面上設有至少一半導體元件之承載件，其中，該半導體元件係藉由黏著層貼附於該承載件上，俾使該承載件的部份表面係顯露於外；形成封裝膠體，以包覆該半導體元件，其中，該封裝膠體具有相對之頂面和與該黏著層同側之底面；移除該黏著層和承載件，以外露出該半導體元件；以及於該外露之半導體元件上形成線路增層結構。
  8. 如申請專利範圍第7項所述之半導體封裝件之製法，復包括於形成該封裝膠體之前，於該顯露之承載件表面及半導體元件表面上形成聚合物層。
  9. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該半導體元件之設置係包括下列步驟：於承載件之整表面上形成黏著層；於該黏著層上設置至少一半導體元件，並外露出 部分該黏著層；以及移除外露之該黏著層。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該半導體元件之設置復包括下列步驟：於設置該至少一半導體元件之前，以遮罩遮蓋住部分該黏著層，以外露出該半導體元件的設置位置；以及對該半導體元件的設置位置照光。
  11. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該半導體元件具有相對之第一表面與第二表面，該第一表面上具有複數電極墊，且該第一表面外露出該封裝膠體底面。
  12. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該半導體元件具有相對之第一表面與第二表面，該第一表面上具有複數電極墊，且該第一表面外露出該聚合物層。
  13. 如申請專利範圍第11或12項所述之半導體封裝件之製法，其中，該線路增層結構係形成於該半導體元件之第一表面上，且該線路增層結構具有至少一介電層、形成於該介電層上之增層線路、及形成於該介電層中之導電盲孔以電性連接該增層線路和電極墊。
  14. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該線路增層結構復具有外露之電性連接墊，且該製法復包括於該電性連接墊上形成導電元件。
  15. 如申請專利範圍第7項所述之半導體封裝件之製法，復包括於移除該黏著層和承載件之前，形成複數個貫穿該封裝膠體之穿孔於該半導體元件旁；於該穿孔中形成導電柱；於該封裝膠體之頂面上形成電性連接該導電柱之導電跡線；以及於該封裝膠體之頂面及導電跡線上形成絕緣層。
  16. 如申請專利範圍第8項所述之半導體封裝件之製法，復包括於移除該黏著層和承載件之前，形成複數個貫穿該封裝膠體和聚合物層之穿孔於該半導體元件旁；於該穿孔中形成導電柱；於該封裝膠體之頂面上形成電性連接該導電柱之導電跡線；以及於該封裝膠體之頂面及導電跡線上形成絕緣層。
  17. 如申請專利範圍第15或16項所述之半導體封裝件之製法，其中，該半導體元件具有相對之第一表面與第二表面，該第一表面上具有複數電極墊。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該線路增層結構係形成於該半導體元件之第一表面上，且該線路增層結構具有至少一介電層、形成於該介電層上之增層線路、及形成於該介電層中之複數導電盲孔以電性連接該增層線路、電極墊和導電柱。
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