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TWI349346B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same

Info

Publication number
TWI349346B
TWI349346B TW096118826A TW96118826A TWI349346B TW I349346 B TWI349346 B TW I349346B TW 096118826 A TW096118826 A TW 096118826A TW 96118826 A TW96118826 A TW 96118826A TW I349346 B TWI349346 B TW I349346B
Authority
TW
Taiwan
Prior art keywords
manufacturing
same
semiconductor device
semiconductor
Prior art date
Application number
TW096118826A
Other languages
English (en)
Other versions
TW200816423A (en
Inventor
Hidetoshi Kusano
Tomoshi Ohde
Original Assignee
Sony Corp
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Computer Entertainment Inc filed Critical Sony Corp
Publication of TW200816423A publication Critical patent/TW200816423A/zh
Application granted granted Critical
Publication of TWI349346B publication Critical patent/TWI349346B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427Cooling by change of state, e.g. use of heat pipes
    • H01L23/4275Cooling by change of state, e.g. use of heat pipes by melting or evaporation of solids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW096118826A 2006-06-16 2007-05-25 Semiconductor device and method for manufacturing the same TWI349346B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006167626A JP4589269B2 (ja) 2006-06-16 2006-06-16 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW200816423A TW200816423A (en) 2008-04-01
TWI349346B true TWI349346B (en) 2011-09-21

Family

ID=38860720

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096118826A TWI349346B (en) 2006-06-16 2007-05-25 Semiconductor device and method for manufacturing the same

Country Status (4)

Country Link
US (1) US20070290310A1 (zh)
JP (1) JP4589269B2 (zh)
CN (1) CN101090098B (zh)
TW (1) TWI349346B (zh)

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US7491577B2 (en) * 2007-01-08 2009-02-17 Bae Systems Information And Electronic Systems Integration Inc. Method and apparatus for providing thermal management on high-power integrated circuit devices
KR101489798B1 (ko) * 2007-10-12 2015-02-04 신꼬오덴기 고교 가부시키가이샤 배선 기판
JP5213736B2 (ja) * 2009-01-29 2013-06-19 パナソニック株式会社 半導体装置
JP5169964B2 (ja) * 2009-04-10 2013-03-27 株式会社デンソー モールドパッケージの実装構造および実装方法
US8647752B2 (en) 2010-06-16 2014-02-11 Laird Technologies, Inc. Thermal interface material assemblies, and related methods
US20130187284A1 (en) * 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
FR2999336A1 (fr) * 2012-12-07 2014-06-13 Commissariat Energie Atomique Composant electronique comportant un materiau absorbeur de chaleur et procede de fabrication de ce composant electronique
US9961798B2 (en) 2013-04-04 2018-05-01 Infineon Technologies Austria Ag Package and a method of manufacturing the same
KR101473356B1 (ko) * 2013-06-19 2014-12-16 에스티에스반도체통신 주식회사 히트 슬러그의 접지방법
JP2015088683A (ja) 2013-11-01 2015-05-07 富士通株式会社 熱接合シート、及びプロセッサ
KR101538573B1 (ko) 2014-02-05 2015-07-21 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
DE102015223422A1 (de) * 2015-11-26 2017-06-01 Robert Bosch Gmbh Elektrische Vorrichtung mit einer Umhüllmasse
JP2017183635A (ja) * 2016-03-31 2017-10-05 ソニー株式会社 半導体装置、半導体装置の製造方法、集積基板、及び、電子機器
JP6477971B2 (ja) * 2016-05-09 2019-03-06 日立化成株式会社 半導体装置の製造方法
CN107399041B (zh) * 2017-06-05 2019-04-16 湖北久祥电子科技有限公司 一种铆合式封胶的led封装工艺
KR20190018812A (ko) * 2017-08-16 2019-02-26 삼성전기주식회사 반도체 패키지와 이를 구비하는 전자 기기
KR20230100752A (ko) 2018-02-20 2023-07-05 가부시키가이샤 무라타 세이사쿠쇼 반도체 장치 및 반도체 장치의 제조 방법
JP2020047836A (ja) * 2018-09-20 2020-03-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
CN113574661B (zh) 2019-02-04 2024-08-30 索尼互动娱乐股份有限公司 电子设备、半导体器件、绝缘片和半导体器件制造方法
WO2020241067A1 (ja) * 2019-05-30 2020-12-03 ソニーセミコンダクタソリューションズ株式会社 基板、電子装置、および、基板の製造方法
US11621211B2 (en) * 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure
KR102601150B1 (ko) * 2019-08-23 2023-11-09 삼성전자주식회사 반도체 패키지
CN111545424B (zh) * 2020-04-28 2022-01-18 中科视拓(南京)科技有限公司 一种计算机cpu导热硅脂涂抹器
TW202220064A (zh) 2020-09-24 2022-05-16 日商索尼互動娛樂股份有限公司 半導體封裝、電子機器及電子機器的製造方法
WO2022080081A1 (ja) * 2020-10-16 2022-04-21 ローム株式会社 半導体装置
CN117157750A (zh) 2021-04-28 2023-12-01 索尼半导体解决方案公司 半导体装置
US20230421119A1 (en) * 2022-06-24 2023-12-28 Wolfspeed, Inc. Semiconductor device packages with exposed heat dissipating surfaces and methods of fabricating the same
CN114823573B (zh) * 2022-06-24 2022-09-09 威海市泓淋电力技术股份有限公司 一种散热型封装结构及其形成方法
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Also Published As

Publication number Publication date
JP4589269B2 (ja) 2010-12-01
JP2007335742A (ja) 2007-12-27
US20070290310A1 (en) 2007-12-20
CN101090098B (zh) 2010-09-29
CN101090098A (zh) 2007-12-19
TW200816423A (en) 2008-04-01

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