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TW201725769A - 整合式扇出型堆疊式封裝及其形成方法 - Google Patents

整合式扇出型堆疊式封裝及其形成方法 Download PDF

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TW201725769A
TW201725769A TW105142324A TW105142324A TW201725769A TW 201725769 A TW201725769 A TW 201725769A TW 105142324 A TW105142324 A TW 105142324A TW 105142324 A TW105142324 A TW 105142324A TW 201725769 A TW201725769 A TW 201725769A
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package
die
tim
molding compound
layer
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TWI720094B (zh
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林文益
劉獻文
林柏堯
黃震麟
呂學德
鄭心圃
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台灣積體電路製造股份有限公司
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Abstract

一種實施例封裝包含：一第一封裝；一熱界面材料(TIM)，其接觸該第一封裝之一頂部表面；及一第二封裝，其經接合至該第一封裝。該第二封裝包含一第一半導體晶粒，且該TIM接觸該第一半導體晶粒之一底部表面。該封裝進一步包含一散熱器，其經放置於與該第一封裝相對之該第二封裝之一表面上。

Description

整合式扇出型堆疊式封裝及其形成方法
本發明實施例係有關半導體裝置及其製造方法，特別是有關半導體封裝及其製造方法。
由於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)之整合密度之持續改良，半導體工業已經歷了迅速成長。整合密度之此改良很大程度上係源於最小構件大小之重複減小(例如，將半導體製程節點朝向小於20 nm之節點縮小)，此允許將更多組件整合至一給定區域中。最近，隨著對小型化、較高速度及較大頻寬以及較低電力消耗及等待時間之要求增強，已需要對半導體晶粒之更小型及更具創造性之封裝技術。 隨著半導體技術進一步發展，堆疊式半導體裝置(例如，3D積體電路(3DIC))，已作為一有效替代形式出現以進一步減小一半導體裝置之實體大小。在一堆疊式半導體裝置中，主動電路(諸如邏輯電路、記憶體電路、處理器電路及諸如此類)被製作於不同半導體晶圓上。兩個或兩個以上半導體晶圓可被安裝於彼此之頂部上以進一步減小半導體裝置之尺寸架構。 可透過適合接合技術將兩個半導體晶圓或晶粒接合在一起。該堆疊式半導體裝置可提供一較高密度及較小尺寸架構且允許經增加效能及較低電力消耗。
根據一實施例，一種封裝包含：一第一封裝；一熱界面材料(TIM)，其接觸該第一封裝之一頂部表面；及一第二封裝，其接合至該第一封裝。該第二封裝包含一第一半導體晶粒，且該TIM接觸該第一半導體晶粒之一底部表面。該封裝進一步包含一散熱器，其放置於與該第一封裝相對的該第二封裝之一表面上。 根據另一實施例，一種封裝包含：一第一晶粒；一第一模塑料，其沿著該第一晶粒之側壁延伸；一聚合物層，其在該第一晶粒之一頂部表面上；及一第二晶粒，其在該第一晶粒上方且藉由一間隙與該第一晶粒分離，該聚合物層橫跨該間隙且接觸該第二晶粒之一底部表面。該封裝進一步包含：一第二模塑料，其沿著該第二晶粒之側壁延伸；及一散熱器，其在該第二晶粒上方。該第一模塑料及該第二模塑料係藉由該間隙分離。 根據又一實施例，一種方法包含：提供具有一第一半導體晶粒之一第一封裝，提供在一頂部表面上具有一熱界面材料(TIM)之一第二封裝，及將該第一封裝接合至該第二封裝以形成一接合式封裝。該TIM接觸該接合式封裝中之該第一半導體晶粒之一底部表面。該方法進一步包含將一散熱器附接至與該TIM相對的該第一封裝之一側。
以下揭露提供諸多不同實施例或實例以實施本發明之不同構件。下文闡述組件及配置之特定實例以簡化本揭露。當然，此等特定實例僅係實例且並不意欲係限制性的。舉例而言，在以下說明中，一第一構件形成於一第二構件上方或該第二構件上可包含其中第一構件與第二構件直接接觸而形成之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡潔及清晰目的且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於說明，本文中可使用空間相對術語(諸如「下」、「下方」、「下部」、「上邊」、「上部」及諸如此類)來闡述一個元件或構件與另一(些)元件或構件之關係，如圖中所圖解說明。除圖中所繪示之定向外，空間相對術語亦意欲囊括在使用或操作中之裝置之不同定向。亦可以其他方式定向(旋轉90度或處於其他定向)設備且可相應地以類似方式解釋本文中所使用之空間相對描述符。 各種實施例包含具有至少兩個接合式裝置封裝之一堆疊式封裝(PoP)結構。裝置封裝中之一頂部裝置封裝包含一第一半導體晶粒，其中一熱界面材料(TIM)在該第一半導體晶粒之一背面上。裝置封裝中之一底部裝置封裝經接合至頂部裝置封裝，且TIM亦可與該底部裝置封裝形成一界面。舉例而言，TIM可接觸底部裝置封裝中之一第二半導體晶粒。因此，可將來自底部封裝之熱量有利地耗散至頂部封裝並(舉例而言)耗散至放置於與底部封裝相對的頂部封裝之一表面上之一散熱器。因此，可改良一實施例封裝之熱效能及可靠性。散熱器可進一步改良頂部封裝之勁度，此可有利地減小翹曲。 圖1至圖5B圖解說明根據某些實施例之形成一裝置封裝100之各種剖面圖。首先參考圖1，提供一半導體晶粒102之一剖面圖。晶粒102可包含一半導體基板、主動裝置及一互連結構(未個別地圖解說明)。基板可包括(舉例而言)塊狀矽(經摻雜或未摻雜)或一絕緣體上半導體(SOI)基板之一主動層。通常，一SOI基板包括形成於一絕緣層上之一層半導體材料，諸如矽。絕緣層可係(舉例而言)一埋入式氧化物(BOX)層或一個氧化矽層。絕緣層經提供於一基板上，諸如一矽基板或玻璃基板。另一選擇係，基板可包含另一基本半導體，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或上述材料之組合。亦可使用其他基板，諸如多層基板或梯度基板。 主動裝置(諸如電晶體、電容器、電阻器、二極體、光電二極體、熔絲及諸如此類)可形成於基板之頂部表面處。一互連結構可形成於主動裝置及基板上方。互連結構可包含層間介電(ILD)層及/或金屬間介電(IMD)層，該等層含有使用任何適合方法形成之導電構件(例如，包括銅、鋁、鎢、上述材料之組合及諸如此類之導電線及導電通路)。ILD層及IMD層可包含放置於此等導電構件之間且具有(舉例而言)低於約4.0或甚至2.0之係數值的低介電係數材料。在某些實施例中，ILD層及IMD層可由(舉例而言)磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟矽酸鹽玻璃(FSG)、SiOx Cy 、旋塗玻璃、旋塗聚合物、碳化矽材料、上述材料之化合物、上述材料之複合物，上述材料之組合或諸如此類製成，且可藉由任何適合方法形成，諸如自旋、化學氣相沉積(CVD)及電漿輔助化學氣相沉積(PECVD)。互連結構電連接各種主動裝置以在晶粒102內形成功能電路。由此等電路提供之功能可包含記憶體結構、處理結構、感測器、放大器、電力重佈、輸入/輸出電路或諸如此類。熟習此項技術者將瞭解，提供以上實例僅出於進一步闡釋各種實施例之應用之說明性目的，且不意在以任何方式限制此等實施例。可視情況將其他電路用於一給定應用。 可在互連結構上方形成輸入/輸出(I/O)構件及鈍化構件。舉例而言，可在互連結構上方形成接點墊104，且可透過互連結構中之各種導電構件來將其電連接至主動裝置。接點墊104可包括一導電材料，諸如鋁、銅及諸如此類。此外，可在互連結構及接點墊上方形成一鈍化層106。在某些實施例中，鈍化層106可係由無機材料形成，諸如氧化矽、未摻雜矽酸鹽之玻璃、氮氧化矽及諸如此類。亦可使用其他適合鈍化材料。鈍化層106的部分可覆蓋接點墊104的邊緣部分。 亦可視情況在接點墊104上方形成額外互連構件(諸如額外鈍化層、導電柱及/或凸塊下金屬(UBM)層)。舉例而言，如由圖1所圖解說明，可在接點墊104上形成導電柱108並將其電連接至接點墊104，且可在此等導電柱108周圍形成一介電層109。 晶粒102之各種構件可係藉由任何適合方法來形成，且在本文中未更詳細地闡述。儘管在本文中稱為一晶粒，但在晶粒102係一較大基板(舉例而言，一晶圓(未圖解說明))的一部分時，可形成晶粒102的一或多個構件。在形成之後，可將晶粒102與晶圓中之其他結構(例如，其他晶粒)單粒化開。此外，以上所闡述之晶粒102之總體特徵及組態僅係一項實例性實施例，且晶粒102可包含任何數目個以上構件及其他構件之任何組合。 如藉由圖1進一步圖解說明，藉由一晶粒附接膜(DAF) 112將晶粒102附接至一載體110。載體110可係一玻璃載體或陶瓷載體，且可在後續處理步驟期間給晶粒102提供暫時機械及結構支撐。以此方式，可減小或防止對晶粒102之損壞。在一實施例中，DAF 112可係任何適合黏合劑，諸如當暴露於UV光下時會喪失其黏合性質之一紫外線(UV)膠。 此外，可在附接晶粒102之前，於載體110上方形成TIV 114。TIV 114可包括(舉例而言)銅、鎳、銀、金及諸如此類，且可藉由任何適合製程來形成。舉例而言，可在載體110上方形成一晶種層(未展示)，且可使用具有開口之一圖案化光阻劑(未展示)來定義TIV 114之形狀。該等開口可暴露晶種層，且該等開口可以一導電材料填充(例如，在一電化學電鍍製程、無電式電鍍製程及諸如此類製程中)。隨後，可在一灰化及/或濕剝除製程中移除光阻劑，從而留下載體110上方之TIV 114。TIV 114亦可係使用銅導線立柱而藉由銅導線接合製程來形成(例如，其中不需要遮罩、光阻劑及銅鍍覆)。然後可使用(舉例而言)光微影及/或蝕刻之一組合來移除晶種層的多餘部分。 隨後，在圖2中，於晶粒102及TIV 114周圍形成一模塑料116。在諸多實施例中，模塑料116包括一環氧樹脂、一樹脂、一可成型聚合物(諸如聚苯并㗁唑)、一模塑底膠(MUF)或另一可成型材料。在某些實施例中，可使用(舉例而言)一模具(未展示)來使模塑料116成形或成型，該模具可具有當施加模塑料116時用於保持模塑料116之一邊界或其他特性。此一模具可用於使模塑料116受壓成型於晶粒102及TIV 114周圍，以迫使模塑料116進入開口及凹槽，從而清除模塑料116中之氣穴或諸如此類。隨後，執行一固化製程以將模塑料116固體化。可使用其他適合製程(諸如氣轉移成型、壓縮成型、液體囊封劑成型及諸如此類)來形成模塑料116。 在模塑料116經形成於晶粒102周圍之後，藉由(舉例而言)研磨、化學機械拋光、蝕刻或另一製程來減小模塑料116或將其平坦化。在某些實施例中，減小模塑料116使得晶粒102之I/O結構(例如，導電柱108)被暴露。平坦化可進一步使晶粒102之頂部表面與TIV 114及模塑料116實質上水平。 圖3圖解說明重佈層(RDL) 118經形成於模塑料116、晶粒102及TIV 114上方。重佈層118可橫向延伸通過晶粒102之邊緣而延伸於模塑料116之一頂部表面上方。重佈層118可包含經形成於一或多個聚合物層122中之導電構件120。聚合物層122可係使用任何適合方法(諸如，一旋塗技術、層壓及諸如此類)而由任何適合材料(例如，聚醯亞胺(PI)、聚苯并㗁唑(PBO)、苯環丁烯(BCB)、環氧樹脂、聚矽氧、丙烯酸酯、奈米級填充酚醛樹脂、矽氧烷、一種氟化聚合物、聚降冰片烯及諸如此類)形成。 可在聚合物層122中形成導電構件120 (例如，導電線120A及/或導電通路120B)並將其電連接至TIV 114及晶粒102之導電柱108。導電構件120之形成可包含：(例如，使用光微影與蝕刻製程之一組合)將聚合物層122圖案化並在圖案化聚合物層上方及其中形成導電構件。導電構件120之形成可包含：沉積一晶種層(未展示)，使用具有各種開口之一遮罩層(未展示)來定義導電構件120之形狀，並使用(舉例而言)一電化學電鍍製程來填充遮罩層中之開口。然後可移除遮罩層及晶種層之多餘部分。因此，在晶粒102、TIV 114及模塑料116上方形成重佈層118。重佈層118之聚合物層及導電構件之數目並不限於所圖解說明之圖3之實施例。舉例而言，重佈層118可包含多個聚合物層中之任何數目個堆疊式電連接導電構件。 如藉由圖3進一步圖解說明，可移除載體110及DAF 112 (例如，在重佈層118形成之後)，並可在與重佈層118相對的TIV 114之一側上形成銲料帽124。銲料帽124可藉由TIV 114及重佈層118電連接至晶粒102。因此，形成一第一裝置封裝130。在後續製程步驟中，銲料帽124可用於將裝置封裝130接合至其他封裝構件(諸如另一封裝)，以便形成一實施例PoP結構(例如，參見圖5A)。 圖4圖解說明一第二裝置封裝150之一剖面圖，根據某些實施例第二裝置封裝150可隨後經接合至裝置封裝130(例如，參見圖5A)。在一實施例中，裝置封裝150包含與裝置封裝130類似之構件。舉例而言，裝置封裝150可包含一晶粒152及形成於晶粒152周圍且沿著晶粒152之側壁延伸之一模塑料154。晶粒152可包括與晶粒102類似之構件，且晶粒152可或可不提供與晶粒102相同之一功能性。舉例而言，在一實施例中，晶粒102可係一記憶體晶粒，而晶粒152可係提供控制電路之一邏輯晶粒。其他實施例可包含提供不同功能性之晶粒。封裝150可進一步包含延伸穿過模塑料154之TIV 156及形成於晶粒152、模塑料154及TIV 156上方之重佈層158。 裝置封裝150可進一步包含額外構件，諸如形成於重佈層158上方之外部連接器160 (例如，BGA球、C4凸塊及諸如此類)。連接器160可放置於UBM 162上，連接器160亦可形成於重佈層158上方。連接器160可藉由重佈層158電連接至晶粒152及TIV 156。連接器160可用於將裝置封裝150 (及隨後裝置封裝100，參見圖5A)電連接至其他封裝組件，諸如另一裝置晶粒、中介層、封裝基板、印刷電路板、一主機板及諸如此類。 如藉由圖4進一步圖解說明，一TIM 164可形成(例如，施配)於與重佈層158相對的裝置封裝150之一側上。舉例而言，TIM 164可形成於裝置封裝150之一表面上以接合至裝置封裝130 (參見圖5A)。TIM 164可包括任何適合材料，諸如具有一良好導熱性(可介於約3瓦特/米開爾文(W/m·K)與約5 W/m·K(或更多)之間)之一聚合物。在一實施例中，TIM 164可包括一黏合型材料、一膠體材料或以上兩項之一組合，諸如由ShinETSU Silicones或Dow Corning提供之一材料。如下文更詳細地闡釋，TIM 164可藉由提供自裝置封裝150至裝置封裝130之一散熱路徑而有利地改良所得接合式裝置封裝100之散熱。 圖5A圖解說明一接合式裝置封裝100，其包括接合至裝置封裝150之裝置封裝130。封裝130及封裝150可(舉例而言)藉由將封裝130之銲料帽124與封裝150之TIV 156對準並接合而接合。晶粒152可藉由重佈層158、TIM 164、TIV 114及重佈層118電連接至晶粒102。在接合期間，TIM 164可放置於裝置封裝130與裝置封裝150之間且接觸該兩者。在此期間，裝置封裝130 (例如，晶粒102)可將壓力施加至TIM 164上，此可使得TIM 164橫向散佈。在某些實施例中，使用一回銲製程來將銲料帽124接合至TIV 156，此可進一步將TIM 164固化。來自裝置封裝150之熱量可透過裝置封裝130之晶粒102耗散，如藉由箭頭168所圖解說明。 TIM 164可橋接裝置封裝130與裝置封裝150之間的一間隙170，且TIM 164可形成為具有充分大而足以橋接間隙170之一厚度Tl (例如，在TIM 164之頂部表面與底部表面之間量測)。舉例而言，在某些實施例中，TIM 164之厚度Tl可係約10 mm至約50 mm。此外，在一俯視圖(未展示)中，TIM 164可覆蓋晶粒102之一底部表面之一相對大百分比。舉例而言，TIM 164之一表面區域可係晶粒102之一底部表面之一表面區域之至少約80％。已觀察到，當TIM 164具有處於此範圍中之一表面區域時，可有利地改良裝置封裝之熱效能。舉例而言，封裝100之熱效能可包含藉由提供穿過晶粒102之一額外熱耗散路徑而達成之經改良效率及經降低熱電阻。在某些實施例中，TIM 164之一表面區域可大於晶粒102之一表面區域，且TIM 164可橫向延伸通過晶粒102之邊緣而接觸模塑料116 (例如，參見圖5B)。在其他實施例中，TIM 164可僅部分覆蓋晶粒102之一底部表面。舉例而言，可取決於封裝設計而將TIM 164局域化並僅放置於晶粒102之熱點(或其他選擇性區域)及/或底部封裝150 (例如，晶粒152上之熱點)上。 可將一 散熱器172附接至與裝置封裝150相對之裝置封裝130之一側，以進一步改良裝置封裝100之散熱。舉例而言，散熱器172可消散自晶粒102及晶粒152傳輸之熱量。在某些實施例中，散熱器172具有一高導熱性(舉例而言，介於約200 W/m·K與約400 W/m·K (或更多)之間)，且可係使用一金屬、一金屬合金或諸如此類來形成。舉例而言，散熱器172可包括金屬及/或金屬合金，諸如Al、Cu、Ni、Co、上述材料之組合及諸如此類。一第二TIM 174可將散熱器172附接至裝置封裝150。散熱器172可增加裝置封裝150之剛性，此有利地減小封裝100之翹曲。因此，一實施例PoP包含有利地減小翹曲且改良熱耗散之熱管理構件。額外構件亦可被接合至封裝100。舉例而言，另一裝置晶粒、中介層、封裝基板、印刷電路板、一主機板及諸如此類(未展示)可藉由連接器160接合至封裝100。 圖6至圖10圖解說明根據某些替代實施例之製造一裝置封裝200之中間階段之剖面圖。封裝200可係類似於封裝100，其中相似元件符號指示相似元件。參考圖6，藉由一DAF 112將一半導體晶粒102附接至一載體基板110。在晶粒102周圍形成一模塑料116，且模塑料116沿著晶粒102之側壁延伸。模塑料116及晶粒102之頂部表面可係實質上水平。 在圖7中，在晶粒102及模塑料116上方形成扇出型重佈層118。重佈層118可經電連接至晶粒102，且重佈層可橫向延伸通過102而至模塑料116上。重佈層118包含經形成於一或多個聚合物層122中之各種導電構件120。在重佈層118經形成之後，可移除載體110及DAF 112，如藉由圖8所圖解說明。 如藉由圖8進一步圖解說明，可使用(舉例而言)一雷射剝蝕製程，將模塑料116中之開口202圖案化。開口202可延伸穿過模塑料116以暴露重佈層118中之導電構件(未在圖8中明確圖解說明)。接下來，在圖9中，使用(舉例而言)一植球製程在開口202中形成焊球204。焊球204可延伸穿過模塑料116，且焊球204之一部分可進一步延伸通過模塑料116之一頂部表面。因此，根據某些實施例而形成一第一封裝130。 圖10圖解說明經接合至一底部封裝150之封裝130。底部封裝150可包含一晶粒152、圍繞晶粒152之一模塑料154、電連接至晶粒152之重佈層158，及外部連接器(例如，UBM 162/連接器160)。底部封裝150可進一步包含經放置於開口208中之焊球206，焊球206延伸穿過模塑料154。可將焊球206接合至封裝150中之焊球204。舉例而言，可將焊球204與焊球206對準、使其接觸並對其進行回銲，以便接合封裝130與封裝150。因此，封裝130及封裝150中之各種構件(例如，晶粒102及152以及重佈層118及158)可係電連接的。在其他實施例中，底部封裝150可包含一不同組態。一 TIM 164可橫跨封裝130與封裝150之間之一間隙170。舉例而言，TIM 164可接觸晶粒102之一底部表面及封裝150 (例如，晶粒152)之一頂部表面。因此，TIM 164可提供自底部封裝150至頂部封裝130之一散熱路徑，如由箭頭168所指示。可進一步將一散熱器172附接至與TIM 164相對的封裝130之一表面。因此，可改良封裝200之熱效能。此外，散熱器172可有利地減小封裝200之翹曲。 圖11至圖13圖解說明根據某些其他實施例之製造一封裝300之中間階段之剖面圖。封裝300可係類似於封裝100，其中相似元件符號指示相似元件。首先參考圖11，一基板302具有經放置於其中之導電構件304。在一實施例中，導電構件304可係形成於可包含低介電係數材料之一或多個介電層中。在另一實施例中，基板302係一封裝基板，且導電構件304可經形成為一或多個增堆層。在此等實施例中，基板302可進一步包含一封裝芯及經電連接在封裝芯之相對側上之導電構件的一或多個貫穿通路。 可在封裝基板302上方形成一 模塑料306 (或其他絕緣材料)。此外，模塑料306可包含一腔308及一或多個開口310。開口310及腔308可延伸穿過模塑料306以暴露封裝基板302上之導電構件(未展示)。可(舉例而言)藉由雷射鑽孔、光微影及/或其他蝕刻製程，將模塑料306中之開口310及腔308圖案化。 在開口310及腔308經圖案化之後，可將焊球312放置於開口310中，如由圖12所圖解說明。舉例而言，可使用一植球製程來將焊球312放置於開口310中。如藉由圖12進一步圖解說明，可將晶粒102至少部分地放置於腔308中，並將經接合至封裝基板302之晶片倒置。舉例而言，晶粒102可包含外部連接器312，外部連接器312可係銲料凸塊(諸如C4凸塊)、微凸塊、BGA球及諸如此類。在各種實施例中，腔308可經圖案化為具有一充分大表面積，以便容納晶粒102。舉例而言，腔308之一橫向尺寸可大於晶粒102之一橫向尺寸。因此，可形成一頂部封裝320。在其他實施例中，除開口310中之焊球312以外，頂部封裝320亦可包含具有銲料帽(例如，類似於銲料帽124)之TIV (例如，類似於TIV 114)，或以TIV代替焊球312。 圖13圖解說明接合至一底部封裝150之封裝320。底部封裝150可包含一晶粒152、圍繞晶粒152之一模塑料154、電連接至晶粒152之重佈層158及外部連接器(例如，UBM 162/連接器160)。底部封裝150可進一步包含在開口316中延伸穿過模塑料154之焊球314。可將焊球314接合至封裝320中之焊球312。舉例而言，可將焊球314與焊球312對準、使其接觸並對其進行回銲以便接合封裝320與封裝150。因此，封裝130及封裝150中之各種構件(例如，晶粒102、封裝基板302、晶粒152及重佈層118)可係電連接的。在其他實施例中，底部封裝150可包含一不同組態。 一TIM 164可橋接封裝320與封裝150之間的一間隙170。舉例而言，TIM 164可接觸晶粒102之一底部表面及封裝150之一頂部表面，因此，TIM 164可提供用以自底部封裝150至頂部封裝320消散熱量之一散熱路徑，如藉由箭頭168所指示。可進一步將一散熱器172附接至與TIM 164相對的封裝320之一表面。因此，可改良封裝300之熱效能。此外，散熱器172可有利地減小封裝300之翹曲。 圖14圖解說明根據某些實施例之用於形成一裝置封裝之一製程流程400。在步驟402中，提供一第一封裝。第一封裝可包含具有一暴露背面之一半導體晶粒(例如，晶粒102)。貫穿說明，一背面可用於闡述與一基板(具有形成於其上之主動裝置及功能電路)之一側相對的一晶粒或該基板之一表面。接下來在步驟404中，提供一底部封裝(例如，封裝150)。可將一TIM (例如，TIM 164)放置於底部封裝之一頂部表面上。在步驟406中，將頂部封裝與底部封裝接合在一起使得TIM接觸半導體晶粒之一底部表面。TIM可提供自底部封裝至頂部封裝之一熱耗散路徑。亦可將額外構件附接至封裝。舉例而言，可將一散熱器(例如，散熱器172)附接至與底部封裝相對的頂部封裝之一側。 各種實施例包含具有至少兩個接合式裝置封裝之一裝置封裝，其中將一TIM放置於兩個封裝之間。TIM可接觸該等裝置封裝中之一頂部裝置封裝中之一半導體晶粒之一底部表面。可將來自該底部封裝之熱量有利地耗散至該頂部封裝並(舉例而言)耗散至該頂部封裝上方之一散熱器。因此，可改良一實施例封裝之熱效能及可靠性。該散熱器可進一步改良該頂部封裝之勁度，此可有利地減小翹曲。 根據一實施例，一種封裝包含：一第一封裝；一熱界面材料(TIM)，其接觸該第一封裝之一頂部表面；及一第二封裝，其接合至該第一封裝。該第二封裝包含一第一半導體晶粒，且該TIM接觸該第一半導體晶粒之一底部表面。該封裝進一步包含一散熱器，其放置於與該第一封裝相對的該第二封裝之一表面上。 根據另一實施例，一種封裝包含：一第一晶粒；一第一模塑料，其沿著該第一晶粒之側壁延伸；一聚合物層，其在該第一晶粒之一頂部表面上；及一第二晶粒，其在該第一晶粒上方且藉由一間隙與該第一晶粒分離，該聚合物層橫跨該間隙且接觸該第二晶粒之一底部表面。該封裝進一步包含：一第二模塑料，其沿著該第二晶粒之側壁延伸；及一散熱器，其在該第二晶粒上方。該第一模塑料及該第二模塑料係藉由該間隙分離。 根據又一實施例，一種方法包含：提供具有一第一半導體晶粒之一第一封裝，提供在一頂部表面上具有一熱界面材料(TIM)之一第二封裝，及將該第一封裝接合至該第二封裝以形成一接合式封裝。該TIM接觸該接合式封裝中之該第一半導體晶粒之一底部表面。該方法進一步包含將一散熱器附接至與該TIM相對的該第一封裝之一側。 前述內容概述數項實施例之特徵，使得熟習此項技術者可較好地理解本揭露之態樣。熟習此項技術者應瞭解，其可容易地將本揭露用作用於設計或修改其他製程及結構以實現本文中所引入實施例之相同目的及/或達成相同優勢之一基礎。熟習此項技術者亦應意識到，此等等效構造並不脫離本揭露之精神及範疇，且應意識到其可在不脫離本揭露之精神及範疇之情況下在本文中作出各種改變、替代及更改。
100‧‧‧裝置封裝/接合式裝置封裝/封裝
102‧‧‧半導體晶粒/晶粒
104‧‧‧接點墊
106‧‧‧鈍化層
108‧‧‧導電柱
109‧‧‧介電層
110‧‧‧載體/載體基板
112‧‧‧晶粒附接膜
114‧‧‧TIV
116‧‧‧模塑料
118‧‧‧重佈層
120‧‧‧導電構件
120A‧‧‧導電線
120B‧‧‧導電通路
122‧‧‧聚合物層
124‧‧‧銲料帽
130‧‧‧第一裝置封裝/裝置封裝/封裝/第一封裝/頂部封裝
150‧‧‧第二裝置封裝/裝置封裝/封裝/底部封裝
152‧‧‧晶粒
154‧‧‧模塑料
156‧‧‧TIV
158‧‧‧重佈層
160‧‧‧外部連接器/連接器
162‧‧‧凸塊下金屬
164‧‧‧熱界面材料
168‧‧‧箭頭
170‧‧‧間隙
172‧‧‧散熱器
174‧‧‧熱界面材料
200‧‧‧裝置封裝/封裝
202‧‧‧開口
204‧‧‧焊球
206‧‧‧焊球
208‧‧‧開口
300‧‧‧封裝
302‧‧‧基板/封裝基板
304‧‧‧導電構件
306‧‧‧模塑料
308‧‧‧腔
310‧‧‧開口
312‧‧‧焊球/外部連接器
314‧‧‧焊球
320‧‧‧頂部封裝/封裝
T1‧‧‧厚度
當與附圖一起閱讀時，依據以下詳細說明最佳地理解本揭露之態樣。注意，根據行業中之標準實踐，各種構件並不按比例繪製。事實上，為論述之清晰起見，可任意地增大或減小各種構件之尺寸。 圖1至圖5A及圖5B圖解說明根據某些實施例之形成一半導體裝置封裝之各種中間階段之剖面圖。 圖6至圖10圖解說明根據某些其他實施例之形成一半導體裝置封裝之各種中間階段之剖面圖。 圖11至圖13圖解說明根據某些其他實施例之形成一半導體裝置封裝之各種中間階段之剖面圖。 圖14圖解說明根據某些實施例之形成一半導體裝置封裝之一製程流程。
100‧‧‧裝置封裝/接合式裝置封裝/封裝
102‧‧‧半導體晶粒/晶粒
114‧‧‧TIV
116‧‧‧模塑料
118‧‧‧重佈層
124‧‧‧銲料帽
130‧‧‧第一裝置封裝/裝置封裝/封裝/第一封裝/頂部封裝
150‧‧‧第二裝置封裝/裝置封裝/封裝/底部封裝
152‧‧‧晶粒
154‧‧‧模塑料
156‧‧‧TIV
158‧‧‧重佈層
160‧‧‧外部連接器/連接器
162‧‧‧凸塊下金屬
164‧‧‧熱界面材料
168‧‧‧箭頭
170‧‧‧間隙
172‧‧‧散熱器
174‧‧‧熱界面材料

Claims (1)

  1. 一種封裝，其包括： 一第一封裝； 一熱界面材料(TIM)，其接觸該第一封裝之一頂部表面； 一第二封裝，其經接合至該第一封裝，其中該第二封裝包括一第一半導體晶粒，且其中該TIM接觸該第一半導體晶粒之一底部表面；及 一散熱器，其經放置於與該第一封裝相對之該第二封裝之一表面上。
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