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TW200739763A - Packaging process of power chips - Google Patents

Packaging process of power chips

Info

Publication number
TW200739763A
TW200739763A TW095112872A TW95112872A TW200739763A TW 200739763 A TW200739763 A TW 200739763A TW 095112872 A TW095112872 A TW 095112872A TW 95112872 A TW95112872 A TW 95112872A TW 200739763 A TW200739763 A TW 200739763A
Authority
TW
Taiwan
Prior art keywords
circuit board
groove
packaging process
forming
chip
Prior art date
Application number
TW095112872A
Other languages
Chinese (zh)
Other versions
TWI297923B (en
Inventor
Hao-Jan Yu
Chung-Chi Chang
Shang-Wei Liu
Original Assignee
Brilliant Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brilliant Technology Co Ltd filed Critical Brilliant Technology Co Ltd
Priority to TW095112872A priority Critical patent/TW200739763A/en
Publication of TW200739763A publication Critical patent/TW200739763A/en
Application granted granted Critical
Publication of TWI297923B publication Critical patent/TWI297923B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Led Device Packages (AREA)

Abstract

A packaging process of power chips comprises steps of: using a metal sheet to form a cup-shaped groove; forming at least one opening on the groove; forming holes on the circuit board corresponding to groove; forming a plurality of contact points on the circuit board; connecting the groove and the circuit board- by making the groove embedded in the circuit board; making the contact points on the circuit board position to the opening of the groove and the bottom surface of the groove protrude out of the back surface of the circuit board, and placing chips in the cup-shaped groove; laying lead from the chip to the contact points on the circuit board corresponding to the openings by wire bonding to form electrical connection; encapsulating the chip; and combining the wire bonded and encapsulated package device with heat dissipating metal substrate, thereby forming a power chip package with good thermal conductivity, fast thermal dissipation, electrothermal separation, simple and stable structure. When the packaging process is for a light emitting power chip, a light gain due to the metal cup reflection will be obtained. The packaging process is suitable for semiconductor and optoelectronic industries, providing good chip package and mold structure design.
TW095112872A 2006-04-11 2006-04-11 Packaging process of power chips TW200739763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095112872A TW200739763A (en) 2006-04-11 2006-04-11 Packaging process of power chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095112872A TW200739763A (en) 2006-04-11 2006-04-11 Packaging process of power chips

Publications (2)

Publication Number Publication Date
TW200739763A true TW200739763A (en) 2007-10-16
TWI297923B TWI297923B (en) 2008-06-11

Family

ID=45069239

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095112872A TW200739763A (en) 2006-04-11 2006-04-11 Packaging process of power chips

Country Status (1)

Country Link
TW (1) TW200739763A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455376B (en) * 2010-04-15 2014-10-01 I Chiun Precision Ind Co Ltd Method for producing electro-thermal separation type light emitting diode support structure
CN113130467A (en) * 2021-04-12 2021-07-16 深圳市科彤科技有限公司 COB display panel with automatically adjusted contrast
TWI824824B (en) * 2022-08-04 2023-12-01 創世電股份有限公司 Power chip package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455376B (en) * 2010-04-15 2014-10-01 I Chiun Precision Ind Co Ltd Method for producing electro-thermal separation type light emitting diode support structure
CN113130467A (en) * 2021-04-12 2021-07-16 深圳市科彤科技有限公司 COB display panel with automatically adjusted contrast
CN113130467B (en) * 2021-04-12 2022-10-18 深圳市科彤科技有限公司 COB display panel with automatically adjusted contrast
TWI824824B (en) * 2022-08-04 2023-12-01 創世電股份有限公司 Power chip package

Also Published As

Publication number Publication date
TWI297923B (en) 2008-06-11

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