SU1690183A1 - Comparator - Google Patents

Abstract

The invention relates to a pulse technique and is intended to build comparison devices that record the moment when the voltage amplitude controlled is greater or less than a predetermined value. The purpose of the invention is to increase speed and expand the scope by eliminating a pulsed mode in the output signal. The comparator contains the threshold elements 1 and 2, the input bus 3, the installation voltage bus 4, the common bus 5, the driver 6 of the delayed front of the input voltage, the D-flip-flop 7 and the output bus 8. The speed is achieved by allowing tolerance control by the threshold elements 1 and 2 amplitudes of the monitored signal in the initial stage of an increase in the alternating monitored voltage. The use of the O-flip-flop 7 eliminates ripple in the output signal due to the unambiguous triggering of the D-flip-flop 7. 2 Il.

Description

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The invention relates to a pulse technique and is intended to build comparison devices that record the moment when the voltage amplitude is controlled to be greater or less than a predetermined value.

The purpose of the invention is to increase speed.

Fig. 1 is a schematic diagram of a comparator; 2 shows timing diagrams for his work.

The comparator contains threshold elements 1 and 2, an input bus 3, an installation voltage bus 4, a common bus 5, an input voltage delayed driver 6, a D-flip-flop 7 and an output bus 8, the first input of the first threshold element 1 being connected to the input bus 3, the output of the D-flip-flop 7 - with the output bus 8, the D-input of the D-flip-flop 7 is connected to the output of the second threshold element 2, the output of the driver 6 of the delayed front of the input voltage is connected to the input of the D-flip-flop 7, and the input to the output the first threshold element 1, the second input of which is connected to the common bus 5, a first input - to the input bus 3 and the second input of the second threshold element is connected with the mounting rail 1 voltage.

The comparator works as follows.

Let at time ti the voltage UBX exceed the potential of the common bus 5 and at the output of the threshold element 1 a front edge of the input voltage is formed, which is delayed by the driver 6 of the delayed front of the input voltage for some time. The following two cases of work are possible.

At the moment of fixing the delayed front from the output of the driver 6, the voltage UBX reaches the voltage on the bus 4 of the installation voltage and therefore the voltage from the output of the threshold element 2 remains equal to the previous state and the D-flip-flop 7 does not change its state, which indicates that the input voltage is less than a certain specified value.

At the time t of the formation of a delayed front from the output of shaper 6 (time instant te), the voltage UBx on the input bus 3 exceeds the voltage 1) y

on the bus 4 of the installation voltage and at the output of the threshold element 2, the potential state of the output voltage changes and therefore changes its state of the D-trigger and on the output bus 8

a potential is generated, indicating that the input alternating voltage on the input bus 3, at its maximum amplitude, is more than a predetermined value.

When the input voltage UBX decreases and becomes less than the value of the installation voltage on bus 4, threshold element 2 will return to its original state, while D-flip-flop 7 will not change its state until its formation

the next voltage drop from the output of the imager 6. If the input signal exceeds the voltage on the bus 4 by its maximum amplitude, then the output of the threshold element 2 will be pulsating

voltage, while at the output of the D-flip-flop 7, the voltage will be constant. With this, an exception is achieved in the pulse output.

Claims (1)

Invention Formula A comparator containing a D-trigger, two threshold elements, an input bus, an installation voltage bus, an output bus connected to the output of the D-trigger, The D-input of which is connected to the output of the second threshold element, the inverting input of the first threshold element is connected to the input bus, characterized in that, in order to improve speed, a delay front of the input voltage, the output of which is connected to the C-input D-, is introduced into it trigger, input - with the output of the first threshold element, inverting input which is connected to a common bus, while the inverting input of the second threshold element is connected to the bus voltage of the installation voltage, and the non-inverting input of the second threshold element is connected to input bus.