SU1257823A1 - Pulse burst-to-rectangular pulse converter - Google Patents

Abstract

The invention can be used in telemechanics systems and information collection systems. The purpose of the invention is to improve the accuracy of converting .i.COB burst into a rectangular pulse. In order to achieve a desired goal, a device containing an OR 2 element, a shaper of 3 pulses, a counter 5, an RS flip-flop 6, an element of AND 7 and a generator of 10 pulses, has additionally introduced inverter 4, a D-trigger 9, and an Element 11. Former 12 impu1y,)) 1 and N1INY 13 and 14 mouths; 1 () 1gkp and zero, respectively. I i:: tsD СЛ Nj 00 ГЧЭ /, -А ;;

Description

The invention relates to a pulse technique and can be used in telemechanics systems and information acquisition systems.

The purpose of the invention is to improve the accuracy of converting a burst of pulses into a rectangular pulse.

The drawing shows an electrical functional circuit diagram of the device.

The pulse train to square pulse converter contains an input bus 1 connected to the first input of element 2 OR, to the input of the first driver 3 pulses, to the input of inverter 4, to the installation input of the bis counter R input of the RS flip-flop 6, whose S input is connected with the output of the inverter 4, and the output with the first input of the element 7 And the second input of which is connected to the output bus 8 and the output of the D-flip-flop 9, the third input of the element 7 And is connected to the output of the generator 10 pulses, and the output with the counting input of the counter 5 whose bit outputs are connected with the inputs of the element 11 And, the output of which is connected to the second input of the element 2 OR, the output of which through the second driver 12 pulses connected to the C-input of D-flip-flop 9, the D-input of which is connected to the output of the first driver of the three pulses, S-input connected to bus 13 installation unit, and R-input - with bus 14 installation zero.

The converter works as follows.

In the initial state (in the absence of input signals) RS-flip-flop 6 is in the single state, D-flip-flop 9 is in the zero state. Input installation "1 (input S) D-flip-flop 9 is connected to the bus 13 of the logical unit. For the initial installation of D-flip-flop 9, its R-input is connected to the initial installation scheme in the "O.

With the arrival of the first pulse at the input of the converter, the counter 5 is set to "O", the RS flip-flop 6 changes to the "O" state and the signal from its output closes element 7 And to pass the counting pulses from the generator 10 pulses. At the same time, the signal from the input bus I arrives at the shaper of 3 pulses, where the input pulse is expanded in duration by double the duration of the transients in the D-flip-flop.

Then from the output of the imaging unit 3, the signal enters the D-input of the D-flip-flop 9 and, in addition, the input signal from the input bus 1 through the element 2 OR enters the 12-pulse former, which generates on the front of the input pulse with a small delay equal to the duration of the transient processes in the D-flip-flop, a narrow sync pulse arriving at the C-input of the D-flip-flop 9, as a result of which the D-flip-flop 9 is set to one state, fixing the beginning of the stack. Shaper 12 pulses can be

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implemented by sequentially combining typical shapers in terms of f); ont and shear pulses.

The signal from the output of D-flip-flop 9 is fed to the first input of the element 7 And, preparing it for opening. When the input pulse is over, RS flip-flop 6 will go into one state and open logic gate 7 for passing signals from generator 10 pulses to the input of counter 5.

If the pause between the pulses at the input of the converter is less than the allowed fixed pause, with the arrival of the next pulse, the counter 5 is reset to "O", the RS flip-flop 6 is set to the state "O by closing the circuit 7".

The duration of a fixed pause is established by appropriately connecting the inputs of element 11 and to the bit outputs of counter 5. Element 11 And connected to different outputs of the counter performs the functions of a decoder. Element 11 And decrypts the contents of the counter 5, and, therefore, if it is triggered when the N position of the counter 5, then the value of the fixed pause will be if.p. N- Ti, where Ti is the period of the pulses of the reference generator.

If the pause between the pulses at the input reaches the value of the permissible fixed pause, element 11 I will trigger. The signal from its output through element 2 OR will go to the input of the driver 12 pulses and D-flip-flop 9 will be set to the state "O. A rectangular pulse at the output of the converter is formed. In this case, the zero signal from the single output of the D-flip-flop 9 closes the circuit 7 and for passing the pulses of the generator 10 pulses.

With the arrival of the first pulse of the next packet, the formation cycle is repeated.

Claims (1)

Invention Formula A pulse train converter into a rectangular pulse containing an input bus connected to the input of a pulse shaper, an RS flip-flop, whose R-input is connected to the first input of the OR element, a pulse counter whose discharge outputs are connected to the inputs of the And element, the output bus, a generator pulses, characterized in that, in order to increase the conversion accuracy, a D-flip-flop, an inverter, a zero setting bus, a unit installation bus, an additional pulse shaper, an additional AND element, and the first input o is connected to the output of the RS-flip-flop, the second input is with the output of the D-flip-flop and the output bus, the third input is with the output of the pulse generator, and the output is with the counting input of the counter, the setup input of which is connected to the R-input of the RS flip-flop and the input bus, the inverter output is connected to the S-input of the RS flip-flop, the second input element 1257823 3A OR is connected to the output of the element I, and is connected to the output of the pulse former, move through the additional driver -S-input - with the unit installation bus, and with a D-trigger C input, a D-input of a co-R input with a zero setting bus.