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KR940002438B1 - Method of making semiconductor device - Google Patents

Method of making semiconductor device Download PDF

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Publication number
KR940002438B1
KR940002438B1 KR1019910011279A KR910011279A KR940002438B1 KR 940002438 B1 KR940002438 B1 KR 940002438B1 KR 1019910011279 A KR1019910011279 A KR 1019910011279A KR 910011279 A KR910011279 A KR 910011279A KR 940002438 B1 KR940002438 B1 KR 940002438B1
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South Korea
Prior art keywords
nitride layer
sog
depositing
nitride
layer
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KR1019910011279A
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Korean (ko)
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KR930003253A (en
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고상기
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금성일렉트론 주식회사
문정환
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Priority to KR1019910011279A priority Critical patent/KR940002438B1/en
Publication of KR930003253A publication Critical patent/KR930003253A/en
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Publication of KR940002438B1 publication Critical patent/KR940002438B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

depositing a buffer oxide layer and first nitride layer on a substrate, and etching the nitride layer of an active area; filling the etched portion of the nitride layer with SOG, etching the resultant structure to create a step height with the nitride layer, and depositing a second nitride layer; anisotropically etching the second nitride layer to form the sidewalls of the second nitride layer, and removing the SOG and the buffer oxide layer under the SOG; forming a gate oxide layer on the portion where the SOG is removed to deposit a gate poly; and anisotropically etching the gate poly, and stripping the sidewalls of the first and second nitride layers, thereby enabling a submicron pattern to be formed.

Description

반도체 미세 소자 제조방법Semiconductor Micro Device Manufacturing Method

제1도는 종래의 반도체 소자 제조공정 단면도.1 is a cross-sectional view of a conventional semiconductor device manufacturing process.

제2도는 본 발명의 반도체 미세 소자 제조공정 단면도.2 is a cross-sectional view of a semiconductor microdevice fabrication process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 버퍼 산화막1: silicon substrate 2: buffer oxide film

3 : 제1질화막 4 : 포토레지스트3: first nitride film 4: photoresist

5 : SOG 6 : 제2질화막5: SOG 6: second nitride film

7 : 사이드 월 8 : 게이트 산화막7: side wall 8: gate oxide film

9 : 게이트 폴리9: gate pulley

본 발명은 섭 미크론(Submicron) 이하의 반도체 미세 소자 제조방법에 관한 것으로, 특히 현재의 기술과 장비 수준에서도 적용할 수 있는 반도체 미세 소자의 패터닝에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor microelement of submicron or less, and more particularly, to patterning of a semiconductor microelement, which can be applied at the current technology and equipment level.

현재의 옵티컬 리토 그래피(Iithography) 기술을 이용한 패터닝 한계는 공정상 0.2~0.4㎛로 알려져 있다.The limit of patterning using current optical lithography technology is known to be 0.2 ~ 0.4㎛ in process.

이를 위해 종래의 기술에서는 제1a도에 도시된 바와 같이, 먼저 실리콘 기판에 액티브 영역과 필드 영역을 형성한 후, 게이트 산화막, 게이트 폴리 및 HTO(High Temperature Oxide)를 차례로 데포지션 한다. 이어서 포토레지스트로 게이트 마스크를 형성한 뒤 에치하므로 게이트 산화막, 게이트 폴리 및 HTO가 적층된 구조를 얻게 된다. 그 후 게이트 마스크를 벗겨내므로 게이트를 형성한다.(제1b도).To this end, in the related art, as shown in FIG. 1A, first, an active region and a field region are formed on a silicon substrate, and then a gate oxide film, a gate poly, and a high temperature oxide (HTO) are sequentially deposited. Subsequently, the gate mask is formed and etched with the photoresist, thereby obtaining a structure in which the gate oxide film, the gate poly, and the HTO are stacked. The gate mask is then peeled off to form a gate (FIG. 1b).

이와 같은 소자 제조방법에서는 장비와 기술의 한계로 0.4㎛ 이하의 패터닝이 불가능하다. 따라서 소자가 상대적으로 커지게 되고 집적도의 한계에 부딛치게 된다.In the device manufacturing method as described above, patterning of 0.4 μm or less is impossible due to limitations in equipment and technology. As a result, the device becomes relatively large and faces the limit of integration.

본 발명은 이러한 문제를 해결하기 위한 것으로서, 각 구성 물질간의 선택도 및 이방성 에치를 이용하여 미세 패턴의 실현을 가능하게 하였다.The present invention has been made to solve such a problem, and has made it possible to realize a fine pattern by using selectivity and anisotropic etch between the respective constituent materials.

본 발명의 제조방법을 첨부된 도면 제2도를 참조하여 설명하면 다음과 같다.Referring to Figure 2 of the accompanying drawings, the manufacturing method of the present invention will be described.

먼저 제2a도와 같이, 액티브 영역 및 필드 영역이 형성된 실리콘 기판(1) 상에 버퍼 산화막(2)및 제1질화막(3) 층을 차례로 데포지션 한 후, 포토레지스트(4) 마스크를 이용하여 상기 액티브 영역 일부의 질화막(3) 층을 식각한다. 마스크의 제거에 이어서 상기 질화막층의 식각된 부분을 SOG(5)(Spin On Glass)로 채우고 기존의 질화막층의 단차가 생기도록 에치한 다음, 그 위에 제2질화막(6) 층을 데포지션한다(제2b도).First, as shown in FIG. 2A, the buffer oxide film 2 and the first nitride film 3 are sequentially deposited on the silicon substrate 1 on which the active region and the field region are formed, and then, the photoresist 4 mask is used. The nitride layer 3 layer of a part of the active region is etched. Following removal of the mask, the etched portion of the nitride film layer is filled with SOG (5) (Spin On Glass) and etched to create a step of the existing nitride film layer, and then the second nitride film 6 layer is deposited thereon. (Figure 2b).

계속해서 상기 제2질화막층을 이방성 에치하여 SOG층 모서리 상부에 제2질화막의 사이드 월(7)을 형성한 다음, 습식 에치로서 상기 SOG(5) 및 SOG 하부의 버퍼 산화막(2)을 모두 제거한다. 그후 상기 SOG를 제거한 자리에 게이트 산화막(8)을 얇게 데포지션 한 후, 게이트 폴리(9)를 두껍게 데포지션 한다(제2c도).Subsequently, the second nitride layer is anisotropically etched to form sidewalls 7 of the second nitride layer on top of corners of the SOG layer, and then the SOG 5 and the buffer oxide layer 2 under the SOG are removed as a wet etch. do. Thereafter, the gate oxide film 8 is thinly deposited in the place where the SOG is removed, and the gate poly 9 is thickly deposited (FIG. 2C).

상기의 두껍게 데포지션한 게이트 폴리를 마스크 없이 이방성 건식 에치하여 실제의 게이트 부분을 형성하고(제2d도), 제1질화막 및 제2질화막의 사이드 월을 제거하므로 모든 공정이 끝나게 된다(제2d도).The thickly deposited gate poly is anisotropically dry etched without a mask to form an actual gate portion (FIG. 2D), and the sidewalls of the first nitride film and the second nitride film are removed, thereby completing all processes (FIG. 2D). ).

이와 같은 제조방법을 사용하므로 옵리컬 리토그래피 기술로는 정의할 수 없는 미세 패턴을 형성할 수 있게 된다.By using such a manufacturing method it is possible to form a fine pattern that cannot be defined by optical lithography techniques.

Claims (1)

액티브 영역 및 필드 영역이 형성된 실리콘 기판상에 버퍼 산화막 및 제1질화막층을 차례로 데포지션한 후, 포토레지스트 마스크를 이용하여 액티브 영역 일부의 질화막층을 식각하는 단계와, 상기 질화막층이 식각된 부분을 SOG로 채우고 기존의 질화물층과 단차가 생기도록 에치한 다음 제2질화막층을 데포지션하는 단계와, 상기 제2질화막층을 이방성 에치하여 SOG 모서리 상부에 제2질화막의 사이드 월을 형성한 후, 습식 에치로서 SOG 및 SOG 하부의 버퍼 산화막을 모두 제거하는 단계와, 계속해서 상기 SOG를 제거한 자리에 게이트 산화막을 형성한 후 게이트 폴리를 두껍게 데포지션하는 단계와, 상기 두껍게 데포지션한 게이트 폴리를 마스크 없이 이방성 건식에치 하고, 제1질화막 및 제2질화막의 사이드 월을 스트립하는 단계를 포함하여 이루어지는 반도체 미세 소자 제조방법.Depositing a buffer oxide layer and a first nitride layer in order on the silicon substrate on which the active region and the field region are formed, and then etching a nitride layer of a portion of the active region using a photoresist mask, and a portion where the nitride layer is etched Is filled with SOG and etched to form a step with an existing nitride layer, and then depositing a second nitride layer, and anisotropically etching the second nitride layer to form sidewalls of the second nitride layer on top of SOG edges. Removing both the SOG and the buffer oxide film under the SOG as a wet etch, and subsequently forming a gate oxide film where the SOG is removed, and then depositing a thick gate poly, and depositing the thickly deposited gate poly. And anisotropic dry etching without a mask, and stripping sidewalls of the first nitride film and the second nitride film. Semiconductor micro device manufacturing method.
KR1019910011279A 1991-07-04 1991-07-04 Method of making semiconductor device KR940002438B1 (en)

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Application Number Priority Date Filing Date Title
KR1019910011279A KR940002438B1 (en) 1991-07-04 1991-07-04 Method of making semiconductor device

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Application Number Priority Date Filing Date Title
KR1019910011279A KR940002438B1 (en) 1991-07-04 1991-07-04 Method of making semiconductor device

Publications (2)

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KR930003253A KR930003253A (en) 1993-02-24
KR940002438B1 true KR940002438B1 (en) 1994-03-24

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