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KR920017115A - 반도체기억장치 - Google Patents

반도체기억장치 Download PDF

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Publication number
KR920017115A
KR920017115A KR1019920001452A KR920001452A KR920017115A KR 920017115 A KR920017115 A KR 920017115A KR 1019920001452 A KR1019920001452 A KR 1019920001452A KR 920001452 A KR920001452 A KR 920001452A KR 920017115 A KR920017115 A KR 920017115A
Authority
KR
South Korea
Prior art keywords
sense amplifier
control signal
memory device
semiconductor memory
activated
Prior art date
Application number
KR1019920001452A
Other languages
English (en)
Other versions
KR950001429B1 (ko
Inventor
야수히로 훗타
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 하루오, 샤프 가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR920017115A publication Critical patent/KR920017115A/ko
Application granted granted Critical
Publication of KR950001429B1 publication Critical patent/KR950001429B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예를 표시하는 블록도, 제5도는 본 발명의 또다른 실시예에 사용되는 센스앰프를 표시하는 회로도.

Claims (4)

  1. 메모리셀에 기억되는 데이터 판독하는 1출력신호선에 제공되는 복수의 센스앰프와, 상기 센스앰프는 서로 병렬로 접속되고, 그리고 상기 센스앰프는 선택적으로 활성화되는 제어신호를 생성하는 제어신호 생성회로를 포함하는 반도체기억장치.
  2. 제1항에 있어서, 적어도 하나의 상기 센스앰프의 구동가능 출력은 적어도 다른 하나의 상기 센스앰프의 것보다 더 큰 반도체기억장치.
  3. 제2항에 있어서, 상기 제어신호 생성회로는 더큰 구동가능출력을 가지는 상기 적어도 하나의 센스앰프가 데이터가 판독되게 되는 어드레스가 전환된 후 소정기간동안 활성화되고 그리고 적어도 다른 하나의 센스앰프가 상기 소정기간과 다른 기간동안 활성화되도록 상기 제어신호를 생성하는 반도체기억장치.
  4. 제1항에 있어서, 상기 센스앰프는 차동형태 센스앰프인 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920001452A 1991-02-13 1992-01-31 반도체기억장치 KR950001429B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007891A JP2680936B2 (ja) 1991-02-13 1991-02-13 半導体記憶装置
JP91-20078 1991-02-13

Publications (2)

Publication Number Publication Date
KR920017115A true KR920017115A (ko) 1992-09-26
KR950001429B1 KR950001429B1 (ko) 1995-02-24

Family

ID=12017067

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001452A KR950001429B1 (ko) 1991-02-13 1992-01-31 반도체기억장치

Country Status (5)

Country Link
US (1) US5291452A (ko)
EP (1) EP0499460B1 (ko)
JP (1) JP2680936B2 (ko)
KR (1) KR950001429B1 (ko)
DE (1) DE69223333T2 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3118472B2 (ja) * 1991-08-09 2000-12-18 富士通株式会社 出力回路
US5455802A (en) * 1992-12-22 1995-10-03 Sgs-Thomson Microelectronics, Inc. Dual dynamic sense amplifiers for a memory array
US6738357B1 (en) * 1993-06-09 2004-05-18 Btg International Inc. Method and apparatus for multiple media digital communication system
KR0172371B1 (ko) * 1995-04-26 1999-03-30 윤종용 반도체 메모리장치의 전원전압 발생회로
GB2304244B (en) * 1995-08-10 2000-01-26 Advanced Risc Mach Ltd Data processing system signal receiving buffers
DE19536486C2 (de) * 1995-09-29 1997-08-07 Siemens Ag Bewerter- und Verstärkerschaltung
JP3219236B2 (ja) * 1996-02-22 2001-10-15 シャープ株式会社 半導体記憶装置
US5668766A (en) * 1996-05-16 1997-09-16 Intel Corporation Method and apparatus for increasing memory read access speed using double-sensing
US5805006A (en) * 1997-04-28 1998-09-08 Marvell Technology Group, Ltd. Controllable integrator
KR100249160B1 (ko) * 1997-08-20 2000-03-15 김영환 반도체 메모리장치
JPH11203881A (ja) * 1998-01-12 1999-07-30 Mitsubishi Electric Corp データ読み出し回路
EP1647989A1 (en) * 2004-10-18 2006-04-19 Dialog Semiconductor GmbH Dynamical adaption of memory sense electronics
WO2009013814A1 (ja) * 2007-07-24 2009-01-29 Fujitsu Limited 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856198B2 (ja) * 1980-09-25 1983-12-13 株式会社東芝 半導体記憶装置
US4907201A (en) * 1986-05-07 1990-03-06 Mitsubishi Denki Kabushiki Kaisha MOS transistor circuit
JPS6386188A (ja) * 1986-09-30 1988-04-16 Toshiba Corp ダイナミツク型半導体記憶装置
JPS63171497A (ja) * 1987-01-08 1988-07-15 Mitsubishi Electric Corp 半導体集積回路装置
JPH0646513B2 (ja) * 1989-07-12 1994-06-15 株式会社東芝 半導体記憶装置のデータ読出回路
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories

Also Published As

Publication number Publication date
EP0499460A2 (en) 1992-08-19
US5291452A (en) 1994-03-01
EP0499460B1 (en) 1997-12-03
JPH04258895A (ja) 1992-09-14
JP2680936B2 (ja) 1997-11-19
DE69223333T2 (de) 1998-05-28
KR950001429B1 (ko) 1995-02-24
EP0499460A3 (en) 1993-10-06
DE69223333D1 (de) 1998-01-15

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