KR20160020991A - Low density parity check encoder with 16200 length and 3/15 rate, and method using the same - Google Patents

Abstract

Disclosed are a LDPC encoder, a decoder and a LDPC coding method. According to an embodiment of the present invention, the LDPC encoder comprises: a first memory configured to store a LDPC code word having the length of 16200 and a 3/15 coding rate; a second memory initialized to zero; and a processor performing an accumulation process of the second memory by using a matrix corresponding to a parity check matrix to generate the LDPC code word corresponding to information bits.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to an LDPC encoder having a length of 16,200, a coding rate of 3/15, and an LDPC encoding method using the LDPC encoder.

The present invention relates to an LDPC (Low Density Parity Check) code for correcting an error occurring in a wireless channel, and more particularly to an LDPC code applicable to a digital broadcasting system.

Current terrestrial TV broadcasting generates co-channel interference equivalent to three times the service change, so the same frequency can not be reused within three times the service radius. In this way, a region where the same frequency can not be reused is called a white space, and the occurrence of white space causes a very low spectral efficiency.

Therefore, in order to improve spectral efficiency, there has been a need to develop a transmission technique which is easy to remove white space and to reuse frequency, which focuses on receiving robustness.

Accordingly, IEEE Transactions on Broadcasting, vol. 58, No. 3, "Cloud Transmission: A New Spectrum-Reuse Friendly Digital Terrestrial Broadcasting Transmission System", which is easy to reuse and does not generate whitespace, is a terrestrial cloud Broadcasting technology was proposed.

With the terrestrial cloud broadcasting technology, broadcasters can transmit different broadcasting contents to one another nationwide through the same broadcasting channel. However, in order to achieve this, the receiver must be able to receive one or more terrestrial cloud broadcast signals in a region where signals transmitted from different transmitters overlap in a single frequency network, that is, in an overlapped region, and demodulate the received terrestrial cloud broadcast signals . That is, in a situation where co-channel interference exists and the timing and frequency synchronization of each transmission signal is not guaranteed, the receiver must be able to demodulate one or more cloud broadcast signals.

On the other hand, Korean Patent Laid-Open Publication No. 2013-0135746, entitled "LDPC Code for Terrestrial Cloud Broadcasting" discloses an LDPC code that is optimized for terrestrial cloud broadcasting and exhibits excellent performance at a low code rate (< 0.5).

However, Korean Patent Laid-Open Publication No. 2013-0135746 relates to a code length which is completely different from the LDPC code length used in the DVB broadcasting standard or the like, and the specific LDPC code method is silent.

An object of the present invention is to provide a new LDPC codeword having a codeword length of 16,200 and a coding rate of 3/15, which can be used in general use.

It is another object of the present invention to provide a method and apparatus for efficiently performing LDPC coding using a sequence having a number of rows corresponding to a value obtained by dividing the sum of 3240, which is the length of the systematic part of the LDPC codeword, and the length of the first parity part, And an LDPC coding method capable of performing LDPC coding.

According to an aspect of the present invention, there is provided an LDPC encoder comprising: a first memory for storing an LDPC codeword having a length of 16,200 and a coding rate of 3/15; A second memory initialized to zero; And a processor for performing accumulation on the second memory using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to information bits, do.

At this time, the accumulation may be performed at parity bit addresses updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword includes a systematic part corresponding to the information bits and having a length of 3240, a first parity part having a length of 1080 and a parity part corresponding to the double diagonal matrix included in the parity check matrix, And a second parity part having a length of 11880 corresponding to the identity matrix included in the first parity part.

At this time, the sequence is divided into a value obtained by dividing 3240, which is the length of the systematic part, by 360, the CPM size corresponding to the parity check matrix, and the value obtained by dividing 1080, which is the length of the first parity part, You can have rows.

At this time, the sequence may be represented by the following table.

[table]

First line: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988

Second line: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267

Third line: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003

Fourth line: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341

5th line: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561

6th line: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990

Line 7: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092

Line 8: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689

Ninth line: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893

10th line: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876

11th line: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810

Line 12: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272

In this case, accumulation may be performed while changing the rows of the series in units of the CPM size (L) of the parity check matrix.

According to another aspect of the present invention, there is provided an LDPC encoding method including: initializing a first memory and a second memory for storing an LDPC codeword; And performing accumulation on the second memory using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to the information bits do.

At this time, the accumulation may be performed at parity bit addresses updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword includes a systematic part having a length of 3240 corresponding to the information bits, a first parity part having a length of 1080 corresponding to the double diagonal matrix included in the parity check matrix, and a parity check matrix And a second parity part having a length of 11880 corresponding to the identity matrix included in the first parity part.

At this time, the sequence is divided into a value obtained by dividing 3240, which is the length of the systematic part, by 360, the CPM size corresponding to the parity check matrix, and the value obtained by dividing 1080, which is the length of the first parity part, You can have rows.

At this time, the sequence may be represented by the table.

Also, an LDPC decoder according to an embodiment of the present invention includes: a receiver for receiving a Low Density Parity Check (LDPC) codeword encoded using a sequence corresponding to a parity check matrix and represented by the table; And a decoding unit which performs decoding corresponding to the parity check matrix and restores information bits in the received LDPC codeword.

According to the present invention, a new LDPC codeword with a codeword length of 16200 and a coding rate of 3/15, which can be used in general use, is provided.

In addition, the present invention efficiently performs LDPC coding using a sequence having a number of rows corresponding to a value obtained by dividing the sum of 3240, which is the length of the systematic part of the LDPC codeword, and 1080, which is the length of the first parity part, can do.

1 is a block diagram illustrating a system for transmitting / receiving a broadcast signal according to an embodiment of the present invention.
2 is a flowchart illustrating a method of transmitting / receiving a broadcast signal according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.
5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention.
6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.
FIG. 7 is a graph illustrating the performance of a QC-LDPC code having a length of 16200 and a coding rate of 3/15 according to an exemplary embodiment of the present invention in comparison with E _b / N _o .

The present invention will now be described in detail with reference to the accompanying drawings. Hereinafter, a repeated description, a known function that may obscure the gist of the present invention, and a detailed description of the configuration will be omitted. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a system for transmitting / receiving a broadcast signal according to an embodiment of the present invention.

Referring to FIG. 1, it can be seen that the transmitter 10 and the receiver 30 perform communication via the wireless channel 20.

The transmitter 10 encodes information bits 11 of k bits in an LDPC encoder 13 to generate codewords of n bits. The codeword is modulated by modulator 15 and transmitted via antenna 17. The signal transmitted through the wireless channel 20 is received through the antenna 31 of the receiver 30 and the receiver 30 undergoes the reverse process of the process occurring at the transmitter 10. That is, the received data can be demodulated by the demodulator 33 and decoded by the LDPC decoder 35 to finally recover the information bits.

It will be apparent to those skilled in the art that the above-described transmission / reception process is described within the minimum range necessary to explain the features of the present invention, and that many other processes necessary for data transmission can be added.

Hereinafter, the concrete procedure of encoding or decoding through the LDPC code in the LDPC encoder 13 or the LDPC decoder 35 and the specific configuration of the encoding or decoding apparatus such as the LDPC encoder 13 or LDPC decoder 35 . The LDPC encoder 13 shown in FIG. 1 may have the structure shown in FIG. 4, and the LDPC decoder 35 may have the structure shown in FIG.

2 is a flowchart illustrating a method of transmitting / receiving a broadcast signal according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a method for transmitting / receiving a broadcast signal according to an exemplary embodiment of the present invention first LDPC-codes input information bits (S210).

That is, in step S210, k bits of information bits are encoded by the LDPC encoder to generate n-bit codewords.

In this case, step S210 may be performed in the same manner as the LDPC coding method shown in FIG.

Also, the broadcasting signal transmitting / receiving method modulates the encoded data (S220).

That is, step S220 modulates the encoded n-bit code word by the modulator.

Also, the broadcasting signal transmitting / receiving method transmits the modulated data (S230).

That is, the step S230 transmits the modulated codeword to the radio channel through the antenna.

In addition, the broadcasting signal transmitting / receiving method demodulates the received data (S240).

That is, the step S240 receives the signal transmitted through the radio channel through the antenna of the receiver and demodulates the received data by the demodulator.

Also, the broadcasting signal transmitting / receiving method performs LDPC decoding on the demodulated data (S250).

That is, in step S250, LDPC decoding is performed through the demodulator of the receiver to finally recover the information bits.

In this case, step S250 corresponds to the inverse process of the LDPC encoding method shown in FIG. 6, and may correspond to the LDPC decoder of FIG.

The LDPC (Low Density Parity Check) code is known as a code close to the Shannon limit in an AWGN (Additive White Gaussian Noise) channel. The LDPC code is asymptotically superior to the turbo code, .

Generally, an LDPC code is defined by a randomly generated low density PCM (Parity Check Matrix). However, a randomly generated LDPC code not only requires a large amount of memory to store the PCM, but also takes a long time to access the memory. In order to solve such a problem, a quasi-cyclic LDPC (QC-LDPC) code has been proposed, and a QC-LDPC code composed of a zero matrix or a CPM (Circulant Permutation Matrix) Lt; RTI ID = 0.0 &gt; PCM. &Lt; / RTI &gt;

[Equation 1]

Here, J is a CPM whose size is L x L and is given by the following equation (2). In the following, L may be 360.

&Quot; (2) &quot;

In addition, J ⁱ is the L x L identity matrix I (= J ⁰ ) shifted to the right i (0 = i L) times, and J ^∞ is the L x L zero matrix. Therefore, in the QC-LDPC code, only the exponent ^{i needs} to be stored in order to store J ⁱ , so that the memory required to store the PCM is greatly reduced.

3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of the matrices A and C are g x K and (N-K-g) x (K + g), respectively. The matrix Z is a zero matrix whose magnitude is gx (NKg), the matrix D is an identity matrix whose magnitude is (NKg) x (NKg), the matrix B is a dual diagonal matrix of size gxg matrix. In this case, the matrix B may be a matrix in which all elements other than the diagonal elements and the elements neighboring the lower diagonal are 0, and may be defined as Equation (3).

&Quot; (3) &quot;

Where I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a general (bit-wise) diagonal diagonal matrix or a block-wise diagonal matrix as shown in Equation (3). A bit-wise double diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438.

Particularly, when the matrix B is a bit-wise diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in FIG. 3 including the matrix B It will be apparent to those skilled in the art that it may be converted to quasi-cyclic.

In this case, N is the length of the codeword, and K is the length of the information.

The present invention proposes a newly designed QC-LDPC code having a code rate of 3/15 and a codeword length of 16200 as shown in Table 1 below. That is, we propose an LDPC code that receives information of length 3240 and generates an LDPC codeword of length 16200.

Table 1 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

[Table 1]

The newly designed LDPC code can be displayed in a sequence, and an equivalent relation between the sequence and the matrix (parity bit check matrix) is established, and the sequence can be expressed as shown in the following table.

[table]

First line: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988

Second line: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267

Third line: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003

Fourth line: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341

5th line: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561

6th line: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990

Line 7: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092

Line 8: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689

Ninth line: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893

10th line: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876

11th line: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810

Line 12: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272

The LDPC codes in the form of a sequence are widely used in the DVB standard.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to an embodiment of the present invention, an LDPC code denoted by a sequence is encoded as follows. Assume an information block S = (s ₀ , s ₁ , ..., s _{K -1} ) with an information size _K. An LDPC encoder uses an information block S having a size K to generate a codeword having a size of N = K + M ₁ + M ₂ ,

. Here, M ₁ = g and M ₂ = NKg. Also, M ₁ is the parity size corresponding to the dual diagonal matrix B, and M ₂ is the parity size corresponding to the identity matrix D. The encoding process is as follows.

- initialization:

&Quot; (4) &quot;

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 16200이며, 부호율이 3/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-first

At the parity bit addresses specified in the first row of the table's sequence. For example, the accumulation process in an LDPC code having a length of 16200 and a code rate of 3/15 is as follows.

)은 GF(2)에서 일어난다.Here, add (

) Occurs in GF (2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.- the next L-1 information bits, i.

Are accumulated at the parity bit addresses calculated in Equation (5) below.

&Quot; (5) &quot;

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 16200이며, 부호율이 3/15인 LDPC 부호는 M₁ = 1080, Q₁ = 3, M₂ = 11880, Q₂ = 33, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.Where x is the first bit

Q ₁ = M ₁ / L, Q ₂ = M ₂ / L, and L = 360, which are the parity bit addresses corresponding to the parity bit addresses corresponding to the parity bits in the table. Q ₁ and Q ₂ are defined in Table 2 below. For example, the LDPC code having a length of 16200 and a coding rate of 3/15 is M ₁ = 1080, Q ₁ = 3, M ₂ = 11880, Q ₂ = 33 and L =

Using Equation (5), the following operation is performed.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ and Q ₂ of the designed QC-LDPC code.

[Table 2]

부터

까지의 새로운 360개의 정보비트들은 상기 수열의 제2행을 이용하여, 상기 수학식 5로부터 패러티 비트 누적기들의 주소를 계산하고, 누적한다.-the next

from

The new 360 information bits up to &lt; RTI ID = 0.0 &gt; Eq. 5 &lt; / RTI &gt; calculate and accumulate the addresses of the parity bit accumulators from Equation 5 using the second row of the sequence.

Similarly, for all groups of new L information bits, the address of the parity bit accumulators from Equation (5) is calculated and accumulated using a new row of the sequences.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

in

All the information bits up to i = 1 are used, and then the operation of Equation (6) is sequentially performed starting from i = 1.

&Quot; (6) &quot;

Next, when parity interleaving is performed as shown in Equation (7), parity generation corresponding to the diagonal diagonal matrix B is completed.

&Quot; (7) &quot;

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

), When parity generation corresponding to the diagonal diagonal matrix B is completed, M ₁ generated parity (

), And generates a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

in

For each group consisting of L bits from the first diagonal matrix B to the new row of the series (starting from the immediately following row of the last row used to generate the parity corresponding to the diagonal diagonal matrix B) To calculate the addresses of the parity bit accumulators, and to perform related calculations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

in

And parity interleaving as shown in Equation (8) below is performed, parity generation corresponding to the identity matrix D is completed.

&Quot; (8) &quot;

4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.

Referring to FIG. 4, an LDPC encoder according to an embodiment of the present invention includes memories 310 and 320 and a processor 330.

The memory 310 is a memory for storing an LDPC codeword having a length of 16200 and a coding rate of 3/15.

The memory 320 is a memory initialized to zero.

Memory 310 and memory 320 are each _{λ i (i = 0, 1} , ..., N-1) and _{P j (j = 0, 1} , ..., M 1 + M 2 -1) Lt; / RTI &gt;

The memory 310 and the memory 320 may correspond to various hardware for storing a set of bits and may include data structures such as an array, a list, a stack, a queue, data structure.

The processor 330 performs accumulation on the memory 320 using a sequence corresponding to a parity check matrix to calculate the LDPC codeword corresponding to the information bits .

At this time, the accumulation may be performed at parity bit addresses that are updated using the sequence of the table.

At this time, the LDPC codeword includes systematic parts (? ₀ ,? ₁ , ...,? _K-1 ) corresponding to the information bits and having a length of 3240 (= K) The first parity part (λ _K , λ _{K + 1} , ..., λ _{K + M1 -1} ) corresponding to the diagonal diagonal matrix and having a length of 1080 (= M ₁ = g) It corresponds to and may include the length of 11880 (= ₂ M) of the second parity part _{(λ K + M1, λ K} + M1 +1, ..., λ K + M1 + M2 -1).

In this case, a value obtained by dividing the length of the systematic part (3240) by the CPM size (L) 360 corresponding to the parity check matrix and dividing the length (M ₁ ) of the first parity part by 1080 by 360 (3240/360 + 1080/360 = 12) rows.

As described above, the sequence may be represented by the table.

At this time, the memory 320 may have a size corresponding to the sum (M ₁ + M ₂ ) of the length (M ₁ ) of the first parity part and the length (M ₂ ) of the second parity part.

At this time, the parity bit addresses may be updated based on the result of comparing each of the previous parity bit addresses (x) shown in each row of the series with the length (M ₁ ) of the first parity part.

That is, the parity bit addresses can be updated by Equation (5). Where m is an integer greater than 0 and less than L, and L is the CPM size of the parity check matrix, Q ₁ is M ₁ / L, and M ₁ is the first parity part Q ₂ may be M ₂ / L, and M ₂ may be the size of the second parity part.

At this time, the accumulation may be performed while changing the rows of the sequence with the CPM size L = 360 units of the parity check matrix as described above.

In this case, the first parity part (? _{K ,? K + 1} , ...,? _{K + M1-1} ) uses the memory 310 and the memory 320, May be generated by performing parity interleaving.

At this time, the second parity part _{(M1 + K} λ, λ _{K + M1 +1,} ..., λ _{K + M1 + M2 -1)} of the first parity part (λ, as described by Equation 8 _K, λ _{K +1,} ..., after the generation of λ _{K + M1-1)} is completed by using the random number sequence and the first parity part (λ _{K, K + 1,} λ, ..., λ _{K + M1-1)} And performing parity interleaving using the memory 310 and the memory 320 after the accumulation to be performed is completed.

5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention.

Referring to FIG. 5, an LDPC decoder according to an embodiment of the present invention includes a receiver 410 and a decoder 420.

The receiving unit 410 receives a Low Density Parity Check (LDPC) codeword, which is encoded using the sequence corresponding to the parity check matrix and represented by the table.

The decoding unit 420 performs decoding corresponding to the parity check matrix and restores information bits in the received LDPC codeword.

At this time, the sequence is used to update parity bit addresses of the memory, and the parity bit addresses can be used for accumulation to generate parity bits corresponding to the LDPC codeword.

In this case, the LDPC codeword includes a systematic part (? ₀ ,? ₁ , ...,? _K-1 ) corresponding to the information bits, a _first part corresponding to the double diagonal matrix included in the parity check matrix parity part _(K λ, λ _{K + 1,} ..., λ _{M1 + K -1)} and a second parity part _{(M1 + K} λ, λ _{K + M1 +1} corresponding to the identity matrix included in the parity check matrix. .., _{K + M1 + M2 - 1} ).

At this time, the parity bit addresses may be updated based on the result of comparing each of the previous parity bit addresses (x) shown in each row of the series with the length (M ₁ ) of the first parity part.

That is, the parity bit addresses can be updated by Equation (5). Where m is an integer greater than 0 and less than L, and L is the CPM size of the parity check matrix, Q ₁ is M ₁ / L, and M ₁ is the first parity part Q ₂ may be M ₂ / L, and M ₂ may be the size of the second parity part.

6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.

Referring to FIG. 6, an LDPC encoding method according to an embodiment of the present invention initializes a first memory and a second memory for storing an LDPC codeword (S510).

In this case, step S510 may be performed according to Equation (4).

Also, an LDPC encoding method according to an embodiment of the present invention performs accumulation on the second memory using a sequence corresponding to a parity check matrix, And generates the LDPC codeword corresponding to the LDPC codeword (S520).

At this time, the accumulation may be performed at parity bit addresses updated using a sequence corresponding to a parity check matrix.

At this time, the LDPC codeword includes systematic parts (? ₀ ,? ₁ , ...,? _K-1 ) corresponding to the information bits and having a length of 3240 (= K) The first parity part (λ _K , λ _{K + 1} , ..., λ _{K + M1 -1} ) corresponding to the diagonal diagonal matrix and having a length of 1080 (= M ₁ = g) It corresponds to and may include the length of 11880 (= ₂ M) of the second parity part _{(λ K + M1, λ K} + M1 +1, ..., λ K + M1 + M2 -1).

In this case, a value obtained by dividing the length of the systematic part (3240) by the CPM size (L) 360 corresponding to the parity check matrix and dividing the length (M ₁ ) of the first parity part by 1080 by 360 (3240/360 + 1080/360 = 12) rows.

As described above, the sequence may be represented by the table.

At this time, the parity bit addresses may be updated based on the result of comparing each of the previous parity bit addresses (x) shown in each row of the series with the length (M ₁ ) of the first parity part.

That is, the parity bit addresses can be updated by Equation (5). Where m is an integer greater than 0 and less than L, and L is the CPM size of the parity check matrix, Q ₁ is M ₁ / L, and M ₁ is the first parity part Q ₂ may be M ₂ / L, and M ₂ may be the size of the second parity part.

At this time, the accumulation may be performed while changing the rows of the sequence with the CPM size L = 360 units of the parity check matrix as described above.

In this case, the first parity part (? _{K ,? K + 1} , ...,? _{K + M1-1} ) has parity interleaving using the first memory and the second memory, (parity interleaving).

At this time, the second parity part _{(M1 + K} λ, λ _{K + M1 +1,} ..., λ _{K + M1 + M2 -1)} of the first parity part (λ, as described by Equation 8 _K, λ _{K +1,} ..., after the generation of λ _{K + M1-1)} is completed by using the random number sequence and the first parity part (λ _{K, K + 1,} λ, ..., λ _{K + M1-1)} And performing parity interleaving using the first memory 310 and the second memory 320 after the accumulation performed is completed.

FIG. 7 is a graph illustrating the performance of a QC-LDPC code having a length of 16200 and a coding rate of 3/15 according to an exemplary embodiment of the present invention in comparison with E _b / N _o .

The graph shown in FIG. 7 is a result of assuming a log-likelihood ratio (LLR) -based sum-product algorithm for BPSK (Binary Phase Shift Keying) modulation and 50 iterative decoding for computational experiments. As shown in FIG. 7, the designed code is found to be about 1.25 dB away from the Shannon limit at BER = 10 ^-6 .

As described above, the LDPC encoder, the decoder, and the LDPC encoding method according to the present invention are not limited to the configuration and method of the embodiments described above, but the embodiments may be modified in various ways, All or some of the embodiments may be selectively combined.

310, 320: memory
330: Processor

Claims (6)

A first memory for storing an LDPC codeword having a length of 16200 and a coding rate of 3/15;
A second memory initialized to zero; And
A processor for performing accumulation on the second memory using a sequence corresponding to a parity check matrix and generating the LDPC codeword corresponding to information bits,
And an LDPC encoder for decoding the LDPC code. The method according to claim 1,
The LDPC codeword
A systematic part having a length of 3240 corresponding to the information bits, a first parity part corresponding to a double diagonal matrix included in the parity check matrix, a first parity part having a length of 1080, and an identity matrix included in the parity check matrix. And a second parity part having a length of 11880 corresponding to the first parity part. The method of claim 2,
The number of rows divided by the value obtained by dividing the length of the systematic part 3240 by the CPM size corresponding to the parity check matrix 360 and the value obtained by dividing the length of the first parity part 1080 by the CPM size and an LDPC encoder. The method of claim 3,
Wherein the sequence is represented by the following table.
[table]
First line: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988
Second line: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267
Third line: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003
Fourth line: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341
5th line: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561
6th line: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990
Line 7: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092
Line 8: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689
Ninth line: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893
10th line: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876
11th line: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810
Line 12: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272 The method of claim 4,
The accumulation,
Wherein the parity bits are performed at parity bit addresses updated using the sequence. The method of claim 5,
The accumulation
Wherein the parity check matrix is performed while changing rows of the sequence in units of CPM size (L) of the parity check matrix.

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