KR102506686B1 - Low density parity check decoder with 64800 length and 2/15 rate, and method using the same - Google Patents

Abstract

An LDPC encoder, a decoder, and an LDPC encoding method are disclosed. An LDPC encoder according to an embodiment of the present invention includes a first memory for storing an LDPC codeword having a length of 64800 and a code rate of 2/15; a second memory initialized to 0; and a processor generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

Description

LDPC decoder with length of 64800 and code rate of 2/15 and LDPC decoding method using the same {LOW DENSITY PARITY CHECK DECODER WITH 64800 LENGTH AND 2/15 RATE, AND METHOD USING THE SAME}

The present invention relates to a Low Density Parity Check (LDPC) code for correcting an error occurring in a radio channel, and more particularly to an LDPC code applicable to a digital broadcasting system.

Since current terrestrial TV broadcasting generates co-channel interference corresponding to three times the service change, the same frequency cannot be reused in an area within three times the service radius. As such, an area in which the same frequency cannot be reused is called a white space, and spectral efficiency is very low due to the occurrence of the white space.

Therefore, there is a need to develop a transmission technology that can easily remove white space and reuse frequencies with an emphasis on reception robustness in order to improve spectral efficiency.

Accordingly, in September 2012, IEEE Transactions on Broadcasting, vol. In the academic literature "Cloud Transmission: A New Spectrum-Reuse Friendly Digital Terrestrial Broadcasting Transmission System" published through 58, no.3, a terrestrial cloud that is easy to reuse, does not generate white space, and is easy to build and operate a single frequency network Broadcast technology is proposed.

Using such a terrestrial cloud broadcasting technology, a broadcaster can transmit the same broadcasting content nationwide or different broadcasting contents for each region through one broadcasting channel. However, for this, the receiver must be able to receive one or more terrestrial cloud broadcasting signals in an area where signals transmitted from different transmitters overlap on a single frequency network, that is, in an overlapping area, and can distinguish and demodulate the received terrestrial cloud broadcasting signal. There should be. That is, a receiver must be able to demodulate one or more cloud broadcasting signals in a situation where co-channel interference exists and timing and frequency synchronization of each transmission signal are not guaranteed.

Meanwhile, Korean Patent Publication No. 2013-0135746 "LDPC code for terrestrial cloud broadcasting" discloses an LDPC code that is optimized for terrestrial cloud broadcasting and shows excellent performance at a low code rate (<0.5).

However, Korean Patent Publication No. 2013-0135746 relates to a code length completely different from the LDPC code length used in the DVB broadcasting standard, etc., and is silent about a specific LDPC code method.

An object of the present invention is to provide a new LDPC codeword with a codeword length of 64800 and a code rate of 2/15 that can be used universally.

In addition, an object of the present invention is to efficiently perform LDPC encoding using a sequence having rows corresponding to the value obtained by dividing the sum of 8640, the length of the systematic part of the LDPC codeword, and 1800, the length of the first parity part, by 360. It is to provide an LDPC encoding technique capable of performing

An LDPC encoder according to the present invention for achieving the above object includes a first memory for storing an LDPC codeword having a length of 64800 and a code rate of 2/15; a second memory initialized to 0; and a processor generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

In this case, accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

At this time, the LDPC codeword is a systematic part corresponding to the information bits and having a length of 8640, a first parity part corresponding to the double diagonal matrix included in the parity check matrix and having a length of 1800, and the parity check matrix A second parity part corresponding to the identity matrix included in and having a length of 54360 may be included.

At this time, the sequence is the number obtained by dividing 8640, the length of the systematic part, by 360, the CPM size corresponding to the parity check matrix, and adding the value obtained by dividing 1800, the length of the first parity part, by the CPM size. You can have rows.

At this time, the sequence can be expressed as the following table.

[table]

Line 1: 615 898 1029 6129 8908 10620 13378 14359 21964 23319 26427 26690 28128 33435 36080 40697 43525 44498 50994

Line 2: 165 1081 1637 2913 8944 9639 11391 17341 22000 23580 32309 38495 41239 44079 47395 47460 48282 51744 52782

Line 3: 426 1340 1493 2261 10903 13336 14755 15244 20543 29822 35283 38846 45368 46642 46934 48242 49000 49204 53370

Line 4: 407 1059 1366 2004 5985 9217 9321 13576 19659 20808 30009 31094 32445 39094 39357 40651 44358 48755 49732

Line 5: 692 950 1444 2967 3929 6951 10157 10326 11547 13562 19634 34484 38236 42918 44685 46172 49694 50535 55109

Line 6: 1087 1458 1574 2335 3248 6965 17856 23454 25182 37359 37718 37768 38061 38728 39437 40710 46298 50707 51572

Line 7: 1098 1540 1711 7723 9549 9986 16369 19567 21185 21319 25750 32222 32463 40342 41391 43869 48372 52149 54722

Line 8: 514 1283 1635 6602 11333 11443 17690 21036 22936 24525 25425 27103 28733 29551 39204 42525 49200 54899 54961

Line 9: 357 609 1096 2954 4240 5397 8425 13974 15252 20167 20362 21623 27190 42744 47819 49096 51995 55504 55719

Line 10: 25 448 1501 11572 13478 24338 29198 29840 31428 33088 34724 37698 37988 38297 40482 46953 47880 53751 54943

Line 11: 328 1096 1262 10802 12797 16053 18038 20433 20444 25422 32992 34344 38326 41435 46802 48766 49807 52966 55751

Line 12: 34 790 987 5082 5788 10778 12824 18217 23278 24737 28312 34464 36765 37999 39603 40797 43237 53089 55319

Line 13: 226 1149 1470 3483 8949 9312 9773 13271 17804 20025 20323 30623 38575 39887 40305 46986 47223 49998 52111

Line 14: 1088 1091 1757 2682 5526 5716 9665 10733 12997 14440 24665 27990 30203 33173 37423 38934 40494 45418 48393

Line 15: 809 1278 1580 3486 4529 6117 6212 6823 7861 9244 11559 20736 30333 32450 35528 42968 44485 47149 54913

Line 16: 369 525 1622 2261 6454 10483 11259 16461 17031 20221 22710 25137 26622 27904 30884 31858 44121 50690 56000

Line 17: 423 1291 1352 7883 26107 26157 26876 27071 31515 35340 35953 36608 37795 37842 38527 41720 46206 47998 53019

Line 18: 540 662 1433 2828 14410 22880 24263 24802 28242 28396 35928 37214 39748 43915 44905 46590 48684 48890 55926

Line 19: 214 1291 1622 7311 8985 20952 22752 23261 24896 25057 28826 37074 37707 38742 46026 51116 51521 52956 54213

Line 20: 109 1305 1676 2594 7447 8943 14806 16462 19730 23430 24542 34300 36432 37133 41199 43942 45860 47598 48401 49407

Line 21: 242 388 1360 6721 14220 21029 22536 25126 32251 33182 39192 42436 44144 45252 46238 47369 47607 47695 50635 51469

Line 22: 199 958 1111 13661 18809 19234 21459 25221 25837 28256 36919 39031 39107 39262 43572 45018 45959 48006 52387 55811

Line 23: 668 1087 1451 2945 3319 12519 21248 21344 22627 22701 28152 29670 31430 32655 38533 42233 43200 44013 44459 51398

Line 24: 244 1133 1665 8222 8740 11285 12774 15922 20147 20978 28927 35086 40197 40583 41066 41223 42104 44650 45391 48437

Line 25: 5623 8050 9679 12978 15846 16049 21807 23364 27226 27758 28661 38147 46337 48141 51364 51927 55124

Line 26: 10369 13704 14491 18632 19430 21218 33392 36182 36722 37342 37415 46322 47449 51136 53392 54356 55108

Line 27: 7460 9411 11132 11739 13722 15501 25588 26463 26738 31980 31981 35002 39659 39783 41581 51358 55114

Line 28: 8915 15253 15264 16513 16896 18367 19110 23492 32074 33302 42443 43797 44715 47538 48515 53464 53548

Line 29: 5884 8910 10123 11311 13654 14207 16122 18113 23100 23784 24825 39629 46372 52454 52799 55039 55973

At this time, accumulation may be performed while changing rows of the sequence in units of CPM size (L) of the parity check matrix.

Also, an LDPC encoding method according to an embodiment of the present invention includes initializing a first memory and a second memory for storing LDPC codewords; and performing accumulation on the second memory using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to information bits. do.

In this case, the accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

At this time, the LDPC codeword is a systematic part having a length of 8640 corresponding to the information bits, a first parity part having a length of 1800 and corresponding to a double diagonal matrix included in the parity check matrix, and the parity check matrix A second parity part corresponding to the identity matrix included in and having a length of 54360 may be included.

At this time, the sequence is the number obtained by dividing 8640, the length of the systematic part, by 360, the CPM size corresponding to the parity check matrix, and adding the value obtained by dividing 1800, the length of the first parity part, by the CPM size. You can have rows.

In this case, the sequence may be expressed as the table.

In addition, the LDPC decoder according to an embodiment of the present invention includes a receiving unit that receives a Low Density Parity Check (LDPC) codeword that corresponds to a parity check matrix and is encoded using a sequence represented by the table; and a decoding unit that restores information bits from the received LDPC codeword by performing decoding corresponding to the parity check matrix.

According to the present invention, a new LDPC codeword having a universally usable codeword length of 64800 and a code rate of 2/15 is provided.

In addition, the present invention efficiently performs LDPC encoding using a sequence having rows corresponding to the value obtained by dividing the sum of 8640, the length of the systematic part of the LDPC codeword, and 1800, the length of the first parity part, by 360 can do.

1 is a block diagram showing a system for transmitting/receiving broadcast signals according to an embodiment of the present invention.
2 is an operational flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.
3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.
5 is a block diagram showing an LDPC decoder according to an embodiment of the present invention.
6 is an operational flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.
7 is a graph showing the performance of a QC-LDPC code having a length of 64800 and a code rate of 2/15 in comparison with E _b /N _o according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings. Here, repeated descriptions, well-known functions that may unnecessarily obscure the subject matter of the present invention, and detailed descriptions of configurations are omitted. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clarity.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a system for transmitting/receiving broadcast signals according to an embodiment of the present invention.

Referring to FIG. 1 , it can be seen that a transmitter 10 and a receiver 30 communicate through a radio channel 20 .

The transmitter 10 encodes k-bit information bits 11 in the LDPC encoder 13 to generate an n-bit codeword. The codeword is modulated by modulator 15 and transmitted via antenna 17. The signal transmitted through the radio channel 20 is received through the antenna 31 of the receiver 30, and the receiver 30 undergoes the reverse process of the process that occurred in the transmitter 10. That is, the received data is demodulated by the demodulator 33 and decoded by the LDPC decoder 35 to finally restore information bits.

The transmission/reception process as described above has been described within the minimum range required to explain the characteristics of the present invention, and it is obvious to those skilled in the art that many processes necessary for data transmission may be added in addition to those described.

Hereinafter, a specific process of encoding or decoding through the LDPC code in the LDPC encoder 13 or the LDPC decoder 35 and the specific configuration of an encoding or decoding device such as the LDPC encoder 13 or the LDPC decoder 35 explain about The LDPC encoder 13 shown in FIG. 1 may have the structure shown in FIG. 4, and the LDPC decoder 35 may have the structure shown in FIG.

2 is an operational flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.

Referring to FIG. 2 , in the broadcast signal transmission/reception method according to an embodiment of the present invention, first, input bits (information bits) are LDPC-encoded (S210).

That is, in step S210, an n-bit codeword is generated by encoding k-bit information bits in the LDPC encoder.

At this time, step S210 may be performed in the same way as the LDPC encoding method shown in FIG. 6 .

In addition, the broadcast signal transmission/reception method modulates coded data (S220).

That is, in step S220, the encoded n-bit codeword is modulated by a modulator.

In addition, the broadcast signal transmission/reception method transmits modulated data (S230).

That is, in step S230, the modulated codeword is transmitted through an antenna through a radio channel.

In addition, the broadcast signal transmission/reception method demodulates received data (S240).

That is, in step S240, a signal transmitted through a radio channel is received through an antenna of the receiver, and the received data is demodulated by a demodulator.

In addition, in the broadcast signal transmission/reception method, demodulated data is LDPC-decoded (S250).

That is, in step S250, LDPC decoding is performed through the demodulator of the receiver to finally restore information bits.

At this time, step S250 corresponds to the reverse process of the LDPC encoding method shown in FIG. 6 and may correspond to the LDPC decoder of FIG. 5 .

LDPC (Low Density Parity Check) codes are known as codes that approach the Shannon limit in an Additive White Gaussian Noise (AWGN) channel, and have asymptotically superior performance to turbo codes, parallelizable decoding, etc. has the advantage of

In general, an LDPC code is defined by a randomly generated low-density Parity Check Matrix (PCM). However, randomly generated LDPC codes not only require a lot of memory to store the PCM, but also take a lot of time to access the memory. To solve this problem, a quasi-cyclic LDPC (QC-LDPC) code has been proposed, and the QC-LDPC code composed of a zero matrix or a Circulant Permutation Matrix (CPM) is It is defined by PCM represented by 1.

[Equation 1]

Here, J is a CPM of size L x L and is given by Equation 2 below. Hereinafter, L may be 360.

[Equation 2]

In addition, J ⁱ is an L x L identity matrix I(=J ⁰ ) shifted to the right i (0=i<L) times, and J ^∞ is an L x L zero matrix. Therefore, in the QC-LDPC code, since only the exponent i needs to be stored to store J ⁱ , the memory required for storing the PCM is greatly reduced.

3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are g x K and (N-K-g) x (K+g), respectively, and are composed of a zero matrix of L x L size and CPM. In addition, matrix z is a zero matrix of size g x (N-K-g), matrix D is an identity matrix of size (N-K-g) x (N-K-g), and matrix B is a dual diagonal matrix of size g x g. matrix). In this case, the matrix B may be a matrix in which all elements other than the elements on the diagonal and the elements adjacent to the bottom of the diagonal are all 0, or may be defined as in Equation 3 below.

[Equation 3]

Here, I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a general (bit-wise) double-diagonal matrix, or a block-wise double-diagonal matrix having an identity matrix as a block as indicated in Equation 3 above. A bit-wise double-diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438 and the like.

In particular, when matrix B is a general (bit-wise) double-diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in FIG. It is obvious to those skilled in the art that it can be converted to quasi-cyclic.

At this time, N is the length of a codeword, and K represents the length of information.

In the present invention, as shown in Table 1 below, a newly designed QC-LDPC code with a code rate of 2/15 and a codeword length of 64800 is proposed. That is, an LDPC code generating an LDPC codeword having a length of 64800 by receiving information having a length of 8640 is proposed.

Table 1 shows the size of A, B, C, D, Z matrices of the QC-LDPC code of the present invention.

[Table 1]

A newly designed LDPC code can be displayed in the form of a sequence, an equivalent relationship is established between a sequence and a matrix (a parity bit check matrix), and the sequence can be expressed as shown in the following table.

[table]

Line 1: 615 898 1029 6129 8908 10620 13378 14359 21964 23319 26427 26690 28128 33435 36080 40697 43525 44498 50994

Line 2: 165 1081 1637 2913 8944 9639 11391 17341 22000 23580 32309 38495 41239 44079 47395 47460 48282 51744 52782

Line 3: 426 1340 1493 2261 10903 13336 14755 15244 20543 29822 35283 38846 45368 46642 46934 48242 49000 49204 53370

Line 4: 407 1059 1366 2004 5985 9217 9321 13576 19659 20808 30009 31094 32445 39094 39357 40651 44358 48755 49732

Line 5: 692 950 1444 2967 3929 6951 10157 10326 11547 13562 19634 34484 38236 42918 44685 46172 49694 50535 55109

Line 6: 1087 1458 1574 2335 3248 6965 17856 23454 25182 37359 37718 37768 38061 38728 39437 40710 46298 50707 51572

Line 7: 1098 1540 1711 7723 9549 9986 16369 19567 21185 21319 25750 32222 32463 40342 41391 43869 48372 52149 54722

Line 8: 514 1283 1635 6602 11333 11443 17690 21036 22936 24525 25425 27103 28733 29551 39204 42525 49200 54899 54961

Line 9: 357 609 1096 2954 4240 5397 8425 13974 15252 20167 20362 21623 27190 42744 47819 49096 51995 55504 55719

Line 10: 25 448 1501 11572 13478 24338 29198 29840 31428 33088 34724 37698 37988 38297 40482 46953 47880 53751 54943

Line 11: 328 1096 1262 10802 12797 16053 18038 20433 20444 25422 32992 34344 38326 41435 46802 48766 49807 52966 55751

Line 12: 34 790 987 5082 5788 10778 12824 18217 23278 24737 28312 34464 36765 37999 39603 40797 43237 53089 55319

Line 13: 226 1149 1470 3483 8949 9312 9773 13271 17804 20025 20323 30623 38575 39887 40305 46986 47223 49998 52111

Line 14: 1088 1091 1757 2682 5526 5716 9665 10733 12997 14440 24665 27990 30203 33173 37423 38934 40494 45418 48393

Line 15: 809 1278 1580 3486 4529 6117 6212 6823 7861 9244 11559 20736 30333 32450 35528 42968 44485 47149 54913

Line 16: 369 525 1622 2261 6454 10483 11259 16461 17031 20221 22710 25137 26622 27904 30884 31858 44121 50690 56000

Line 17: 423 1291 1352 7883 26107 26157 26876 27071 31515 35340 35953 36608 37795 37842 38527 41720 46206 47998 53019

Line 18: 540 662 1433 2828 14410 22880 24263 24802 28242 28396 35928 37214 39748 43915 44905 46590 48684 48890 55926

Line 19: 214 1291 1622 7311 8985 20952 22752 23261 24896 25057 28826 37074 37707 38742 46026 51116 51521 52956 54213

Line 20: 109 1305 1676 2594 7447 8943 14806 16462 19730 23430 24542 34300 36432 37133 41199 43942 45860 47598 48401 49407

Line 21: 242 388 1360 6721 14220 21029 22536 25126 32251 33182 39192 42436 44144 45252 46238 47369 47607 47695 50635 51469

Line 22: 199 958 1111 13661 18809 19234 21459 25221 25837 28256 36919 39031 39107 39262 43572 45018 45959 48006 52387 55811

Line 23: 668 1087 1451 2945 3319 12519 21248 21344 22627 22701 28152 29670 31430 32655 38533 42233 43200 44013 44459 51398

Line 24: 244 1133 1665 8222 8740 11285 12774 15922 20147 20978 28927 35086 40197 40583 41066 41223 42104 44650 45391 48437

Line 25: 5623 8050 9679 12978 15846 16049 21807 23364 27226 27758 28661 38147 46337 48141 51364 51927 55124

Line 26: 10369 13704 14491 18632 19430 21218 33392 36182 36722 37342 37415 46322 47449 51136 53392 54356 55108

Line 27: 7460 9411 11132 11739 13722 15501 25588 26463 26738 31980 31981 35002 39659 39783 41581 51358 55114

Line 28: 8915 15253 15264 16513 16896 18367 19110 23492 32074 33302 42443 43797 44715 47538 48515 53464 53548

Line 29: 5884 8910 10123 11311 13654 14207 16122 18113 23100 23784 24825 39629 46372 52454 52799 55039 55973

The LDPC code expressed in the form of a sequence is widely used in the DVB standard.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to one embodiment of the present invention, the LDPC code expressed in the form of a sequence is encoded as follows. Assume an information block S=(s ₀ , s ₁ , ..., s _K-1 ) with an information size K. The LDPC encoder uses an information block S of size K to generate a codeword of size N=K+M ₁ +M ₂

generate Here, M ₁ =g, M ₂ =NKg. In addition, M ₁ is the size of parity corresponding to the dual diagonal matrix B, and M ₂ is the size of parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Equation 4]

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 64800이며, 부호율이 2/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-first

Accumulate at the parity bit addresses specified in the first row of the sequence of the table. For example, an accumulation process in an LDPC code having a length of 64800 and a code rate of 2/15 is as follows.

)은 GF(2)에서 일어난다.Add here (

) occurs in GF(2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.-the next L-1 information bits, i.e.

For , the parity bit addresses calculated in Equation 5 below are accumulated.

[Equation 5]

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 64800이며, 부호율이 2/15인 LDPC 부호는 M₁ = 1800, Q₁ = 5, M₂ = 54360, Q₂ = 151, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.where x is the first bit

Indicates parity bit addresses corresponding to , that is, parity bit addresses indicated in the first row of the sequence of the table, Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, L = 360. In addition, Q ₁ and Q ₂ are defined in Table 2 below. For example, an LDPC code with a length of 64800 and a code rate of 2/15 has M ₁ = 1800, Q ₁ = 5, M ₂ = 54360, Q ₂ = 151, L = 360, so the second bit

For Equation 5, the following calculation is performed.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

[Table 2]

부터

까지의 새로운 360개의 정보비트들은 상기 수열의 제2행을 이용하여, 상기 수학식 5로부터 패러티 비트 누적기들의 주소를 계산하고, 누적한다.-the next

from

For the new 360 information bits up to , the addresses of the parity bit accumulators are calculated and accumulated from Equation 5 using the second row of the sequence.

-Similarly, for all groups composed of L new information bits, addresses of parity bit accumulators are calculated and accumulated from Equation 5 using a new row of the sequence.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

at

After all information bits up to are used, operations of Equation 6 below are sequentially performed, starting from i = 1.

[Equation 6]

-Next, if parity interleaving is performed as shown in Equation 7 below, parity generation corresponding to the double diagonal matrix B is completed.

[Equation 7]

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

), when parity generation corresponding to the double diagonal matrix B is completed, M ₁ generated parity (

) is used to generate a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

at

For all groups consisting of up to L bits, a new row of the sequences (starting from the row immediately following the last row used when generating the parity corresponding to the double diagonal matrix B) and Equation 5 Calculate the addresses of the parity bit accumulators using , and perform related operations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

at

After all bits up to are used, if parity interleaving is performed as shown in Equation 8 below, parity generation corresponding to the identity matrix D is completed.

[Equation 8]

4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.

Referring to FIG. 4 , the LDPC encoder according to an embodiment of the present invention includes memories 310 and 320 and a processor 330 .

The memory 310 is a memory for storing an LDPC codeword having a length of 64800 and a code rate of 2/15.

The memory 320 is a memory that is initialized to zero.

The memory 310 and the memory 320 are respectively λ _i (i=0, 1, ..., N-1) and P _j (j=0, 1, ..., M ₁ +M ₂ -1) may correspond to

The memory 310 and the memory 320 may correspond to various hardware for storing a set of bits, and data structures such as an array, a list, a stack, and a queue ( data structure).

The processor 330 performs accumulation on the memory 320 using a sequence corresponding to a parity check matrix, and obtains the LDPC codeword corresponding to information bits. create

In this case, accumulation may be performed on parity bit addresses that are updated using the sequence of the table.

At this time, the LDPC codeword is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits and having a length of 8640 (=K), included in the parity check matrix The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 1800 (=M ₁ =g) and the identity included in the parity check matrix It may include a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) corresponding to the matrix and having a length of 54360 (=M ₂ ).

At this time, the sequence is a value obtained by dividing 8640, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 1800, which is the length (M ₁ ) of the first parity part, by 360. It can have as many rows as the added number (8640/360+1800/360=29).

As described above, a sequence can be represented by the table above.

In this case, the memory 320 may have a size corresponding to the sum (M ₁ +M ₂ ) of the lengths of the first parity part (M ₁ ) and the lengths of the second parity part (M ₂ ).

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) indicated in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses can be updated by Equation 5 above. At this time, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

At this time, as described above, the accumulation may be performed while changing rows of the sequence in units of CPM size L = 360 of the parity check matrix.

At this time, the first parity part (λ _K , λ _{K + 1} , ..., λ _{K + M1-1} ), as described through Equation 7, uses the memory 310 and the memory 320, It may be generated by performing parity interleaving.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ), the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence It may be generated by performing parity interleaving using the memory 310 and the memory 320 after the accumulation performed using .

5 is a block diagram showing an LDPC decoder according to an embodiment of the present invention.

Referring to FIG. 5 , the LDPC decoder according to an embodiment of the present invention includes a receiver 410 and a decoder 420.

The receiving unit 410 receives a Low Density Parity Check (LDPC) codeword that is encoded using a sequence corresponding to the parity check matrix and represented by the table.

The decoder 420 restores information bits from the received LDPC codeword by performing decoding corresponding to the parity check matrix.

In this case, the sequence is used to update parity bit addresses of the memory, and the parity bit addresses may be used for accumulation to generate parity bits corresponding to the LDPC codeword.

At this time, the LDPC codeword is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits, a first corresponding to a double diagonal matrix included in the parity check matrix The parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the second parity part (λ _K+M1 , λ _K+M1+ corresponding to the identity matrix included in the parity check matrix) ₁ , ..., λ _K+M1+M2-1 ).

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) indicated in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses can be updated by Equation 5 above. At this time, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

6 is an operational flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.

Referring to FIG. 6 , in the LDPC encoding method according to an embodiment of the present invention, a first memory and a second memory for storing LDPC codewords are initialized (S510).

At this time, step S510 may be performed by Equation 4 above.

In addition, the LDPC encoding method according to an embodiment of the present invention performs accumulation on the second memory using a sequence corresponding to a parity check matrix, and information bits The LDPC codeword corresponding to is generated (S520).

In this case, the accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

At this time, the LDPC codeword is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits and having a length of 8640 (=K), included in the parity check matrix The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 1800 (=M ₁ =g) and the identity included in the parity check matrix It may include a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) corresponding to the matrix and having a length of 54360 (=M ₂ ).

At this time, the sequence is a value obtained by dividing 8640, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 1800, which is the length (M ₁ ) of the first parity part, by 360. It can have as many rows as the added number (8640/360+1800/360=29).

As described above, a sequence can be represented by the table above.

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) indicated in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses can be updated by Equation 5 above. At this time, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

At this time, as described above, the accumulation may be performed while changing rows of the sequence in units of CPM size L = 360 of the parity check matrix.

In this case, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) performs parity interleaving using the first memory and the second memory, as described through Equation 7 above. It can be created by performing parity interleaving.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ), the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence It may be generated by performing parity interleaving using the first memory 310 and the second memory 320 after the accumulation performed using .

7 is a graph showing the performance of a QC-LDPC code having a length of 64800 and a code rate of 2/15 in comparison with E _b /N _o according to an embodiment of the present invention.

The graph shown in FIG. 7 is a result of assuming a log-likelihood ratio (LLR)-based sum-product algorithm that performs BPSK (Binary Phase Shift Keying) modulation and 50 iterative decoding for computational experiments. As shown in Fig. 7, it can be seen that the designed code is about 0.7 dB away from the Shannon limit at BER=10 ^-6 .

As described above, the LDPC encoder, decoder, and LDPC encoding method according to the present invention are not limited to the configuration and method of the embodiments described above, but the embodiments are All or part of the embodiments may be configured by selectively combining them.

310, 320: memory
330: processor

Claims (9)

delete A receiving unit for receiving a signal corresponding to a low density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15, encoded using a sequence corresponding to a parity check matrix; and
A decoding unit that performs decoding corresponding to the parity check matrix on the received signal;
LDPC decoder, characterized in that the sequence is represented by the following table.
[table]
Line 1: 615 898 1029 6129 8908 10620 13378 14359 21964 23319 26427 26690 28128 33435 36080 40697 43525 44498 50994
Line 2: 165 1081 1637 2913 8944 9639 11391 17341 22000 23580 32309 38495 41239 44079 47395 47460 48282 51744 52782
Line 3: 426 1340 1493 2261 10903 13336 14755 15244 20543 29822 35283 38846 45368 46642 46934 48242 49000 49204 53370
Line 4: 407 1059 1366 2004 5985 9217 9321 13576 19659 20808 30009 31094 32445 39094 39357 40651 44358 48755 49732
Line 5: 692 950 1444 2967 3929 6951 10157 10326 11547 13562 19634 34484 38236 42918 44685 46172 49694 50535 55109
Line 6: 1087 1458 1574 2335 3248 6965 17856 23454 25182 37359 37718 37768 38061 38728 39437 40710 46298 50707 51572
Line 7: 1098 1540 1711 7723 9549 9986 16369 19567 21185 21319 25750 32222 32463 40342 41391 43869 48372 52149 54722
Line 8: 514 1283 1635 6602 11333 11443 17690 21036 22936 24525 25425 27103 28733 29551 39204 42525 49200 54899 54961
Line 9: 357 609 1096 2954 4240 5397 8425 13974 15252 20167 20362 21623 27190 42744 47819 49096 51995 55504 55719
Line 10: 25 448 1501 11572 13478 24338 29198 29840 31428 33088 34724 37698 37988 38297 40482 46953 47880 53751 54943
Line 11: 328 1096 1262 10802 12797 16053 18038 20433 20444 25422 32992 34344 38326 41435 46802 48766 49807 52966 55751
Line 12: 34 790 987 5082 5788 10778 12824 18217 23278 24737 28312 34464 36765 37999 39603 40797 43237 53089 55319
Line 13: 226 1149 1470 3483 8949 9312 9773 13271 17804 20025 20323 30623 38575 39887 40305 46986 47223 49998 52111
Line 14: 1088 1091 1757 2682 5526 5716 9665 10733 12997 14440 24665 27990 30203 33173 37423 38934 40494 45418 48393
Line 15: 809 1278 1580 3486 4529 6117 6212 6823 7861 9244 11559 20736 30333 32450 35528 42968 44485 47149 54913
Line 16: 369 525 1622 2261 6454 10483 11259 16461 17031 20221 22710 25137 26622 27904 30884 31858 44121 50690 56000
Line 17: 423 1291 1352 7883 26107 26157 26876 27071 31515 35340 35953 36608 37795 37842 38527 41720 46206 47998 53019
Line 18: 540 662 1433 2828 14410 22880 24263 24802 28242 28396 35928 37214 39748 43915 44905 46590 48684 48890 55926
Line 19: 214 1291 1622 7311 8985 20952 22752 23261 24896 25057 28826 37074 37707 38742 46026 51116 51521 52956 54213
Line 20: 109 1305 1676 2594 7447 8943 14806 16462 19730 23430 24542 34300 36432 37133 41199 43942 45860 47598 48401 49407
Line 21: 242 388 1360 6721 14220 21029 22536 25126 32251 33182 39192 42436 44144 45252 46238 47369 47607 47695 50635 51469
Line 22: 199 958 1111 13661 18809 19234 21459 25221 25837 28256 36919 39031 39107 39262 43572 45018 45959 48006 52387 55811
Line 23: 668 1087 1451 2945 3319 12519 21248 21344 22627 22701 28152 29670 31430 32655 38533 42233 43200 44013 44459 51398
Line 24: 244 1133 1665 8222 8740 11285 12774 15922 20147 20978 28927 35086 40197 40583 41066 41223 42104 44650 45391 48437
Line 25: 5623 8050 9679 12978 15846 16049 21807 23364 27226 27758 28661 38147 46337 48141 51364 51927 55124
Line 26: 10369 13704 14491 18632 19430 21218 33392 36182 36722 37342 37415 46322 47449 51136 53392 54356 55108
Line 27: 7460 9411 11132 11739 13722 15501 25588 26463 26738 31980 31981 35002 39659 39783 41581 51358 55114
Line 28: 8915 15253 15264 16513 16896 18367 19110 23492 32074 33302 42443 43797 44715 47538 48515 53464 53548
Line 29: 5884 8910 10123 11311 13654 14207 16122 18113 23100 23784 24825 39629 46372 52454 52799 55039 55973 The method of claim 2,
The LDPC codeword is
It is generated based on accumulation performed using the sequence,
The accumulation is the second bit of information bits corresponding to the LDPC codeword

As for

(p _x (0≤x≤56159) is the memory used for the accumulation,

is the addition operator)
An LDPC decoder characterized in that it is performed using 19 equations of The method of claim 3,
The LDPC codeword is
A systematic part corresponding to information bits and having a length of 8640, a first parity part corresponding to a double diagonal matrix included in the parity check matrix and having a length of 1800, and corresponding to an identity matrix included in the parity check matrix and a second parity part having a length of 54360. The method of claim 4,
The sequence is obtained by dividing 8640, the length of the systematic part, by 360, the Circulant Permutation Matrix (CPM) size corresponding to the parity check matrix, and adding a value obtained by dividing 1800, the length of the first parity part, by the CPM size. An LDPC decoder characterized in that it has as many rows as the number of rows. The method of claim 5,
The accumulation is
LDPC decoder, characterized in that it is performed in parity bit addresses updated using the sequence. The method of claim 6,
The cumulative
LDPC decoder, characterized in that it is performed while changing rows of the sequence in units of CPM size of the parity check matrix. Receiving a signal corresponding to a Low Density Parity Check (LDPC) codeword having a length of 64800 and a code rate of 2/15, encoded using a sequence corresponding to a parity check matrix; and
performing decoding corresponding to the parity check matrix on the received signal;
LDPC decoding method, characterized in that the sequence is represented by the following table.
[table]
Line 1: 615 898 1029 6129 8908 10620 13378 14359 21964 23319 26427 26690 28128 33435 36080 40697 43525 44498 50994
Line 2: 165 1081 1637 2913 8944 9639 11391 17341 22000 23580 32309 38495 41239 44079 47395 47460 48282 51744 52782
Line 3: 426 1340 1493 2261 10903 13336 14755 15244 20543 29822 35283 38846 45368 46642 46934 48242 49000 49204 53370
Line 4: 407 1059 1366 2004 5985 9217 9321 13576 19659 20808 30009 31094 32445 39094 39357 40651 44358 48755 49732
Line 5: 692 950 1444 2967 3929 6951 10157 10326 11547 13562 19634 34484 38236 42918 44685 46172 49694 50535 55109
Line 6: 1087 1458 1574 2335 3248 6965 17856 23454 25182 37359 37718 37768 38061 38728 39437 40710 46298 50707 51572
Line 7: 1098 1540 1711 7723 9549 9986 16369 19567 21185 21319 25750 32222 32463 40342 41391 43869 48372 52149 54722
Line 8: 514 1283 1635 6602 11333 11443 17690 21036 22936 24525 25425 27103 28733 29551 39204 42525 49200 54899 54961
Line 9: 357 609 1096 2954 4240 5397 8425 13974 15252 20167 20362 21623 27190 42744 47819 49096 51995 55504 55719
Line 10: 25 448 1501 11572 13478 24338 29198 29840 31428 33088 34724 37698 37988 38297 40482 46953 47880 53751 54943
Line 11: 328 1096 1262 10802 12797 16053 18038 20433 20444 25422 32992 34344 38326 41435 46802 48766 49807 52966 55751
Line 12: 34 790 987 5082 5788 10778 12824 18217 23278 24737 28312 34464 36765 37999 39603 40797 43237 53089 55319
Line 13: 226 1149 1470 3483 8949 9312 9773 13271 17804 20025 20323 30623 38575 39887 40305 46986 47223 49998 52111
Line 14: 1088 1091 1757 2682 5526 5716 9665 10733 12997 14440 24665 27990 30203 33173 37423 38934 40494 45418 48393
Line 15: 809 1278 1580 3486 4529 6117 6212 6823 7861 9244 11559 20736 30333 32450 35528 42968 44485 47149 54913
Line 16: 369 525 1622 2261 6454 10483 11259 16461 17031 20221 22710 25137 26622 27904 30884 31858 44121 50690 56000
Line 17: 423 1291 1352 7883 26107 26157 26876 27071 31515 35340 35953 36608 37795 37842 38527 41720 46206 47998 53019
Line 18: 540 662 1433 2828 14410 22880 24263 24802 28242 28396 35928 37214 39748 43915 44905 46590 48684 48890 55926
Line 19: 214 1291 1622 7311 8985 20952 22752 23261 24896 25057 28826 37074 37707 38742 46026 51116 51521 52956 54213
Line 20: 109 1305 1676 2594 7447 8943 14806 16462 19730 23430 24542 34300 36432 37133 41199 43942 45860 47598 48401 49407
Line 21: 242 388 1360 6721 14220 21029 22536 25126 32251 33182 39192 42436 44144 45252 46238 47369 47607 47695 50635 51469
Line 22: 199 958 1111 13661 18809 19234 21459 25221 25837 28256 36919 39031 39107 39262 43572 45018 45959 48006 52387 55811
Line 23: 668 1087 1451 2945 3319 12519 21248 21344 22627 22701 28152 29670 31430 32655 38533 42233 43200 44013 44459 51398
Line 24: 244 1133 1665 8222 8740 11285 12774 15922 20147 20978 28927 35086 40197 40583 41066 41223 42104 44650 45391 48437
Line 25: 5623 8050 9679 12978 15846 16049 21807 23364 27226 27758 28661 38147 46337 48141 51364 51927 55124
Line 26: 10369 13704 14491 18632 19430 21218 33392 36182 36722 37342 37415 46322 47449 51136 53392 54356 55108
Line 27: 7460 9411 11132 11739 13722 15501 25588 26463 26738 31980 31981 35002 39659 39783 41581 51358 55114
Line 28: 8915 15253 15264 16513 16896 18367 19110 23492 32074 33302 42443 43797 44715 47538 48515 53464 53548
Line 29: 5884 8910 10123 11311 13654 14207 16122 18113 23100 23784 24825 39629 46372 52454 52799 55039 55973 The method of claim 8,
The LDPC codeword is
It is generated based on accumulation performed using the sequence,
The accumulation is the second bit of information bits corresponding to the LDPC codeword

As for

(p _x (0≤x≤56159) is the memory used for the accumulation,

is the addition operator)
LDPC decoding method characterized in that it is performed using 19 equations of.

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