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KR20140104717A - Semiconductor light emitting device and manufacturing method of the same - Google Patents

Semiconductor light emitting device and manufacturing method of the same Download PDF

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Publication number
KR20140104717A
KR20140104717A KR1020130018552A KR20130018552A KR20140104717A KR 20140104717 A KR20140104717 A KR 20140104717A KR 1020130018552 A KR1020130018552 A KR 1020130018552A KR 20130018552 A KR20130018552 A KR 20130018552A KR 20140104717 A KR20140104717 A KR 20140104717A
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South Korea
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semiconductor layer
base semiconductor
substrate
layer
base
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KR1020130018552A
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Korean (ko)
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KR102022346B1 (en
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이건훈
박성현
윤의준
윤석호
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삼성전자주식회사
서울대학교산학협력단
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Priority to KR1020130018552A priority Critical patent/KR102022346B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

One aspect of the present invention provides a semiconductor light emitting device which includes a base semiconductor layer which has at least one void set group having multiple voids, a first conductivity type semiconductor layer which is formed on the base semiconductor layer, an active layer which is formed on the first conductivity type semiconductor layer, and the second conductivity type semiconductor layer which is formed on the active layer. According to one embodiment of the present invention, a semiconductor light emitting device which has a semiconductor layer of excellent crystallinity and improved light efficiency can be obtained.

Description

Technical Field [0001] The present invention relates to a semiconductor light emitting device,

The present invention relates to a semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device.

BACKGROUND ART A light emitting diode (LED), which is a kind of semiconductor light emitting device, is a semiconductor device capable of generating light of various colors by recombination of electrons and holes, and has a long lifetime, low power, And high vibration resistance. Therefore, demand is continuously increasing. Particularly, in recent years, group III nitride semiconductors capable of generating light in the short wavelength range of the blue series have been spotlighted. On the other hand, when a nitride semiconductor is grown using a substrate for semiconductor growth, a lattice defect occurs inside the semiconductor due to a difference in lattice constant and a thermal expansion coefficient between the substrate and the semiconductor, and a crack due to stress generation is a problem. Also, it is pointed out that light generated in a semiconductor can not be emitted to the outside due to a difference in refractive index between a semiconductor material and an external material (e.g., a substrate or air), and is totally reflected to the inside, thereby reducing light extraction efficiency.

It is an object of the present invention to improve lattice defects of a semiconductor layer, minimize stress acting on a semiconductor layer by substrate warping during growth, and effectively emit light generated inside the light emitting device to the outside, And a semiconductor light emitting element which can be improved.

Another object of the present invention is to provide a method for effectively manufacturing a semiconductor light emitting device having the above structure.

It should be understood, however, that the scope of the present invention is not limited thereto and that the objects and effects which can be understood from the solution means and the embodiments of the problems described below are also included therein.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a base semiconductor layer having at least one group of cavity aggregates in which a plurality of air gaps are grouped; a first conductivity type semiconductor layer formed on the base semiconductor layer; And a second conductivity type semiconductor layer formed on the active layer.

The base semiconductor layer may be a nitride semiconductor layer having a non-polar surface.

The sapphire substrate may further include a sapphire substrate formed on a bottom surface of the base semiconductor layer. The bottom surface of the base semiconductor layer may contact the R surface of the sapphire substrate.

The substrate may further include a substrate formed on a bottom surface of the base semiconductor layer, and the at least one group of pore groups may be located in contact with the substrate.

The plurality of cavities clustered in the group of pore groups may include a region that increases in a direction away from a lower surface of the base semiconductor layer.

The base semiconductor layer may be a semiconductor layer doped with a first conductivity type to have the same conductivity type as the first conductivity type semiconductor layer.

Alternatively, the base semiconductor layer may be an undoped semiconductor layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a base semiconductor layer including at least one group of pore groups in which a plurality of pores are grouped on a substrate; forming a first conductivity type semiconductor layer on the base semiconductor layer Forming an active layer on the first conductive type semiconductor layer, and forming a second conductive type semiconductor layer on the active layer.

Wherein forming the base semiconductor layer comprises: forming a first base semiconductor layer having at least one trench on a substrate; providing a plurality of beads to the trench; A method of manufacturing a semiconductor device, comprising: forming a second base semiconductor layer on a base semiconductor layer; removing a plurality of beads formed on the trench to form a group of pore aggregates in which a plurality of pores are grouped in the first and second base semiconductor layers And forming a third base semiconductor layer to cover the groove portion.

The substrate may be a sapphire substrate, and the forming of the base semiconductor layer on the substrate may include forming the base semiconductor layer on the R surface of the sapphire substrate.

In addition, the solution of the above-mentioned problems does not list all the features of the present invention. The various features of the present invention and the advantages and effects thereof will be more fully understood by reference to the following specific embodiments.

According to one embodiment of the present invention, a semiconductor light emitting device having improved light emitting efficiency can be obtained from a semiconductor layer having excellent quality.

Further, a method for efficiently manufacturing a semiconductor light emitting device having the above structure can be obtained.

However, the advantageous effects and advantages of the present invention are not limited to those described above, and other technical effects not mentioned can be easily understood by those skilled in the art from the following description.

1 is a cross-sectional view schematically showing a semiconductor light emitting device according to an embodiment of the present invention.
2 is a flowchart schematically showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.
3 is a cross-sectional view for explaining the step of forming the base semiconductor layer in more detail.
4 and 5 are cross-sectional views schematically showing a semiconductor light emitting device according to still another embodiment of the present invention.
6 is a photograph showing a step of forming the base semiconductor layer shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

1 is a cross-sectional view schematically showing a semiconductor light emitting device 100 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor light emitting device 100 according to the present embodiment includes a substrate 110, at least one group of pores 50 formed on the substrate 110 and having a plurality of gaps g A first conductive semiconductor layer 121 formed on the base semiconductor layer 120; an active layer 130 formed on the first conductive semiconductor layer 121; And a second conductive semiconductor layer 140 formed on the active layer 130.

The semiconductor light emitting device 100 may include first and second electrodes 161 and 162 electrically connected to the first and second conductivity type semiconductor layers 121 and 140. In this case,

The substrate 110 is provided as a substrate for semiconductor growth, and may be a substrate made of an electrically insulating or conductive material such as sapphire, SiC, MgAl 2 O 4 , MgO, LiAlO 2 , or GaN. In this case, it is preferable that sapphire having electrical insulation is used. Sapphire is a crystal having hexagonal-rhombo-symmetry (Hexa-Rhombo R3c) and has lattice constants of 13.001 Å and 4.758 Å in the c- , A C (0001) plane, an A (1120) plane, an R (1102) plane, and the like.

In the present embodiment, the substrate 110 may be a sapphire substrate on which the R plane is provided as a semiconductor growth surface. In this case, the luminous efficiency can be improved, and a structure advantageous for forming the group of pore groups 50 as described later in Fig. 3 can be provided.

More specifically, when the GaN-based semiconductor layer having a Wurtzite crystal structure is grown using the C-plane of the sapphire substrate, the Ga-based semiconductor layer is grown along the c- , And spontaneous polarization occurs due to the Wurtz crystal characteristic of the GaN-based semiconductor layer whose N atom is preferentially oriented. Furthermore, since the C-plane of the sapphire substrate has a c-axis orientation, the GaN-based semiconductor layer having a large piezoelectric constant has piezoelectric polarization in the c-axis direction due to strain due to the difference in lattice constant between the GaN- Which polarization may cause electrostatic fields inside the semiconductor layer. Such an electrostatic field separates the spatial distribution of electrons and holes and may cause the bandgap of the active layer to be distorted to hinder the internal quantum efficiency of the light emitting device.

On the other hand, when the R-plane of the sapphire substrate is provided as a growth surface, the GaN-based semiconductor layer can be grown from the M-plane to the A-plane existing on the same plane of Ga atoms and N-atoms, The efficiency deterioration can be remarkably improved. The bottom surface of the base semiconductor layer 120 may be in contact with the R surface of the sapphire substrate, and the base semiconductor layer 120 may be a nitride semiconductor layer having a non-polar surface.

The substrate 110 according to the present embodiment may be a sapphire substrate provided with a C-plane as a semiconductor growth surface, and may be a Si A substrate may also be used. When a Si substrate is used, a nucleation layer made of a material such as Al x Ga 1 - x N may be formed on the substrate 110, and then a nitride semiconductor having a desired structure may be grown thereon.

The base semiconductor layer 120 and the first and second conductivity-type semiconductor layers 121 and 140 may be nitride semiconductors. For example, the base semiconductor layer 120 and the second conductivity type semiconductor layers 121 and 140 may have a composition formula of Al x In y Ga (1-xy) 1, 0? Y? 1, 0? X + y? 1). However, the present invention is not limited to this, and it may be made of AlGaInP series semiconductor or AlGaAs series semiconductor instead of a nitride semiconductor.

The first and second conductivity type semiconductor layers 121 and 140 may be doped to have first and second conductivity types, respectively. Although not limited thereto, in the present embodiment, the first and second conductivity types Type may be n-type and p-type, respectively. As the n-type dopant, Si may be typically used, and as the p-type dopant, Zn, Cd, Be, Mg, Ca, Ba, etc. may be used.

Meanwhile, the base semiconductor layer 120 may be a semiconductor layer doped with a first conductivity type to have the same conductivity type as the first conductivity type semiconductor layer 121, but the present invention is not limited thereto, 120 may be an undoped semiconductor layer functioning as a buffer layer. When the base semiconductor layer 120 is employed as a buffer layer, the base semiconductor layer 120 has a function of mitigating lattice defects when forming the first conductivity type semiconductor layer 121. When the active layer 130 is grown, 110 may be adjusted to reduce the wavelength dispersion of the wafer.

Although the first and second conductivity type semiconductor layers 121 and 140 may have a single layer structure, the first and second conductivity type semiconductor layers 121 and 140 may have a multi-layer structure having different compositions and thicknesses as required. For example, the first and second conductivity type semiconductor layers 121 and 140 may each have a carrier injection layer capable of improving the injection efficiency of electrons and holes, and may have various superlattice structures have.

The first conductive semiconductor layer 121 may further include a current diffusion layer adjacent to the active layer 130. The current diffusion layer may have a structure in which a plurality of In x Al y Ga (1-xy) N layers having different compositions or having different impurity contents are repeatedly laminated, or a layer of an insulating material may be partially formed. The second conductive semiconductor layer 140 may further include an electron blocking layer adjacent to the active layer 130. The electron blocking layer may have a structure in which a plurality of different In x Al y Ga (1-xy) N layers are stacked or a single layer or more of Al y Ga (1-y) N, Electrons can be prevented from overflowing into the second conductivity type semiconductor layer 140 having a second conductivity type (for example, p-type) because the band gap is larger than that of the second conductivity type semiconductor layer 130.

The active layer 130 is disposed between the first conductivity type semiconductor layer 121 and the second conductivity type semiconductor layer 140 and emits light having a predetermined energy by recombination of electrons and holes. Here, the active layer 130 may be a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked, for example, an InGaN / GaN or GaN / AlGaN structure.

The base semiconductor layer 120 and the first and second conductivity type semiconductor layers 121 and 140 and the active layer 130 are formed by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy Epitaxy, HVPE), Molecular Beam Epitaxy (MBE), and the like.

In the present embodiment, the base semiconductor layer 120 includes at least one group of pore groups 50 in which a plurality of gaps g are grouped. In the present embodiment, the group of pore aggregates 50 may be formed in a region adjacent to the lower surface of the base semiconductor layer 120, and may be located in contact with the substrate 110.

As described later, the pore group group 50 is formed by collecting a plurality of air-voids g formed by removing a plurality of beads provided by the semiconductor growth process by etching or the like, The gap g may be a structure in which the outer circumferential surface is completely closed with a material forming the base semiconductor layer 120, but may include a structure in which a part of the gap g is in contact with the outer circumferential surface of another gap g in one region have.

1, the plurality of gaps g are stacked in the thickness direction in the base semiconductor layer 120 to form a group of pore aggregates 50, and in the group of pore aggregates 50 The plurality of gaps g may include a region that is increased in a direction away from a lower surface of the base semiconductor layer 120. A more detailed description related to this will be described later with reference to FIG. 3. First, the operation of the group of pore groups 50 according to the present embodiment will be described.

Specifically, the group of pore groups 50 according to the present embodiment can block dislocations generated during semiconductor layer growth. That is, a crystal defect such as a dislocation may be generated in the semiconductor layer due to a difference in lattice constant between the substrate and the substrate during growth. Such crystal defects propagate upward along the semiconductor layer growth direction to deteriorate the crystallinity of the semiconductor layer , Leakage current path of the current, etc., so that the luminous efficiency can be lowered. At this time, the gap group 50 can prevent a potential from being propagated upward along with the growth of the semiconductor layer by forming an empty space in the semiconductor layer, The layer can effectively reduce the dislocation defect density.

In addition, the substrate 110 made of a different material such as sapphire or Si may have a warp in the growth process of the semiconductor layer, the cooling process after the growth due to the difference in the thermal expansion coefficient from the semiconductor layer grown thereon, Damage such as cracks may be applied to the semiconductor layer by the stress. However, according to the present embodiment, the void group group 50 forms voids in the semiconductor layer to buffer the stress acting on the semiconductor layer, thereby protecting the semiconductor layer from cracks and the like.

In addition, the group of pore aggregates 50 can improve light extraction efficiency by scattering the light generated in the active layer 130. Specifically, the light generated in the semiconductor layer is not extracted to the outside due to a difference in refractive index with respect to an external material (e.g., air), and is totally reflected to the inside, and a considerable amount of light is lost inside. The group of pore groups 50 can scatter light by performing an action similar to the concavo-convex pattern in each of the gaps g, thereby improving the external quantum efficiency of the semiconductor light emitting device 100.

Of course, such a light scattering function may be realized by additionally forming an additional concavo-convex pattern on the substrate 110. [ The concavo-convex pattern of the substrate 110 may be formed by etching a part of the substrate 110, but the size of the pattern may be selected from the range of 5 nm to 500 μm. The concavo-convex pattern may be employed without any particular limitation as long as it has a structure for improving light extraction efficiency in a regular or irregular pattern. The shape may be employed in various forms such as a column, a mountain, a hemisphere, and a polygon.

However, the method of forming the concavo-convex pattern on the substrate 110 requires a substrate etching process, which increases the cost and complexity of the process, and causes a problem that the substrate 110 is damaged due to the etching process . However, according to the present embodiment, even when a separate uneven pattern is not formed on the substrate 110, the light scattering effect can be realized due to the air gap group 50, so that the manufacturing process is simplified and the semiconductor light emitting device having a stable structure is obtained There is an advantage to be able to.

Although not shown, the semiconductor light emitting device 100 according to the present embodiment further includes a bead (b) filling at least one of a plurality of gaps (g) in the group of cavity aggregates (50) . The beads (b) are not particularly limited as long as they can be removed by wet etching or dry etching, and may include at least one of nano silica beads and micro silica beads. In this case, it may be understood that the plurality of beads (b) provided in the semiconductor growth process are left unremoved through the etching process, or remain unremoved in the etching process.

The first and second electrodes 161 and 162 may be formed of an electrically conductive material known in the art such as Ag, Al, Ni, Cr, Pd, Cu, Pt, Sn, W, Au, Rh, Mg, Zn, and the like may be formed by vapor deposition, sputter plating, or the like. Ag / Ag / Ag / Ni / Al / Zn / Al / Ag / Pd / The present invention is not limited to the above-mentioned materials, and thus it is not limited as long as it is a conductive material, and the electrode (s) As shown in FIG.

1, the first electrode 161 is formed on the exposed region of the first conductive type semiconductor layer 121, the second electrode 162 is formed on the exposed region of the second conductive type semiconductor layer 140, And is electrically connected to the second conductive type semiconductor layer 140. However, the second conductive type semiconductor layer 140 is not limited to the first conductive type semiconductor layer 140 and may be formed as shown in FIGS. 4 and 5 And may be provided in various forms as well.

The ohmic contact layer 150 may be formed of a material having electrical ohmic characteristics with the second conductive semiconductor layer 140 and may be transparent or a reflective material depending on the usage of the semiconductor light emitting device 100 . For example, the ohmic contact layer 150 may be formed of a transparent conductive oxide such as ITO, CIO, ZnO, or the like, which has a high light transmittance and relatively good ohmic contact performance among the transparent electrode materials. Alternatively, the ohmic contact layer 150 may be formed of a highly reflective material such as Ag, Al or the like. In this case, the ohmic contact layer 150 may be suitable for mounting the semiconductor light emitting device in a so-called flip chip form. However, the ohmic contact layer 150 is not necessarily a necessary element in the present embodiment, and may be omitted in some cases.

According to the present embodiment, it is possible to obtain a high-quality semiconductor layer by mitigating the lattice defects of the semiconductor layer and the stress acting on the semiconductor layer by providing the group of cavity aggregates 50. Accordingly, the internal quantum efficiency of the semiconductor light emitting device 100 can be improved, and the external quantum efficiency can also be improved due to the light scattering function of the cavity aggregation group 50.

2 is a flowchart schematically showing a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.

Referring to FIG. 2, a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes the steps of: (S10) forming a base semiconductor layer including at least one group of cavity aggregates in which a plurality of gaps are grouped on a substrate; A method of manufacturing a semiconductor light emitting device, comprising: forming a first conductive semiconductor layer on a semiconductor layer (S20); forming an active layer on the first conductive semiconductor layer (S30); forming a second conductive semiconductor layer on the active layer Step S40. Such a semiconductor layer formation can be performed using a known semiconductor growth process such as MOCVD, HVPE, MBE and the like.

First, step (S10) of forming the base semiconductor layer with reference to FIG. 3 will be described in more detail.

3A, forming the base semiconductor layer 120 includes growing a first base semiconductor layer 120a having at least one trench v on a substrate 110 (S11 ).

In the present embodiment, the trench v may be spontaneously formed when the first base semiconductor layer 120a is grown on the substrate 110 without any additional process. Specifically, when the R surface of the sapphire substrate is employed as the growth surface of the substrate 110 during the growth of the first base semiconductor layer 120a, the first base semiconductor layer 120a grows parallel to the surface of the first base semiconductor layer 120a The first base semiconductor layer 120a has a trench v spontaneously formed at the boundary between the plurality of islands i without forming a flat surface on the top surface of the first base semiconductor layer 120a .

In this case, there is no need for a separate step for forming the trench v, for example, a step of forming a mask such as SiO 2 on the substrate 110 or etching a part after forming the base semiconductor layer , The process can be significantly simplified.

Next, a bead b is provided on the trench v as shown in FIG. 3B (S12). The beads (b) may be at least one of nano-silica beads and micro-silica beads, which may be removed by wet etching, dry etching, or the like. The beads may be spin- May be applied on the trench (v) by applying screen printing or the like.

As shown, when the trench v is provided so as to have a predetermined inclination angle at the boundary between the plurality of islands i, the plurality of beads b are stacked in the thickness direction in the trench v, But the amount of the first base semiconductor layer 120a and the substrate 110 may be increased as the distance between the first base semiconductor layer 120a and the substrate 110 is increased.

Meanwhile, the thickness t2 formed by loading the beads b at this time may be the thickness t3 of the group of cavity aggregates according to the embodiment of the present invention through a later process. That is, the thickness t3 of the group of cavity aggregates according to the present embodiment can be adjusted by controlling the thickness t2 formed by loading the beads b, wherein the thickness t2 Can be controlled by adjusting at least one parameter between the growth thickness t1 of the first base semiconductor layer 120a in which the trench is formed and the amount of the bead b provided in the trench.

Thereafter, as shown in FIG. 3C, a second base semiconductor layer 120b is formed on the first base semiconductor layer 120a (S13). This step can also be understood to re-grow the first base semiconductor layer 120a after providing the beads b on the trench v.

In this step, ELO (Epitaxial Lateral Overgrowth) can be applied so that the second base semiconductor layer 120b can grow while filling the gap between the beads b more easily.

Next, as shown in FIG. 3D, the second base semiconductor layer 120b stops growing the second base semiconductor layer 120b in a state where the second base semiconductor layer 120b does not completely cover the trench v, The plurality of beads b formed are removed to form a group of pore groups 50 in which a plurality of gaps g are clustered (S14).

The beads (b) may be removed by wet etching or dry etching. In the wet etching, for example, the second base semiconductor layer 120b stops growing in a state in which the trench v is not completely covered, so that the etchant e can easily penetrate into the trench v , And the bead (b) is removed by using the etching solution (e) to form the gap (g) in the area occupied by the bead (b). As the etching liquid (e), for example, hydrogen fluoride (HF) may be used.

The plurality of voids g formed in this step are vacant spaces provided by removing a plurality of beads b, and the group of void aggregates 50 in which the plurality of voids g are clustered is formed as shown in FIG. 3A It will be understood that it is provided corresponding to the trench (v).

Next, as shown in FIG. 3E, a third base semiconductor layer 120c is formed to cover the trench v (S15). In this step, the third base semiconductor layer 120c may be sufficiently grown to have a flat upper surface, and ELO may be applied.

Meanwhile, the first to third base semiconductor layers 120a, 120b, and 120c may be doped semiconductor layers having a first conductivity type. However, the first to third base semiconductor layers 120a, 120b, , 120b, and 120c may be undoped semiconductor layers. When an undoped semiconductor layer is employed, the base semiconductor layer can function as a buffer layer in the semiconductor light emitting element.

In addition, since the first to third base semiconductor layers 120a, 120b and 120c do not necessarily have to be doped with the same dopant, the first base semiconductor layer is formed of the undoped semiconductor layer 120a, The base semiconductor layers 120b and 120c may be formed of a doped semiconductor layer having a first conductivity type.

Next, referring again to FIG. 2, a first conductive semiconductor layer is formed on the base semiconductor layer (S20), and an active layer is formed on the first conductive semiconductor layer (S30). As described above, the active layer may be formed to have a multiple quantum well (MQW) structure such as an InGaN / GaN or GaN / AlGaN structure in which a quantum well layer and a quantum barrier layer are alternately stacked .

Thereafter, a second conductive semiconductor layer is formed on the active layer (S40). Although not shown separately, the ohmic electrode layer is formed on the second conductive semiconductor layer, and then the first and second conductive semiconductor layers By forming the first and second electrodes to be connected, the structure shown in FIG. 1 can be obtained.

According to the present embodiment, by providing the group of pore aggregates 50 to relieve the lattice defects of the semiconductor layer and the stress acting on the semiconductor layer to obtain a high-quality semiconductor layer, the internal quantum efficiency is improved, ) Can efficiently and easily produce a semiconductor light emitting device having improved external quantum efficiency due to the light scattering function.

4 is a cross-sectional view schematically showing a semiconductor light emitting device 200 according to still another embodiment of the present invention.

4, the semiconductor light emitting device 200 according to the present embodiment includes a base semiconductor layer 120, a first conductive semiconductor layer 121 formed on the base semiconductor layer 120, An active layer 130 formed on the first conductivity type semiconductor layer 121 and a second conductivity type semiconductor layer 140 formed on the active layer 130 and a conductive substrate 130 formed on the second conductivity type semiconductor layer 140. [ (170).

Here, the base semiconductor layer 120 includes at least one group of pore groups 50 in which a plurality of gaps g are grouped.

That is, this embodiment may be understood as an embodiment of a so-called vertical structure in which the growth substrate 110 is removed and one surface of the base semiconductor layer 120 is provided as a light emitting surface, unlike the embodiment of FIG. 1 .

The first and second electrodes 161 and 162 may be electrically connected to the first and second conductivity type semiconductor layers 121 and 140. In this embodiment, When the first conductivity type is doped so that the semiconductor layer 120 has the same conductivity type as the first conductivity type semiconductor layer 121, the first electrode 161 may be formed on the base semiconductor layer 120 There will be.

The second electrode 162 may be formed between the second conductive semiconductor layer 140 and the conductive substrate 170 and may include a light reflecting function and a second conductivity type semiconductor layer 140, Such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt and Au.

The conductive substrate 170 may be formed of a material including any one of Au, Ni, Al, Cu, W, Si, Se, GaAs, SiAl, Ge, SiC, AlN, Al2O3, GaN, and AlGaN And may be formed by a process such as plating, sputtering, vapor deposition or adhesion.

In the present embodiment, since the cavity aggregate group 50 has a light scattering function, the light generated in the active layer 130 can be easily emitted to the outside through the first surface of the first semiconductor layer 120 Also, since the refractive index of the gap g may be 1 as in air, the total reflection phenomenon due to the refractive index difference with the external material in the semiconductor layer can be effectively reduced.

In addition, the present embodiment requires a step of removing the semiconductor growth substrate. Since the void aggregation group 50 forms an empty space at the interface between the semiconductor growth substrate and the base semiconductor layer 120, It is possible to provide a structure in which the process can be performed more easily.

5 is a cross-sectional view schematically showing a semiconductor light emitting device 300 according to still another embodiment of the present invention.

5, the semiconductor light emitting device 300 according to the present embodiment includes a substrate 110, at least one group of void aggregates formed on the substrate 110 and having a plurality of gaps g A first conductive semiconductor layer 121 formed on the base semiconductor layer 120; an active layer 130 formed on the first conductive semiconductor layer 121; And a second conductive semiconductor layer 140 formed on the active layer 130.

The present embodiment can be understood as a so-called nano LED chip type semiconductor light emitting device.

The first conductive semiconductor layer 121 may be defined as a nanocore protruding from the base semiconductor layer 120. The base semiconductor layer 120 may be a layer providing a growth surface of the nanocore , Or a semiconductor doped with the first conductivity type. A mask layer m having an open region for growing a nanocore may be formed on the base semiconductor layer 120. Here, the mask layer m may be a silicon oxide such as SiO 2 , a silicon nitride such as SiN x , or a dielectric material such as silicon oxynitride (SiO x N y ).

The nanocore is formed on an open region of the mask layer m, and the active layer 130 may be formed as a shell layer on a protruding surface of the nanocore. A second conductivity type semiconductor layer 140 is formed on the active layer 130 and a core-shell type nano-light-emitting structure N may be formed thereon.

Of course, in the present embodiment, the nano-light-emitting structure N is illustrated as a rod-like structure as a core-shell structure, but is not limited thereto, and may have a structure similar to a pyramid structure.

In the present embodiment, the semiconductor light emitting device may include a filling material 180 filled between the nanostructured structures N. The filling material 180 may structurally stabilize the nano-light-emitting structure N. The filling material 180 may be formed of a transparent material such as SiO 2 , although it is not limited thereto.

The ohmic contact layer 150 may be formed on the nano-light-emitting structure N to be connected to the second conductive semiconductor layer 140. In this case, the semiconductor light emitting device may include first and second electrodes 161 and 162 connected to the base semiconductor layer 120 and the ohmic contact layer 150, respectively.

In the case of the semiconductor light emitting device using the nano-light-emitting structure N, the emission area can be increased by using the nano-light-emitting structure N to improve the luminous efficiency, and the non-polarity of the active layer 130 can be more easily induced , The internal quantum efficiency by polarization can be improved more effectively.

6 is a photograph showing the semiconductor light emitting device according to the embodiment of the present invention in process steps. 6 (a) to 6 (e) show the semiconductor light emitting device in a state in which the steps shown in Figs. 3a to 3e are completed, respectively.

Referring to the top view and the top view (right upper end) shown in FIG. 6A together, a base semiconductor layer 120a and a trench v constituting a plurality of islands (i) can be identified.

Referring to FIGS. 6 (b) and 6 (c), when the bead b is provided in the trench v and the second base semiconductor layer 120b is formed on the first base semiconductor layer 120a, 120b are formed.

6 (d). Referring to FIG. 6 (d) and FIG. 6 (e) together, the first and second bases b and b are removed by wet etching, It can be confirmed that at least one group of cavity aggregates in which a plurality of gaps g are grouped is formed in the semiconductor layers 120a and 120b.

The present invention is not limited to the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 200, 300: semiconductor light emitting element
110: substrate 120: base semiconductor layer
121: first conductivity type semiconductor layer 130: active layer
140: second conductive type semiconductor layer g: void
50: cavity group 150: ohmic contact layer
161: first electrode 162: second electrode
170: conductive substrate 180: filling material

Claims (10)

A base semiconductor layer having at least one group of void aggregates in which a plurality of voids are clustered;
A first conductive semiconductor layer formed on the base semiconductor layer;
An active layer formed on the first conductive semiconductor layer; And
A second conductive semiconductor layer formed on the active layer;
And a light emitting element.
The method according to claim 1,
Wherein the base semiconductor layer is a nitride semiconductor layer having a non-polar surface.
The method according to claim 1,
And a sapphire substrate formed on a bottom surface of the base semiconductor layer,
And the bottom surface of the base semiconductor layer is in contact with the R surface of the sapphire substrate.
The method according to claim 1,
And a substrate formed on a bottom surface of the base semiconductor layer,
Wherein the at least one group of cavity aggregates is located in contact with the substrate.
The method according to claim 1,
Wherein a plurality of cavities clustered in the group of pore groups includes a region that becomes larger in a direction away from a bottom surface of the base semiconductor layer.
The method according to claim 1,
Wherein the base semiconductor layer is a semiconductor layer doped with a first conductivity type to have the same conductivity type as the first conductivity type semiconductor layer.
The method according to claim 1,
Wherein the base semiconductor layer is an undoped semiconductor layer.
Forming a base semiconductor layer including at least one group of pore groups in which a plurality of pores are grouped on a substrate;
Forming a first conductive semiconductor layer on the base semiconductor layer;
Forming an active layer on the first conductive semiconductor layer; And
Forming a second conductive semiconductor layer on the active layer;
Gt; a < / RTI > semiconductor light emitting device.
9. The method of claim 8,
Wherein forming the base semiconductor layer comprises:
Forming a first base semiconductor layer having at least one trench on a substrate;
Providing a plurality of beads to the trench;
Forming a second base semiconductor layer on the first base semiconductor layer;
Removing a plurality of beads formed in the trench to form a group of pore aggregates in which a plurality of pores are grouped in the first and second base semiconductor layers; And
Forming a third base semiconductor layer to cover the groove portion;
Wherein the semiconductor light emitting device is formed on a semiconductor substrate.
9. The method of claim 8,
Wherein the substrate is a sapphire substrate,
Wherein forming the base semiconductor layer on the substrate comprises:
And forming the base semiconductor layer on the R surface of the sapphire substrate.
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Publication number Priority date Publication date Assignee Title
CN111864019A (en) * 2020-07-10 2020-10-30 武汉大学 Flip light-emitting diode with embedded scattering layer and preparation method thereof

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Publication number Priority date Publication date Assignee Title
JP2007103774A (en) * 2005-10-06 2007-04-19 Showa Denko Kk Group iii nitride semiconductor stacked structure and its manufacturing method
KR20120092928A (en) * 2011-02-14 2012-08-22 삼성전자주식회사 Semiconductor device and method of manufacturing the same

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2007103774A (en) * 2005-10-06 2007-04-19 Showa Denko Kk Group iii nitride semiconductor stacked structure and its manufacturing method
KR20120092928A (en) * 2011-02-14 2012-08-22 삼성전자주식회사 Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111864019A (en) * 2020-07-10 2020-10-30 武汉大学 Flip light-emitting diode with embedded scattering layer and preparation method thereof
CN111864019B (en) * 2020-07-10 2021-11-30 武汉大学 Flip light-emitting diode with embedded scattering layer and preparation method thereof

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