KR101382801B1

KR101382801B1 - Semiconductor light emitting device and fabrication method thereof

Info

Publication number: KR101382801B1
Application number: KR1020070082493A
Authority: KR
Inventors: 손효근; 정흥섭
Original assignee: 엘지이노텍 주식회사
Priority date: 2007-08-16
Filing date: 2007-08-16
Publication date: 2014-04-09
Also published as: KR20090017945A

Abstract

An embodiment of the present invention relates to a semiconductor light emitting device and a manufacturing method thereof.

According to an embodiment of the present invention, a semiconductor light emitting device includes: a semiconductor layer having a concave-convex surface having a concave-convex surface; It includes a light emitting structure in which each layer is formed in an uneven shape on the semiconductor layer of the uneven surface.

Semiconductor, light emitting device, uneven structure

Description

TECHNICAL FIELD The present invention relates to a semiconductor light emitting device and a fabrication method thereof,

Generally, a semiconductor light emitting device has a light emitting region covering ultraviolet, blue, and green regions. In particular, the GaN-based nitride semiconductor light emitting device has been widely applied to blue / green LED optical devices, high-speed switching devices such as MESFET (Metal Semiconductor Field Effect Transistor) and HEMT (Hetero junction Field-Effect Transistors) .

1 is a view showing a conventional semiconductor light emitting device.

1, the semiconductor light emitting device 10 includes an n-type semiconductor layer 13, an active layer 15, and a p-type semiconductor layer 17 formed on a sapphire substrate 11. The p-type electrode 21 is formed on the n-type electrode 19 and the p-type semiconductor layer 17 on the n-type semiconductor layer 13 through a partial etching process.

When the voltage is applied to the p-type electrode 21 and the n-type electrode 19, a forward bias is applied between the p-type semiconductor layer 17 and the n-type semiconductor layer 13, . At this time, electrons and holes are recombined in the active layer 15 to emit light.

The semiconductor light emitting device 10 needs to have high internal quantum efficiency in order to obtain a large amount of light from a current flowing therein, and an extraction efficiency for emitting light to the outside of the light emitting device. This should be high. To this end, by growing a semiconductor layer having excellent crystallinity between the sapphire substrate 11 and the n-type semiconductor layer 13 to increase the internal quantum efficiency of the light emitting device, and by modifying the geometry of the semiconductor layer, the total internal reflection of the emitted light ( The total internal reflection ratio should be reduced to increase the extraction efficiency of the light emitting device.

In the conventional semiconductor light emitting device, a large amount of light emitted from the active layer does not easily escape to the outside of the light emitting device, and causes a total reflection therein, thereby circulating and disappearing.

An embodiment of the present invention provides a semiconductor light emitting device and a method of manufacturing the same, by forming a concave-convex structure for a reflector layer and a light emitting structure on a substrate to improve light extraction efficiency.

An embodiment of the present invention provides a semiconductor light emitting device and a method of manufacturing the same, by providing an active layer having an inclined concave-convex structure, to recombine electrons and holes in the active layer more efficiently.

Method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention comprises the steps of forming a semiconductor layer of the uneven surface; And forming a light emitting structure in which each layer has an uneven structure on the semiconductor layer of the uneven surface.

According to a semiconductor light emitting device and a method of manufacturing the same according to an embodiment of the present invention, by reflecting, scattering or refracting the light emitted from the inside of the semiconductor light emitting device, by reducing the total internal reflection ratio, light extraction efficiency and external quantum efficiency Can improve.

In addition, it is possible to improve the optical characteristics and reliability of the semiconductor light emitting device.

In addition, due to the inclined structure of the active layer, the emission area may be enlarged and doubled, and electrons and holes may be recombined more efficiently, thereby increasing internal quantum efficiency.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings.

2 is a view illustrating a semiconductor light emitting device according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor light emitting device 100 may include a substrate 110, a semiconductor layer 120 having an uneven surface, and a first conductive semiconductor layer 140 having an uneven structure and an active layer having an uneven structure as a light emitting structure having an uneven structure. 140 and the second conductive semiconductor layer 150 having an uneven structure.

The substrate 110 may be selected from the group consisting of sapphire substrate (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP and GaAs, and may be removed after the light emitting structure is generated.

A mask pattern 112 is formed on the substrate 110. The mask pattern 112 may be selected from the group consisting of Si0 ₂ , Si0 _x , SiN ₂ , SiN _x , SiO _x N _y, or a metal material. Here, the planar shape of the mask pattern 112 may be formed in the shape of a polygon or a circle, such as a square, a pentagon.

The semiconductor layer 120 having the uneven surface is formed on the substrate 110 on which the mask pattern 112 is formed. The uneven surface semiconductor layer 120 may be selected from the group consisting of GaN, InN, InGaN, AlGaN, or InAlGaN. In addition, the uneven surface semiconductor layer 120 may be implemented as an undoped semiconductor layer doped with a dopant or a conductive semiconductor layer doped with an n-type dopant.

The uneven structure semiconductor layer 120 is a low defect semiconductor layer, and after the first semiconductor layer 122 is formed from a region where the mask pattern 112 is not formed, the first semiconductor layer is formed to have a predetermined height. By forming a second semiconductor layer (124 in Fig. 5) and sealing it with a neighboring second semiconductor layer, the surface of the semiconductor layer 120 on the uneven surface is formed into an uneven shape.

The surface 126 of the semiconductor layer 120 of the uneven surface is formed of the uneven structure 126a, 126b, the depth of the yaw (126a) portion is formed of 0 <depth ≤ 5um, between the yaw and yaw The period or the period between the iron 126b and the iron 126b may be formed with 0 <period ≦ 10um. In addition, the through dislocation density of the semiconductor layer 120 on the uneven surface is a × 10 ⁷ / cm ² The above a is 0 <a≤10. That is, the penetration dislocation density may be 10 ⁸ / cm ² .

The semiconductor layer 120 of the uneven surface on the substrate 110 has an epitaxial lateral overgrowth (ELO) method, a lateral epitaxy on patterned sapphire substrate (LEPS) method using a patterned sapphire substrate (PSS), and a pendant-epitaxy And a variety of selective growth techniques such as CE (cantilever epitaxy) using a patterned substrate (eg, Si).

A buffer layer (not shown) may be formed between the substrate 110 and the semiconductor layer 120 on the uneven surface. The buffer layer is a layer for reducing a difference in lattice constant from the substrate 110, and a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, an InGaN buffer layer, and the like may be selectively formed. Such a buffer layer may not be formed.

The light emitting structure having the uneven structure is formed on the semiconductor layer 120 on the uneven surface. The light emitting structure includes a second conductive semiconductor layer 130 having an uneven structure, an active layer 140 having an uneven structure, and a second conductive semiconductor layer 150 having an uneven structure.

The first conductive semiconductor layer 130 is formed in a concave-convex structure (132a, 132b) on the semiconductor layer 120 of the concave-convex surface. The first conductive semiconductor layer 130 may be implemented as at least one or more n-type semiconductor layer, the n-type semiconductor layer may be selected from GaN, AlGaN, InGaN, etc., Si, Ge, Sn, Se, N-type dopants such as Te and the like are selectively doped.

The active layer 140 of the uneven surface 141n is formed on the first conductive semiconductor layer 130. The active layer 140 is formed of a single quantum well structure or a multiple quantum well structure. In the active layer 140, a quantum well layer 141 made of InGaN and a quantum barrier layer 142 made of AlGaN or GaN are alternately formed, and in the case of a multi-quantum well structure, the period of the quantum well layer and the quantum barrier layer is It can be formed in several cycles (eg 10 cycles). The quantum well layer 141 and the quantum barrier layer 142 have uneven surfaces 141a and 142a, such as inverted polygonal horns or inverted pyramid shapes.

Conductive cladding layers may be formed on both sides of the active layer 140, respectively.

The second conductive semiconductor layer 150 having an uneven structure is formed on the active layer 140. The second conductive semiconductor layer 150 may be implemented with at least one p-type semiconductor layer, and the p-type semiconductor layer may be selected from GaN, AlGaN, InGaN, InN, AlN, AlInGaN, and the like. Dopants (eg Mg, Ze) are doped. The surface 152 of the second conductive semiconductor layer 150 is formed of a concave-convex structure having an inverted polygonal horn or an inverted pyramid shape.

When the semiconductor light emitting device 100 is implemented as a horizontal semiconductor light emitting device, the second conductive semiconductor layer 150 is partially exposed to a part of the first conductive semiconductor layer 130 to be exposed, and the first conductive semiconductor is exposed. A first electrode may be formed on the layer 130, and a second electrode may be formed on the second conductive semiconductor layer 150. In addition, in the case of a vertical semiconductor light emitting device, a conductive support substrate (not shown) that performs a function of the second electrode and the substrate is formed on the second conductive semiconductor layer 150, and then the substrate 110 is laser lifted off. After removal by the LLO) method, a first electrode is formed.

In addition, the semiconductor light emitting device may be implemented in a pn junction structure or an np junction structure, and may be formed in a structure such as npn or pnp by forming a third conductive semiconductor layer on the second conductive semiconductor layer 150.

Meanwhile, a manufacturing process of the semiconductor light emitting device according to the embodiment of the present invention will be described with reference to FIGS. 3 to 7.

3 is a cross-sectional view of the mask layer formed on the substrate according to an embodiment of the present invention, Figure 4 is a side cross-sectional view showing a mask pattern according to the etching of the mask layer of FIG.

3 and 4, the growth mask layer 111 is formed on the substrate 110 using PECVD or sputtering equipment, and the growth mask layer 111 is deposited in a predetermined pattern. The mask pattern 112 is formed by performing a dry or wet etching process. The mask material may be selected from Si0 ₂ , Si0 _x , SiN ₂ , SiN _x , SiO _x N _y, or a metal material (eg tungsten).

Here, the mask pattern 112 includes a mask having a polygonal or circular shape or a net pattern, such as a triangle, a rectangle, a pentagon, and a planar shape, and is formed at predetermined intervals. In addition, the mask pattern 112 may have a thickness of several tens nm to several hundred nm. Embodiments of the present invention are not limited thereto.

5 is a cross-sectional view illustrating a semiconductor layer 120 having a concave-convex surface on a substrate according to an exemplary embodiment of the present invention. FIG. 6 is a diagram illustrating a state where a penetration potential of the uneven surface of the semiconductor layer 120 is reduced.

Referring to FIG. 5, a semiconductor layer 120 having an uneven surface is formed on the substrate 110 on which the mask pattern 112 is formed. The semiconductor layer 120 of the uneven surface includes a first semiconductor layer 122 and a second semiconductor layer 124, and the first semiconductor layer 122 is perpendicular to an area where the mask pattern 112 is not formed. The second semiconductor layer 124 is formed between the first semiconductor layer 122 and on the mask pattern 124 to promote growth in the horizontal direction. It is sealed with a semiconductor layer. The surface 126 of the second semiconductor layer 124 may be formed in a concave-convex structure (126a, 126b) having an inverted hexagonal horn or an inverted pyramid shape.

The uneven surface semiconductor layer 120 supplies NH ₃ and TMGa at a predetermined growth temperature (500 to 1200 ° C.) using, for example, MOCVD equipment to grow the first GaN semiconductor layer 122 to 1 μm or more. . At this time, as the second GaN semiconductor layer 124 is grown under more active horizontal growth, the second GaN semiconductor layer 124 may be sealed with another horizontal GaN semiconductor layer. In this case, when the surface of the second GaN semiconductor layer 124 has an uneven shape, the horizontal growth step is stopped, so that the surface 126 of the uneven surface of the semiconductor layer 120 may have the uneven shape 126a and 126b. .

The uneven surface semiconductor layer 120 may be selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, or InAlGaN. Here, the semiconductor layer 120 of the uneven surface on the substrate 110 is an epitaxial lateral overgrowth (ELO) method, a lateral epitaxy on patterned sapphire substrate (LEPS) method using a patterned sapphire substrate (PSS), and a pendant (PE) It may be selectively grown using any one of a variety of selective growth techniques, such as epitaxy) and cantilever epitaxy (CE) using a patterned substrate (eg, Si). In addition, the pattern on the substrate may be formed in various patterns.

Referring to FIG. 6, the surface 126 of the semiconductor layer 120 on the uneven surface is formed of an uneven structure, and the depth of the uneven portion 126a may be formed with 0 <depth ≦ 10um. The period between or the period between the iron 126b and the iron 126b may be formed as 0 <period ≤ 20um. The size and period of such irregularities are not limited. In addition, since the first semiconductor layer 122 is grown and the second semiconductor layer 124 is grown, the through dislocation 121 is bent to the horizontal potential 123 by the horizontal growth of the semiconductor layer. The density of the through dislocations may be reduced on the uneven surface of. For example, the through dislocation density of the semiconductor layer 120 on the uneven surface is a × 10 ⁷ / cm ² The above a is 0 <a≤10. That is, the penetration dislocation density may be 10 ⁸ / cm ² . In addition, the penetration potential density may be larger or smaller depending on the growth conditions, the pattern of the growth mask, and the like. In addition, by using a horizontal growth technology, a considerable number of through dislocations are bent in the horizontal direction, thereby reducing the density of the through dislocations propagating to the surface of the semiconductor layer 120 on the uneven surface.

The cross-sectional shape of the first semiconductor layer 122 of the semiconductor layer 120 of the uneven surface may be made into a polygon such as a triangle, trapezoid, square shape, etc. For the surface shape of the uneven structure, an inverted hexagonal horn or an inverted pyramid It is provided in the shape. 9 is a planar scanning electron microscope (SEM) photograph of the semiconductor layer 120 of the uneven surface according to the embodiment of the present invention, wherein the surface 126 of the semiconductor layer 120 of the uneven surface is concave (126a). ) Portion is formed in the mask pattern 112 region, and the iron 126b portion is formed in the region between the mask patterns 112. Inclined surface between yaw 126a and iron 126b at this time {

} Is formed.

Here, a GaN buffer layer may be formed between the uneven surface semiconductor layer 120 and the substrate 110. The GaN buffer layer may be grown to a thickness of 20 to 30nm at 500 ~ 600 ℃.

As shown in FIG. 7, a light emitting structure having an uneven structure is formed on the semiconductor layer 120 of the uneven surface. The light emitting structure includes a first conductive semiconductor layer 130, an active layer 140, and a second conductive semiconductor layer 150.

The first conductive semiconductor layer 130 is an n-type semiconductor layer having uneven surfaces 132: 132a and 132b, and may be selectively formed from GaN, AlGaN, InGaN, InN, AlN, AlInGaN, etc. doped with an n-type dopant. have. The first conductive semiconductor layer 130 is grown to be stacked in a concave-convex shape on the semiconductor layer 120 on the concave-convex surface, so that the surface 132 of the first conductive semiconductor layer 130 has a concave-convex structure.

Here, FIG. 10 is a planar SEM photograph of the first conductive semiconductor layer 130. The surface 132 is a hexagonal pyramid concave region 132a and the iron region 132b around the concave region in a continuous pattern. It is formed.

The active layer 140 of the uneven surface 141n is formed on the first conductive semiconductor layer 130. The active layer 140 has a period of the quantum well layer 141 and the quantum barrier layer 142, and is single or single. It can be formed into a multiple quantum well structure. Surfaces or interfaces of the quantum well layer 141 and the quantum barrier layer 142 are formed of the uneven structures 141a and 142a.

The second conductive semiconductor layer 150 of the uneven surface 152 is formed on the active layer 140. The second conductive semiconductor layer 150 may be implemented as a p-type semiconductor layer, and the p-type semiconductor layer may be selected from GaN, AlGaN, InGaN, InN, AlN, and AlInGaN doped with a p-type dopant.

8 is a diagram illustrating a structure of an active layer 140 according to an embodiment of the present invention.

Referring to FIG. 8, the active layer 140 may include a plane 141m or interface (0001) perpendicular to the c-axis ([0001]) and an inclined surface 141j. The plane or interface perpendicular to the C-axis in the active layer 140 may be formed in a minimum or small ratio in order to reduce the QCSE (Quantum Confined Stark Effect) and increase the extraction efficiency of the emitted light through the uneven surface of the semiconductor. Accordingly, the active layer of the concave-convex structure can improve the recombination efficiency of electrons and holes therein. As a result, the internal quantum efficiency can be improved.

In addition, by forming the semiconductor layers 120, 130, 140, and 150 having an uneven structure, the reflection and scattering of light may be induced, thereby reducing the total internal reflection ratio and improving the extraction efficiency of the light emitting device. As a result, the external quantum efficiency can be improved.

11 and 12 illustrate SEM photographs and cathode luminescence (CL) images at the same positions of planes of the first conductive semiconductor layer or the uneven surface semiconductor layer according to the embodiment of the present invention.

In the SEM image of FIG. 11, the uneven structure is honeycomb-shaped, and has a connection structure of a hexagonal pyramidal concave region and a hexagonal linear iron region (a plane perpendicular to the c-axis). Since light is better extracted from the inclined surface of the concave-convex region of the concave-convex structure, the extraction efficiency of the LED can be increased. As shown in FIG. 12, when the electron beam is irradiated from the outside, most of the light emitted from GaN of the second conductive semiconductor layer is emitted in the inclined region. At this time, the light extraction efficiency is higher than the planar region in the inclined region. As shown in the drawing, most of the GaN bandedge emitting light (eg, 364 nm) is extracted through the inclined surface of the uneven structure semiconductor surface.

13 and 14 are planar SEM photographs and CL images of the first conductive semiconductor layer or the semiconductor layer of the uneven surface having uneven surfaces of different sizes of the present invention. That is, the uneven structure of FIGS. 13 and 14 has a smaller or irregular size than the uneven structure of FIGS. 11 and 12, and the iron surface is relatively increased in the uneven structure. As shown in FIGS. 13 and 13, most of GaN bandedge emitting light (eg, 364 nm) is extracted through the inclined surface of the uneven structure semiconductor surface in the CL image. In other words, it can be seen that light extraction efficiency is higher in the hexagonal pyramidal yaw region than in the iron region. FIG. 13 also shows that the area of the plane perpendicular to the c-axis is wider and the inclined plane inclined from the c-axis is narrower than in FIG. 11. Accordingly, the region of the quantum well layer grown on the inclined surface may also be narrowed. In the inclined quantum well layer, the electric field due to the polarization phenomenon is weak, so that electrons and holes in the active layer can be recombined more efficiently.

Therefore, when comparing FIG. 11 and FIG. 13, the light extraction efficiency can be increased as the concave region of each layer, particularly the active layer, of the light emitting structure is wider than the iron region.

15 is a diagram illustrating a first modified example of the semiconductor light emitting device 100A according to the embodiment of the present invention. The first variation is the same reference numerals for the same parts as in FIG. 2 and duplicate descriptions will be omitted.

A buffer layer 114 or a semiconductor bulk layer having a thickness of several micrometers or more is formed on the substrate 110 of the semiconductor light emitting device 100A, and a mask layer is formed on the buffer layer 114, and then, an etch process is performed. The mask pattern 112a is formed. The buffer layer 114 may be selectively formed among a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, and an InGaN buffer layer.

When the mask pattern 112a is formed on the buffer layer 114, the second semiconductor layer 120 is formed on the buffer layer 114 and the mask pattern 112a. Here, the second semiconductor layer 120 may be grown using the ELO method.

16 is a second modified example of the semiconductor light emitting device 100B according to the embodiment of the present invention. The second modified example will be denoted by the same reference numerals for the same parts as those in FIG. 2, and redundant descriptions thereof will be omitted.

Referring to FIG. 16, in the semiconductor light emitting device 100B, the uneven pattern 115 is formed on the substrate 110, and the first semiconductor layer 122 and the second semiconductor layer (above the iron pattern of the uneven pattern 115). A semiconductor layer 120 having an uneven surface formed of 124 is formed. Here, the second semiconductor layer 120 is grown using a lateral epitaxy on patterned sapphire substrate (LEPS) method. The substrate 110 is integrally formed with the iron pattern, and a mask pattern is formed on the concave pattern or the convex pattern of the concave-convex pattern 115.

In this modification, the crystallinity of the semiconductor layer under the light emitting structure may be improved, and the geometric shape may be modified, thereby improving luminous efficiency and reliability.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications not illustrated in the drawings are possible.

For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

In the description of the embodiments according to the present invention, each layer (film), region, pattern or structure is referred to as being "on" or "under" a substrate, each layer Quot; on "and" under "include both the meaning of" directly "and" indirectly ". In addition, the criteria for above or below each layer will be described with reference to the drawings.

1 is a side sectional view of a conventional semiconductor light emitting device.

2 is a side cross-sectional view of a semiconductor light emitting device according to an embodiment of the present invention.

3 to 7 are cross-sectional views illustrating a process of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.

8 is a view showing the structure of an active layer in a semiconductor light emitting device according to an embodiment of the present invention.

9 is a planar SEM photograph of the semiconductor layer on the uneven surface of the semiconductor light emitting device according to the embodiment of the present invention.

10 is a planar SEM photograph of the first conductive semiconductor layer in the semiconductor light emitting device according to the embodiment of the present invention.

11 and 12 are planar SEM photographs and CL images of a semiconductor layer before growth of an active layer in the semiconductor light emitting device according to the embodiment of the present invention.

13 and 14 are planar SEM photographs and CL images of another structure of the semiconductor layer before the active layer is grown in the semiconductor light emitting device according to the embodiment of the present invention.

15 is a cross-sectional view illustrating a first modified example of the semiconductor light emitting device according to the embodiment of the present invention.

16 is a cross-sectional view illustrating a second modified example of the semiconductor light emitting device according to the embodiment of the present invention.

100,100A, 100B: semiconductor light emitting device

110 substrate 112112a mask pattern

114: buffer layer 120: semiconductor layer on uneven surface

122: first semiconductor layer 124: second semiconductor layer

130: first conductive semiconductor layer 140: active layer

150: second conductive semiconductor layer

Claims

A semiconductor layer having a concave-convex surface having a concave-convex surface;

A substrate having a mask pattern formed below the semiconductor layer on the concave-convex surface below a region of the concave-convex shape; And

A light emitting structure in which each layer is formed in an uneven shape on the semiconductor layer of the uneven surface,

The substrate has an uneven pattern formed integrally,

The mask pattern is formed on the concave pattern of the concave-convex pattern of the substrate,

The light emitting structure may include a first conductive semiconductor layer having a concave-convex structure on the semiconductor layer on the concave-convex surface; An active layer formed on the first conductive semiconductor layer with an uneven structure; A semiconductor light emitting device comprising a second conductive semiconductor layer formed of a concave-convex structure on the active layer.

The method according to claim 1,

And a second electrode formed on the first conductive semiconductor layer and a second electrode formed on the second conductive semiconductor layer.

The method according to claim 1,

The mask pattern is a semiconductor light emitting device is selectively formed from SiO ₂ , SiO _x , SiN ₂ , SiN _x , SiO _x N _y or a metal material.

The method according to claim 1,

The uneven surface semiconductor layer includes at least one of GaN, InN, AlN, InGaN, AlGaN or InAlGaN.

The method according to claim 1,

The semiconductor layer on the uneven surface is a first semiconductor layer grown between the mask pattern on the substrate, and a second semiconductor grown on the first semiconductor layer and the mask pattern, the surface of which is formed with an inverted polygonal horn or an inverted pyramid structure. A semiconductor light emitting device comprising a layer.

6. The method of claim 5,

The first semiconductor layer is a semiconductor light emitting device having a triangular cross-sectional shape having an inclined structure.

The method according to any one of claims 1 to 6,

And a buffer layer disposed between the substrate and the semiconductor layer on the uneven surface.

The method according to any one of claims 1 to 6,

The substrate is a semiconductor light emitting device selected from the group consisting of Al ₂ O ₃ , GaN, SiC, ZnO, Si, GaP, InP or GaAs.

The method according to any one of claims 1 to 6,

The through-potential density of the semiconductor layer on the uneven surface is a × 10 ⁷ / cm ² or less, and wherein 0 <a ≦ 10.

The method according to any one of claims 1 to 6,

The recessed depth of the semiconductor layer on the uneven surface is 0 <depth <10um,

The period between the yaw or iron is 0 <period <20um semiconductor light emitting device.

5. The method according to any one of claims 1 to 4,

The semiconductor layer of the uneven surface is a semiconductor light emitting device which is an undoped semiconductor layer doped with dopant.

The method according to any one of claims 1 to 6,

Each layer of the light emitting structure comprises a plane or interface (0001) perpendicular to the c-axis [0001] of the compound semiconductor, and an inclined surface inclined from the c-axis [0001],

And a concave region of the concave-convex structure of each layer is larger than the iron region.

The method according to any one of claims 1 to 6,

The first conductive semiconductor layer is at least one n-type semiconductor layer,

The second conductive semiconductor layer is at least one p-type semiconductor layer,

The active layer is a semiconductor light emitting device consisting of a single or multiple quantum well structure.

The method according to claim 1,

A semiconductor light emitting device comprising a conductive support substrate or a third conductive semiconductor layer formed on the second conductive semiconductor layer.

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