KR20140090472A - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides an array substrate and a method of fabricating the same. The array substrate includes a first buffer layer made of an inorganic insulation material on the entire surface of a substrate in which a pixel region including a device region is defined; a second buffer layer formed on the first buffer layer out of metal oxide representing insulation characteristics; an oxide semiconductor layer formed on the second buffer layer and including an active region in one island form and a conductive source region and a conductive drain region formed at both sides of the active region; a gate insulation layer and a gate electrode sequentially laminated on the oxide semiconductor layer corresponding to the active region; an interlayer insulation layer formed on the entire surface of the gate electrode and having semiconductor layer contact holes exposing the source region and the drain region, respectively; and a source electrode and a drain electrode making contact with the source region and the drain region of the oxide semiconductor layer, respectively, through the semiconductor layer contact holes over the interlayer insulation layer while being spaced apart from each other.

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

The present invention relates to an array substrate and more particularly to a semiconductor device having an oxide semiconductor layer excellent in device characteristics and stability and suppressing the generation of voids in the buffer layer located on the main surface thereof at the oxide semiconductor layer boundary, To an array substrate capable of minimizing the area of a thin film transistor and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In such a liquid crystal display device and an organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is essentially constituted in order to on / off each pixel region in common.

1 is a cross-sectional view of a portion of a conventional array substrate where one pixel region is cut including a thin film transistor.

As shown in the figure, in the element region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a plurality of data wirings 33 are defined in the array substrate 11, gate electrodes 15 are formed.

A gate insulating layer 18 is formed on the entire surface of the gate electrode 15 and sequentially formed thereon an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon. (28) are formed.

A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15.

At this time, the gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the element region TrA constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45.

The active layer 22 of the pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the element region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed.

The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method, and the difference in thickness (t1? T2) of the active layer 22, more precisely the source and drain The thickness of the exposed portion between the electrodes 36 and 38 is reduced, thereby deteriorating the characteristics of the thin film transistor Tr.

Therefore, recently, as shown in Fig. 2 (a cross-sectional view of one pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer), an oxide semiconductor material is used instead of an ohmic contact layer A thin film transistor having a single-layer structure of the oxide semiconductor layer 63 has been developed.

Since the thin film transistor OTr having the oxide semiconductor layer 63 does not need to form a separate ohmic contact layer on the oxide semiconductor layer 63, the conventional semiconductor layer (28 in FIG. 1) made of amorphous silicon, Since it is not necessary to be exposed to the dry etching proceeding to form mutually spaced ohmic contact layers (26 in FIG. 1) made of an impurity amorphous silicon of a similar material as in the array substrate (11 in FIG. 1) It is possible to prevent deterioration of the characteristics of the transistor OTr.

Further, since the oxide semiconductor layer 63 has a carrier mobility characteristic of a semiconductor layer of amorphous silicon (28 in FIG. 1) by a factor of a few to several tens of times, the oxide semiconductor layer 63 is more advantageous to operate as a driving thin film transistor.

In the thin film transistor OTr having the oxide semiconductor layer 63, a coplanar structure in which the oxide semiconductor layer 63 is located at the bottom is mainly used.

Since the thin film transistor OTr having a coplanar structure is smaller than that of the bottom gate structure in which the gate electrode is formed at the bottom of the thin film transistor OTr itself, A thin film transistor of a coplanar structure is mainly used as an array substrate for an organic electroluminescent element in which a thin film transistor is provided.

On the other hand, in the array substrate 61 having the coplanar structure OTr having the oxide semiconductor layer 63 described above, the oxide semiconductor layer 63 is located at the bottom and the substrate 100 A buffer layer 63 made of an inorganic insulating material is formed on the substrate 61 in order to prevent deterioration of the characteristics of the oxide semiconductor layer 63 due to alkali ions which may be generated from the substrate 61 constituting the base by exposure to about 300 [ And the oxide semiconductor layer 63 is formed thereon.

In the case of the array substrate 61 having the conventional oxide semiconductor layer 63 having such a structural feature, the step of forming the gate insulating film 66 on the oxide semiconductor layer 63 and the step of forming the gate electrode 69 outside The buffer layer 62 made of the same inorganic insulating material as that of the gate insulating film 66 is damaged or damaged during the conducting process for the oxide semiconductor layer portions 63b and 63c exposed to the oxide semiconductor layer A large step is generated at a boundary between the oxide semiconductor layer 63 and the oxide semiconductor layer 63 or an excessive angle is generated to cause the buffer layer 62 to have an inverted tapered shape under the oxide semiconductor layer 63.

When the buffer layer 62 generates a step at the boundary of the oxide semiconductor layer 63 or forms a reverse tapered shape, the buffer layer 62 is etched together when the interlayer insulating layer 72 made of an inorganic insulating material is formed A void is formed at the boundary of the oxide semiconductor layer 63 and the step coverage of the interlayer insulating film 72 is deteriorated by the generation of the voids to cause the source electrode 76 and the drain electrode 77 formed on the interlayer insulating film 72, Or the etching solution penetrates when the gate wiring (not shown) is patterned to cause a problem that the oxide semiconductor layer 63 itself or the gate wiring (not shown) is damaged.

The interlayer insulating layer 72 is provided with a semiconductor layer contact hole 74 for exposing the conductive regions 63b and 63c of the oxide semiconductor layer 63. The semiconductor layer contact hole 74, When the semiconductor layer contact hole 74 is deviated from the conductive portion 63b of the oxide semiconductor layer 63 due to a process error in the process of forming the oxide semiconductor layer 63, 63 or the buffer layer 62 is inversely tapered to the bottom of the oxide semiconductor layer 63.

Therefore, the oxide semiconductor layer 63 is formed sufficiently wide in consideration of the process margin in order to suppress such a problem, so that the semiconductor layer contact holes 74 are formed in the conductive regions 63b and 63c of the oxide semiconductor layer As shown in FIG.

However, when the oxide semiconductor layer 63 is formed sufficiently wide, the area of the thin film transistor OTr including the oxide semiconductor layer 63 is increased.

In the case of an array substrate for a liquid crystal display device, since only one thin film transistor is provided in each pixel region P, the array substrate for an organic electroluminescent device is improved in display quality A driving thin film transistor and a thin film transistor for compensating at least two currents are further required in each pixel region P for the sake of simplicity.

Therefore, since a plurality of thin film transistors must be formed in one pixel region, if the area of the thin film transistor is increased, the degree of freedom of design is reduced and the aperture ratio is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can suppress the occurrence of a step or a short circuit between a source electrode and a drain electrode, And an object of the present invention is to provide an array substrate including a thin film transistor capable of reducing an area and a manufacturing method thereof.

According to an aspect of the present invention, there is provided an array substrate comprising: a first buffer layer made of an inorganic insulating material formed on a front surface of a substrate on which a pixel region including an element region is defined; A second buffer layer formed on the first buffer layer and made of a metal oxide having an insulating property; An oxide semiconductor layer formed on the second buffer layer, the oxide semiconductor layer including an island region in the element region and an active region and a source region and a drain region which are formed on both sides of the active region; A gate insulating film and a gate electrode sequentially formed on the oxide semiconductor layer in correspondence with the active region; An interlayer insulating film formed on the gate electrode and having a semiconductor layer contact hole exposing the source region and the drain region, respectively; And source and drain electrodes formed in contact with the source region and the drain region provided on the oxide semiconductor layer through the semiconductor layer contact hole over the interlayer insulating film and spaced apart from each other.

At this time, the inorganic insulating material is silicon oxide (SiO ₂ ) or silicon nitride (SiN x), and the metal oxide is aluminum oxide (AlO x).

In addition, the oxide semiconductor layer may be in the form of a bar having the same width, or the active region may have a first width and the ends of the source region and the drain region located on both sides of the active region may have a width And has a second width smaller than the first width.

The semiconductor layer contact holes are formed by exposing the second buffer layer located at one end of the source region and the second buffer layer located at the periphery of the one end of the second buffer layer and the drain region, And the gate insulating film and the interlayer insulating film are made of the inorganic insulating material.

A gate wiring formed in the boundary of the pixel region on the second buffer layer so as to extend in one direction via the gate insulating film; A data line formed on the interlayer insulating film so as to cross the gate line at a boundary of the pixel region; And a drain contact hole formed over the source electrode and the drain electrode, the drain contact hole exposing the drain electrode; And a pixel electrode formed in contact with the drain electrode through the drain contact hole in each pixel region on the protective layer.

The oxide semiconductor layer is formed of any one of IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), and ZIO (Zinc Indium Oxide).

A method of manufacturing an array substrate according to an embodiment of the present invention includes: forming a first buffer layer made of an inorganic insulating material on a front surface of a substrate on which pixel regions including an element region are defined; Forming a second buffer layer made of a metal oxide having an insulating property on the first buffer layer; Forming an oxide semiconductor layer on the device region over the second buffer layer; Forming a gate insulating layer and a gate electrode on the oxide semiconductor layer sequentially stacked on the center of the oxide semiconductor layer; The oxide semiconductor layer exposed outside the gate electrode is made conductive to form a source region and a drain region; Forming an interlayer insulating film having a semiconductor layer contact hole exposing the source region and the drain region, respectively, over the gate electrode; And forming a source electrode and a drain electrode spaced apart from each other and contacting the source region and the drain region provided in the oxide semiconductor layer through the semiconductor layer contact hole over the interlayer insulating film.

The step of forming the second buffer layer made of a metal oxide having an insulating property on the first buffer layer may include depositing a metal material having an insulating property on the entire surface of the first buffer layer to form a buffer metal layer having a first thickness, ; ≪ / RTI > And annealing the substrate on which the buffer metal layer is formed to oxidize the buffer metal layer, wherein the first thickness is 10 to 50 Å.

The forming of the second buffer layer made of a metal oxide having an insulating property on the first buffer layer may include RF sputtering on the substrate on which the first buffer layer is formed to form a metal oxide having a second thickness, And forming the second buffer layer by depositing the first buffer layer, wherein the second thickness is 10 to 300 ANGSTROM.

The metal oxide is preferably aluminum oxide (AlOx).

The oxide semiconductor layer may be formed to have a bar shape having the same width or the active region may have a first width and an end of each of the source region and the drain region located on both sides of the active region may have a first width, And has a second width smaller than the width.

At this time, the semiconductor layer contact holes are formed to expose the second buffer layer located at one end of the source region and the second buffer layer located at the periphery of the one end of the second buffer layer and the drain region, respectively, to be.

And the gate insulating film and the interlayer insulating film are made of the inorganic insulating material.

The forming of the gate insulating layer and the gate electrode may include forming a gate wiring extending in one direction through the gate insulating film on the boundary of the pixel region on the second buffer layer, Forming a data line crossing the gate line on the boundary of the pixel region on the interlayer insulating layer, wherein a drain contact hole exposing the drain electrode over the source electrode and the drain electrode, To form a protective layer having a protective layer; And forming a pixel electrode in each pixel region on the protective layer, the pixel electrode being in contact with the drain electrode through the drain contact hole.

Even when a process error occurs, the area of the oxide semiconductor layer is formed to be sufficiently large by reflecting the error margin so that the contact hole of the semiconductor layer provided in the interlayer insulating film completely overlaps the source region or the drain region of the oxide semiconductor layer It is possible to reduce the area of the thin film transistor compared to the conventional array substrate by forming the oxide semiconductor layer without a margin reflecting such a process error, thereby increasing the aperture ratio of each pixel region.

Further, since the buffer layer is not affected by dry etching at the time of patterning the gate insulating film and the interlayer insulating film, the step of the buffer layer located at the boundary of the oxide semiconductor layer is widened or the erosion of the gate wiring or the oxide semiconductor layer due to the formation of voids, And short-circuiting of the drain electrode are prevented at the source.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional array substrate including a pixel region including a thin film transistor. FIG.
2 is a cross-sectional view of a pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer.
3 is a sectional view of one pixel region including a thin film transistor in an array substrate according to an embodiment of the present invention;
4 is a plan view showing an element region of an array substrate according to an embodiment of the present invention and an element region of an array substrate including a thin film transistor having a conventional oxide semiconductor layer as a comparative example.
5A to 5J are cross-sectional views illustrating steps of manufacturing an array substrate including a thin film transistor having an oxide semiconductor layer of a coplanar structure according to an embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3 is a cross-sectional view of one pixel region including a thin film transistor in an array substrate according to an embodiment of the present invention. For convenience of description, a region where the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

The array substrate 101 according to the embodiment of the present invention is formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of a transparent insulating substrate 101 made of glass or plastic, A first buffer layer 102 is formed on the first buffer layer 102 and a second buffer layer 104 made of a metal oxide such as aluminum oxide (AlOx) having a thickness of about 10 Å to 300 Å and an insulation property is formed on the first buffer layer 102, As shown in Fig.

At this time, the first buffer layer 102 made of silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is an alkali ion, for example, potassium ions (K +), sodium Ion (Na +) or the like may be eluted to the outside of the substrate 101 when heat is applied during the course of a unit process for forming a constituent element of the thin film transistor Tr. The film quality characteristic of the oxide semiconductor layer Is prevented from being lowered.

Thus the alkali ion is eluted from the substrate 101 can be most effectively inhibited by the inorganic insulating material of silicon oxide (SiO ₂₎ or silicon nitride (SiNx), the first buffer layer 102 is a silicon oxide (SiO ₂₎ Or silicon nitride (SiNx).

The second buffer layer 104 made of a metal oxide is etched by being affected by the first buffer layer 102 made of the same material when patterning the gate insulating layer 110 and the interlayer insulating layer 125 to be formed later .

In the case of the array substrate 101 according to the embodiment of the present invention, the second buffer layer 104 made of a metal oxide having an insulating property is formed, and a gate insulating layer 110 made of an inorganic insulating material and an interlayer insulating layer 125 ) Problems such as an increase in the level difference caused by etching together with the patterning or formation of voids around the oxide semiconductor layer 106 can be originally suppressed.

This isolation of the inorganic insulating material is silicon oxide (SiO ₂₎ or silicon nitride (SiNx) material layer is the patterned to the desired shape, proceed to the ordinary dry etching, silicon (SiO ₂₎ or silicon nitride (SiNx) material such oxidation In the case of the insulating layer, dry etching is carried out using a reaction gas such as CF ₄ , CF ₃ , CF ₂ or the like. In this reaction gas, the metal oxide does not react at all, and further, And no reaction occurs.

 On the other hand, on the second buffer layer 104 made of a metal oxide, each element region TrA is provided with an active region 106a which is not subjected to a conductorization process corresponding to the central portion, that is, the portion where the gate electrode 115 is formed And an oxide semiconductor layer 106 composed of a source region 106b and a drain region 106c, which are each formed into a conductor and processed on both sides of the active region 106a.

At this time, the oxide semiconductor layer 106 may have a bar shape having a constant width. In order to further reduce the area of the thin film transistor Tr, the oxide semiconductor layer 106 has a width at both ends thereof, The width may be smaller than the width.

The oxide semiconductor layer 106 having such a structure is characterized by being made of any one of oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), and ZIO (Zinc Indium Oxide).

Such an oxide semiconductor material is characterized in that the conductive characteristic is improved by a plasma process in a reaction atmosphere containing a specific reactive gas such as helium (He) or argon (Ar), which is an inert gas.

Next, on the active region 106a of the oxide semiconductor layer 106 including the active region 106a and the source region 106b and the drain region 106c which are made conductive, an inorganic insulating material such as an oxide silicon (SiO ₂₎ or silicon nitride gate insulating film 110 made of (SiNx) with a low-resistance metallic material, for example aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and molybdenum A gate electrode 115 made of one or two or more materials of a metal alloy (MoTi) is formed.

In addition, a gate insulating film 110 made of the inorganic insulating material and a gate wiring (not shown) made of the low-resistance metal material are formed on the second buffer layer 104, Not shown) are formed.

At this time, the gate insulating layer 110 is formed in the same plane shape as the gate electrode 115 and the gate wiring (not shown) located on the gate insulating layer 110.

This is because the gate insulating film 110, the gate electrode 115, and the gate wiring (not shown) are patterned by the same mask process.

When the array substrate 101 is an array substrate for a liquid crystal display, the gate electrode 115 and the gate wiring (not shown) are connected to each other. In the case of an array substrate for an organic electroluminescent device, The gate line (not shown) is connected to the gate electrode 115 of the switching thin-film transistor, and the other thin-film transistor is formed for compensating the current. And is not connected to the gate electrode 115.

Next, an interlayer insulating film 125 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 over the gate wiring (not shown) and the gate electrode 115 .

A semiconductor layer contact hole 128 exposing the source region 106b and the drain region 106c located on both sides of the active region 106a of each of the oxide semiconductor layers 106 is formed in the interlayer insulating layer 125, .

At this time, the semiconductor layer contact hole 128 provided in the interlayer insulating film 125 is shifted to the outside of the source region 106b or the drain region 106c by a process error, so that a part of the second buffer layer 104 is exposed The array substrate 101 according to the embodiment of the present invention has a problem that the semiconductor layer contact hole 128 completely deviates from the source region 106b or the drain region 106c It does not.

When the semiconductor layer contact hole 128 is formed in the interlayer insulating film 125 made of an inorganic insulating material, the second buffer layer 104 has no influence at all and therefore voids are formed at the boundary of the oxide semiconductor layer 106 Or the problem of increasing the level difference between the oxide semiconductor layer 106 and the oxide semiconductor layer 106 does not occur.

Therefore, in the case of the array substrate 101 according to the embodiment of the present invention, even if a process error occurs in the area of the oxide semiconductor layer 106, the semiconductor layer contact hole 128 provided in the interlayer insulating film 125 It is not necessary to form the oxide semiconductor layer 106 sufficiently large enough to completely overlap the source region 106b or the drain region 106c of the oxide semiconductor layer 106. Thus, by forming the oxide semiconductor layer 106 without a margin reflecting such a process error, It is possible to reduce the area of the thin film transistor Tr relative to the substrate 61 (FIG. 2).

Since the portion where the thin film transistor Tr is formed in each pixel region P is a non-opening region, if the area of the thin film transistor Tr is reduced, the aperture ratio of each pixel region P is increased.

Since the second buffer layer 104 is not affected by dry etching at the time of patterning the gate insulating layer 110 and the interlayer insulating layer 125, the step of the second buffer layer 104 located at the boundary of the oxide semiconductor layer 106 (Not shown) or the erosion of the oxide semiconductor layer 106, short circuit of the source electrode 133 and the drain electrode 136, or the like due to enlargement of the source electrode 133 or formation of voids.

 On the other hand, a low resistance metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, molybdenum (Mo), or the like is formed on the interlayer insulating film 125 having the semiconductor layer contact hole 128. ) And a molybdenum alloy (MoTi), and a data line (not shown) is formed which intersects with the gate line (not shown) to define the pixel region P.

A source electrode 133 is formed in the device region TrA in contact with the source region 106b of the oxide semiconductor layer 106 through the semiconductor layer contact hole 128. The source electrode 133 And the drain electrode 136 is formed in contact with the drain region 106c of the oxide semiconductor layer 106 through the semiconductor layer contact hole 128. [

At this time, the source electrode 133 may be connected to the data line (not shown) or may be formed separately.

That is, although the data line (not shown) is formed to be connected to the source electrode 133 when the array substrate 101 is an array substrate for a liquid crystal display device, In the case of a substrate, it is formed to be connected to the source electrode of the switching thin film transistor, and is not connected to the source electrode of the driving thin film transistor or the source electrode of the thin film transistor formed for current compensation.

On the other hand, an oxide semiconductor layer 106, a gate insulating film 110, a gate electrode 115, and an interlayer insulating film 125 provided with a semiconductor layer contact hole 128, which are sequentially stacked in each device region TrA, And the source electrode 133 and the drain electrode 136 which are spaced apart from each other constitute a thin film transistor Tr.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or an organic insulating material such as benzocyclobutene (BCB) is formed on the entire surface of the substrate 101 over the thin film transistor Tr. And a protective layer 140 made of a photo-acryl.

At this time, the passivation layer 140 is provided with a drain contact hole 143 for exposing the drain electrode 136 of the thin film transistor Tr.

When the drain contact hole 143 and the array substrate 101 are an array substrate for an organic electroluminescent device, the drain contact hole 143 is not necessarily formed to expose the drain electrodes of all the thin film transistors, And the drain contact hole 143 is omitted for the switching thin film transistor or the drain electrode of the auxiliary thin film transistor for current compensation.

On the other hand, the pixel electrode 150 is formed in each pixel region P by making contact with the drain electrode 136 through the drain contact hole 143 on the passivation layer 140 provided with the drain contact hole 143, .

4 is a plan view showing an element region of an array substrate according to an embodiment of the present invention and a device region of an array substrate including a conventional thin film transistor having a conventional oxide semiconductor layer as a comparative example.

In the case of the array substrate 101 according to the embodiment of the present invention, for example, the oxide semiconductor layer 106 does not have a constant width, and the width of the portion constituting the source region 106b and the drain region 106c is greater than the width of the center portion And the semiconductor layer contact hole 128 provided in the interlayer insulating film 125 includes the source region 106b and the drain region 106c and is exposed to the outside.

However, in the case of an array substrate having a thin film transistor having a conventional oxide semiconductor layer 63, which is a comparative example, the oxide semiconductor layer 63 is formed such that the active region 63a and the source and drain regions 63b and 63c have the same width And the semiconductor layer contact hole 74 provided in the interlayer insulating film (not shown) is formed so as to completely overlap the source region 63b and the drain region 63c of the oxide semiconductor layer 663 .

This is because when the semiconductor layer contact hole 74 is formed by shifting to the outside of the oxide semiconductor layer 63, a short or the like of the source electrode 76 or the drain electrode 77 is generated in the buffer layer (not shown) The width of the oxide semiconductor layer 63 is set to be greater than the width of the semiconductor layer 63 so as to completely overlap the oxide semiconductor layer 63 even if a process error occurs in the semiconductor layer contact hole 74. [ It should be formed to be sufficiently larger than the area of the contact hole 74.

Therefore, the area of the thin film transistor Tr included in the array substrate 101 according to the embodiment of the present invention is formed to be compact in comparison with the area of the thin film transistor OTr provided in the conventional array substrate 61 .

Hereinafter, a method of manufacturing an array substrate according to an embodiment of the present invention having the above-described configuration will be described.

5A to 5J are cross-sectional views illustrating an array substrate including a thin film transistor having an oxide semiconductor layer 106 of a coplanar structure according to an embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

5A, an inorganic insulating material such as silicon nitride is deposited on the entire surface of a transparent insulating substrate 101, for example, a substrate 101 made of glass or plastic to form a first buffer layer 102 .

Next, as shown in FIG. 5B, a metal material having an insulating property, for example, aluminum (Al) is deposited on the first buffer layer 102 to have a thickness of about 10 Å to 50 Å, thereby forming a first metal layer 103 ).

5C, the substrate 101 on which the first metal layer 103 is formed is placed in an oven or furnace, for example, in a heat treatment apparatus, and then subjected to a heat treatment, The entirety of the metal layer 103 (FIG. 5B) is oxidized to form aluminum oxide (AlOx), for example, a metal oxide having an insulating property, thereby forming a second buffer layer 104.

On the other hand, the first metal layer (103 in FIG. 5B) has a thickness of about 10 to 50 angstroms because the first metal layer (103 in FIG. 5B) So as to form a layer.

That is, if the first metal layer (103 in FIG. 5B) has a thickness greater than 50 ANGSTROM, it takes too much time to be oxidized by the heat treatment process, resulting in a decrease in productivity per unit time, Since the entirety of the first metal layer (103 of FIG. 5B) does not form a metal oxide having an insulating characteristic but partially has a metal characteristic, it is formed to have a thickness of about 50 ANGSTROM to suppress it.

5B) is set to about 10 angstroms, the thickness of the first metal layer (103 of FIG. 5B) is set to about 10 angstroms because of the thickness error of the first metal layer (103 of FIG. 5B) (103 in FIG. 5B) is not formed.

Meanwhile, in the embodiment of the present invention, the second buffer layer 104 made of the metal oxide is formed by forming the first metal layer (103 in FIG. 5B) and performing the heat treatment to oxidize it. The second buffer layer 104 made of aluminum oxide (AlOx) may be formed without performing heat treatment by performing RF (Radio Frequency) sputtering in the state where the first buffer layer 102 is formed.

The thickness of the second buffer layer 104 made of a metal oxide material formed by the RF sputtering process is preferably about 10 to 300 ANGSTROM.

In the embodiment of the present invention, since the portion of the first metal layer (103 in FIG. 5B) is not oxidized after the heat treatment is performed, the thickness of the first metal layer is reduced to 50 ANGSTROM or less. However, When the second buffer layer 104 made of an oxide is formed, it is not a problem even if it is thicker than 50 ANGSTROM.

5D, an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or zirconium oxide (ZIO) is deposited on the second buffer layer 104. Then, An oxide semiconductor material layer (not shown) is formed on the entire surface of the substrate 101.

Thereafter, the oxide semiconductor material layer (not shown) is subjected to a photolithography process including a photolithographic process such as a photoresist application, exposure using an exposure mask, development of an exposed photoresist, etching using photoresist remaining after development, The mask process is performed and patterned to form an island-shaped oxide semiconductor layer 106 corresponding to each device region TrA.

At this time, the oxide semiconductor layer 106 may have a bar shape having the same width in each device region TrA, or the center portion may have a first width and both side ends may have a width smaller than the first width. And may have a width of 2 mm.

In order to reduce the area of the thin film transistor (Tr in FIG. 5J), it is more preferable that the oxide semiconductor layer 106 has a first width and a second width at both ends of the oxide semiconductor layer 106 Do.

Next, as shown in FIG. 5e, the oxide semiconductor layer 106 over the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx), a vapor-deposited on the front and forming a gate insulating material layer, continuous (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and molybdenum alloy (MoTi) on the gate insulating material layer And then a second metal layer (not shown) is formed.

Thereafter, the second metal layer (not shown) and the gate insulating material layer (not shown) located under the second metal layer (not shown) are patterned by performing a masking process so that the oxide semiconductor layer 106 The gate insulating film 110 and the gate electrode 115 are sequentially formed corresponding to the central portion and the gate wiring 115 connected to the gate electrode 115 is formed over the second buffer layer 104 in one direction, ).

At this time, the gate insulating layer 110 is formed under the gate wiring (not shown) in the same plane shape as the gate wiring (not shown).

The second metal layer (not shown) is wet-etched using a second metal layer (not shown) and an etchant of a metal material to form a gate insulating material layer (not shown) (Not shown) and the gate electrode 115 are formed on the gate electrode 115 and then the gate electrode 115 and the gate insulating material layer (not shown) exposed to the outside of the gate electrode 115 (Not shown) is removed to expose a portion of the oxide semiconductor layer 106 and the second buffer layer 104, thereby forming the gate insulating layer 110.

At this time, in the process of patterning the gate insulating film 110 made of the inorganic insulating material by dry etching in the characteristics of the array substrate 101 according to the embodiment of the present invention, the second buffer layer 104 is etched by the drain etching The second buffer layer 104 made of a metal oxide is not affected by the drain etching as described above so that the second buffer layer 104 is etched at the boundary of the oxide semiconductor layer 106, A phenomenon that a large step is formed or a gap is formed is prevented at the source.

Next, as shown in FIG. 5F, an inert gas such as argon (Ar) or helium (He) is used as a reaction gas for the substrate 101 on which the gate wiring (not shown) and the gate electrode 115 are formed The source region 106b and the drain region 106c are formed by applying a conductive property to the oxide semiconductor layer 106 exposed to the outside of the gate electrode 115 by performing a plasma process.

The gate insulating layer 110 and the gate electrode 115 are formed so that the oxide semiconductor layer 106 region not exposed to the plasma forms an active region 106a in which a channel is formed.

5G, an example of an inorganic insulating material is formed on the entire surface of the substrate 101 on which the oxide semiconductor layer 106 formed with the source region 106b and the drain region 106c formed with the conductive characteristics is formed. (SiO ₂ ) or silicon nitride (SiN x) is deposited to form an interlayer insulating film 125.

Thereafter, the masking process is performed on the interlayer insulating film 125 to pattern the source and drain regions 106b and 106c on both sides of the gate electrode 115 in each device region TrA, Thereby forming a semiconductor layer contact hole 128 to be exposed.

The semiconductor layer contact hole 128 formed in the interlayer insulating film 125 may be formed to completely overlap the source region 106b and the drain region 106c on the characteristics of the array substrate 101 according to the embodiment of the present invention And the source region 106b and the drain region 106c may be formed so as to be respectively exposed so as to completely overlap with the source region 106b or the drain region 106c, It is not a problem whether or not the battery 104 is exposed.

In the drawing, one end of each of the source region 106b and the drain region 106c and the surface of the second buffer layer 104 adjacent to the source region 106b and the drain region 106c are exposed at the same time.

5H, a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and a molybdenum alloy (MoTi) on the entire surface to form a third metal layer (not shown).

Thereafter, the third metal layer (not shown) is patterned by a mask process to form source regions 106b of the oxide semiconductor layer 106 through the semiconductor layer contact holes 128 in the device regions TrA, Drain regions 136 are formed on the interlayer insulating film 125. A source electrode 133 and a drain electrode 136 which are in contact with the drain region 106c and are spaced apart from each other are formed on the interlayer insulating film 125. At the same time, (Not shown) is defined.

Next, as shown in FIG. 5I, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the source electrode 133 and the drain electrode 136 and the data line (not shown) Or a protective layer 140 is formed on the entire surface of the substrate 101 by applying an organic insulating material such as benzocyclobutene or photoacrylic.

Thereafter, a mask process is performed on the passivation layer 140 and patterned to form a drain contact hole 143 exposing the drain electrode 136 in each device region TrA.

Next, as shown in FIG. 5J, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the protective layer 140 provided with the drain contact hole 143 And a masking process is performed to pattern the transparent conductive material layer (not shown), thereby forming a pixel electrode P in contact with the drain electrode 136 through the drain contact hole 143, Thereby completing the array substrate 101 according to the embodiment of the present invention.

In the case of the array substrate 101 according to the embodiment of the present invention manufactured as described above, even if a process error occurs, the semiconductor layer contact hole 128 provided in the interlayer insulating film 125 is formed in the oxide semiconductor layer 106, It is not necessary to sufficiently increase the area of the oxide semiconductor layer 106 to reflect the error margin so as to completely overlap the source region 106b or the drain region 106c of the oxide semiconductor layer 106. Therefore, The area of the thin film transistor Tr compared to the conventional array substrate 61 (FIG. 2) can be reduced, thereby increasing the aperture ratio of each pixel region P.

In addition, since the second buffer layer 104 is not affected by dry etching at the time of patterning the gate insulating film 110 and the interlayer insulating film 125, the step of the second buffer layer 104 located at the boundary of the oxide semiconductor layer 106 The gate wiring (not shown) or the erosion of the oxide semiconductor layer 106, the shorting of the source electrode 133 and the drain electrode 136, etc., are prevented originally from being enlarged or formed with voids.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: (Array) substrate
102: first buffer layer
104: second buffer layer
106: oxide semiconductor layer
106a: active area
106b and 106c: a source region and a drain region
110: gate insulating film
115: gate electrode
125: interlayer insulating film
128: semiconductor layer contact hole
133: source electrode
136: drain electrode
140: Protective layer
143: drain contact hole
150: pixel electrode
P: pixel area
Tr: thin film transistor
TrA: device region

Claims (17)

A first buffer layer made of an inorganic insulating material formed on a front surface of a substrate on which a pixel region including an element region is defined;
A second buffer layer formed on the first buffer layer and made of a metal oxide having an insulating property;
An oxide semiconductor layer formed on the second buffer layer, the oxide semiconductor layer including an island region in the element region and an active region and a source region and a drain region which are formed on both sides of the active region;
A gate insulating film and a gate electrode sequentially formed on the oxide semiconductor layer in correspondence with the active region;
An interlayer insulating film formed on the gate electrode and having a semiconductor layer contact hole exposing the source region and the drain region, respectively;
And a source electrode and a drain electrode formed in contact with the source region and the drain region provided on the oxide semiconductor layer through the semiconductor layer contact hole over the interlayer insulating film,
≪ / RTI >
The method according to claim 1,
The inorganic insulating material is silicon oxide (SiO ₂₎ or silicon nitride (SiNx),
Wherein the metal oxide is aluminum oxide (AlOx).
The method according to claim 1,
Wherein the oxide semiconductor layer is in the form of a bar having the same width or the active region has a first width and the ends of the source region and the drain region located on both sides thereof have a width smaller than the first width The second width being greater than the second width.
The method of claim 3,
And the semiconductor layer contact holes are formed to expose the second buffer layer located at one end of the source region and the second buffer layer located at the periphery of the one end of the drain region and the periphery of the second buffer layer, respectively.
5. The method of claim 4,
Wherein the gate insulating film and the interlayer insulating film are made of the inorganic insulating material.
The method according to claim 1,
A gate wiring formed on the boundary of the pixel region on the second buffer layer so as to extend in one direction via the gate insulating film;
A data line formed on the interlayer insulating film so as to cross the gate line at a boundary of the pixel region;
And a drain contact hole formed over the source electrode and the drain electrode, the drain contact hole exposing the drain electrode;
A pixel electrode formed in contact with the drain electrode through the drain contact hole,
≪ / RTI >
The method according to claim 1,
Wherein the oxide semiconductor layer is formed of any one selected from the group consisting of Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), and Zinc Indium Oxide (ZIO).
Forming a first buffer layer made of an inorganic insulating material on an entire surface of a substrate on which a pixel region including an element region is defined;
Forming a second buffer layer made of a metal oxide having an insulating property on the first buffer layer;
Forming an oxide semiconductor layer on the device region over the second buffer layer;
Forming a gate insulating layer and a gate electrode on the oxide semiconductor layer sequentially stacked on the center of the oxide semiconductor layer;
The oxide semiconductor layer exposed outside the gate electrode is made conductive to form a source region and a drain region;
Forming an interlayer insulating film having a semiconductor layer contact hole exposing the source region and the drain region, respectively, over the gate electrode;
Forming a source electrode and a drain electrode in contact with the source region and the drain region provided on the oxide semiconductor layer through the semiconductor layer contact hole on the interlayer insulating film and spaced apart from each other,
Wherein the substrate is a substrate.
9. The method of claim 8,
Wherein forming the second buffer layer made of a metal oxide having an insulating property over the first buffer layer comprises:
Depositing a metal material having an insulating property on the entire surface to form a buffer metal layer having a first thickness when oxidized onto the first buffer layer;
Performing a heat treatment on the substrate on which the buffer metal layer is formed to oxidize the buffer metal layer
Wherein the substrate is a substrate.
10. The method of claim 9,
Wherein the first thickness is 10 to 50 ANGSTROM.
9. The method of claim 8,
Wherein forming the second buffer layer made of a metal oxide having an insulating property over the first buffer layer comprises:
Performing RF (Radio Frequency) sputtering on the substrate on which the first buffer layer is formed to deposit a metal oxide having a second thickness to form the second buffer layer
Wherein the substrate is a substrate.
12. The method of claim 11,
And the second thickness is 10 to 300 ANGSTROM.
9. The method of claim 8,
Wherein the metal oxide is aluminum oxide (AlOx).
9. The method of claim 8,
The oxide semiconductor layer may be formed in a bar shape having the same width,
Or the active region has a first width and the ends of the source region and the drain region located on both sides of the active region have a second width smaller than the first width.
15. The method of claim 14,
And the semiconductor layer contact holes are formed so as to expose the second buffer layer located at one end of the source region and the second buffer layer located at the periphery of the one end of the drain region, / RTI >
9. The method of claim 8,
Wherein the gate insulating film and the interlayer insulating film are made of the inorganic insulating material.
9. The method of claim 8,
Wherein forming the gate insulating film and the gate electrode includes forming a gate wiring extending in one direction through the gate insulating film on the boundary of the pixel region over the second buffer layer,
The step of forming the source electrode and the drain electrode includes forming a data line crossing the gate line on the boundary of the pixel region on the interlayer insulating film,
Forming a protective layer having drain contact holes exposing the drain electrodes over the source electrode and the drain electrode;
Forming a pixel electrode on each of the pixel regions on the protective layer in contact with the drain electrode through the drain contact hole;
Wherein the substrate is a substrate.

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