KR101588447B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

A buffer layer made of an inorganic insulating material; an impurity amorphous silicon layer; a first inorganic insulating layer; a pure amorphous silicon layer; and a second inorganic insulating layer are successively laminated on a substrate on which a pixel region and a switching region are defined, ; Crystallizing the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer by performing a solid phase crystallization (SPC) process; Forming an impurity polysilicon gate electrode and a gate insulating film sequentially stacked on the buffer layer in the island shape and having the same planarity, exposing the edge of the gate insulating film over the gate insulating film, Forming an active layer of stacked pure polysilicon and an inorganic insulating pattern; Forming an insulating interlayer on the entire surface of the inorganic insulating pattern by depositing an inorganic insulating material on the entire surface of the inorganic insulating pattern; patterning the inorganic insulating pattern on the interlayer insulating layer to expose both sides of the active insulating layer, ; ≪ / RTI > A barrier pattern of pure amorphous silicon in contact with the active layer through the active contact holes and spaced apart from each other through the active interlayer insulating film; an ohmic contact layer of impurity amorphous silicon on the respective barrier patterns; Forming source and drain electrodes spaced apart from each other and simultaneously forming a data line connected to the source electrode on the boundary of the pixel region on the interlayer insulating film; Forming a first protective layer over the data line and the source and drain electrodes, patterning the first protective layer, the interlayer insulating layer, and the gate insulating layer to expose the gate electrode outside the active layer, Forming a hole; Forming a gate interconnection that contacts the gate electrode through the gate contact hole as a metal material at the boundary of the pixel region on the first protective layer and crosses the data interconnection; Forming a second passivation layer on the entire surface of the substrate over the gate wiring, forming a drain contact hole exposing the drain electrode by patterning the second passivation layer and a first passivation layer under the gate electrode; And forming a pixel electrode in the pixel region in contact with the drain electrode through the drain contact hole over the second passivation layer, wherein the solid-phase crystallization process is performed in a state where the second inorganic insulating layer is formed, Wherein a thermal oxide film is prevented from being formed at an interface between the polysilicon layer and the second inorganic insulating layer, and an array substrate manufactured by the method.

Array substrate, polysilicon, thermal oxide film, solid phase crystallization, active layer, damage

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

In particular, the present invention relates to an array substrate, and more particularly to an array substrate, which is capable of originally suppressing the occurrence of surface damage of the active layer by dry etching progression, preventing formation of a thermal oxidation film on the surface of the active layer, Layer thin film transistor array substrate and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

An active matrix liquid crystal display device including an array substrate having a thin film transistor which is a switching device capable of controlling on / off of a voltage for each pixel in a liquid crystal display device, It has the most attention because it has excellent implementation ability.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

An array substrate having a thin film transistor, which is essentially a switching element, is provided in order to commonly turn on and off each pixel region in the liquid crystal display device and the organic electroluminescent device.

FIG. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device including a pixel region including a thin film transistor.

A gate electrode 15 is formed in a switching region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a data wiring 33 are defined in the array substrate 11, And a gate insulating film 18 is formed on the entire surface of the gate electrode 15. An active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon A semiconductor layer 28 is formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 in correspondence to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method and the characteristic difference of the thin film transistor Tr occurs due to the difference in thickness (t1? T2) of the active layer 22 have.

2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate. In the figure, the gate electrode and the gate insulating film are omitted for convenience of explanation.

2A, a pure amorphous silicon layer 20 is formed on a substrate 11, and an impurity amorphous silicon layer 24 and a metal layer 30 are sequentially formed thereon. Thereafter, a photoresist layer is formed on the metal layer 30 to form a photoresist layer (not shown), exposing the photoresist layer using an exposure mask, and successively developing the photoresist layer, thereby forming a third And a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed corresponding to the spacing region between the source and drain electrodes .

Next, as shown in FIG. 2B, the metal layer (30 in FIG. 2A) exposed at the outside of the first and second photoresist patterns 91 and 92 and the impurities and the pure amorphous silicon layer 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top and an impurity amorphous silicon pattern 25 and an active layer 22 as a bottom portion.

Next, as shown in FIG. 2C, the second photoresist pattern (92 in FIG. 2B) of the fourth thickness is removed by performing ashing. In this case, the first photoresist pattern (91 of FIG. 2B) having the third thickness becomes a third photoresist pattern 93 in a reduced thickness and remains on the source drain pattern 31.

Next, as shown in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching away the source drain pattern (31 in FIG. 2C) exposed to the outside of the third photoresist pattern 93, . At this time, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, dry etching is performed on the impurity amorphous silicon pattern (25 in FIG. 2D) exposed in the spacing region between the source and drain electrodes 36 and 38, The ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38.

At this time, the dry etching is performed for a sufficiently long time to completely eliminate the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38. In this process, the impurity amorphous silicon pattern A portion of the impurity amorphous silicon pattern (25 in FIG. 2D) is etched to a predetermined thickness even to the active layer 22 located at the lower portion of the impurity-amorphous silicon pattern 25 (FIG. 2D). Therefore, in the active layer 22, there is a difference in thickness (t1? T2) between the portion where the ohmic contact layer 26 is formed on the active layer 22 and the portion where the ohmic contact layer 26 is formed. If the dry etching is not performed for a sufficiently long time, the impurity amorphous silicon pattern (25 in FIG. 2D) to be removed in the spacing region between the source and drain electrodes 36 and 38 remains on the active layer 22 This is to prevent this.

Therefore, in the above-described conventional method of manufacturing the array substrate 11, inevitably, the thickness of the active layer 22 is different, and the characteristics of the thin film transistor (Tr in FIG. 1) deteriorates.

2A) which is thick enough to form the active layer 22 in consideration of the thickness of the active layer 22 to be etched away during the dry etching for forming the ohmic contact layer 26, Must be deposited sufficiently thick so as to have a thickness of 1000 ANGSTROM or more, which results in an increase in deposition time and a decrease in productivity.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

However, in the case of a thin film transistor generally constituted in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, which is a problem in stability when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process using a laser device has been proposed.

3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate including a thin film transistor having a conventional polysilicon as a semiconductor layer, polysilicon is formed on the semiconductor layer Region 55b containing a high concentration of impurities on both sides of the first region 55a in the semiconductor layer 55 made of polysilicon or an n + the formation of a p + region (not shown) is required. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the progress of the doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment.

It is an object of the present invention to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching and the surface of the active layer is not damaged so that the characteristics of the thin film transistor are improved .

It is another object of the present invention to provide a method of manufacturing an array substrate including a thin film transistor which does not require a doping process but which can improve mobility characteristics even when the semiconductor layer is formed of polysilicon.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, including: forming a buffer layer made of an inorganic insulating material on a substrate defining a pixel region and a switching region; a first inorganic insulating layer; A pure amorphous silicon layer, and a second inorganic insulating layer; Crystallizing the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer by performing a solid phase crystallization (SPC) process; Forming an impurity polysilicon gate electrode and a gate insulating film sequentially stacked on the buffer layer in the island shape and having the same planarity, exposing the edge of the gate insulating film over the gate insulating film, Forming an active layer of stacked pure polysilicon and an inorganic insulating pattern; Forming an insulating interlayer on the entire surface of the inorganic insulating pattern by depositing an inorganic insulating material on the entire surface of the inorganic insulating pattern; patterning the inorganic insulating pattern on the interlayer insulating layer to expose both sides of the active insulating layer, ; ≪ / RTI > A barrier pattern of pure amorphous silicon in contact with the active layer through the active contact holes and spaced apart from each other through the active interlayer insulating film; an ohmic contact layer of impurity amorphous silicon on the respective barrier patterns; Forming source and drain electrodes spaced apart from each other and simultaneously forming a data line connected to the source electrode on the boundary of the pixel region on the interlayer insulating film; A gate contact hole for exposing the gate electrode to the outside of the active layer by patterning the first passivation layer, the interlayer insulating film, and the gate insulating film; forming a first passivation layer over the data line and the source and drain electrodes; ; ≪ / RTI > Forming a gate interconnection that contacts the gate electrode through the gate contact hole as a metal material at the boundary of the pixel region on the first protective layer and crosses the data interconnection; Forming a second passivation layer on the entire surface of the substrate over the gate wiring, forming a drain contact hole exposing the drain electrode by patterning the second passivation layer and a first passivation layer under the gate electrode; And forming a pixel electrode in the pixel region in contact with the drain electrode through the drain contact hole over the second passivation layer, wherein the solid-phase crystallization process is performed in a state where the second inorganic insulating layer is formed, Thereby preventing formation of a thermal oxidation film at the interface between the polysilicon layer and the second inorganic insulating layer.

A gate electrode of an impurity polysilicon layer which is sequentially stacked on the buffer layer and has the same planarity as an island shape and a gate insulating film are formed on the gate insulating film and an edge of the gate insulating film is exposed on the gate insulating film, The step of forming an active layer and an inorganic insulating pattern of successively stacked pure polysilicon includes forming a first photoresist pattern having a first thickness corresponding to a portion where the active layer is formed on the second inorganic insulating layer, Forming second and third photoresist patterns having a second thickness that is thinner than the first thickness and different in width from each other, corresponding to edges of the gate electrode exposed to the outside of the active layer; The second inorganic insulating layer exposed to the outside of the first to third photoresist patterns and the pure polysilicon layer, the first inorganic insulating layer, and the impurity polysilicon layer below the first inorganic insulating layer are sequentially removed, Forming a gate electrode of the impurity polysilicon, a gate insulating film, a pure polysilicon pattern, and an inorganic insulating material pattern having the same planarity and sequentially stacked; Exposing an edge of the inorganic insulating material pattern to the outside of the first photoresist pattern by ashing and removing the second and third photoresist patterns; Removing the inorganic insulating material pattern exposed to the outside of the first photoresist pattern and the pure polysilicon pattern thereunder to expose edges of the gate insulating film on the gate insulating film, Forming an active layer of pure polysilicon and an inorganic insulating pattern; And removing the first photoresist pattern.

The buffer layer, the impurity amorphous silicon layer, the first inorganic insulating layer, the pure amorphous silicon layer, and the second inorganic insulating layer may be continuously formed in the same vacuum chamber through a chemical vapor deposition (CVD) As shown in FIG.

In addition, the solid phase crystallization (SPC) process is preferably an alternating magnetic field crystallization using a thermal crystallization or an alternating magnetic field crystallization apparatus through a heat treatment in a temperature range of 600 ° C to 800 ° C.

In addition, the barrier pattern, the ohmic contact layer, and the source and drain electrodes are formed by patterning at the same time by performing the same mask process so that they have the same shape, the same size, and the completely overlapping shape.

The active layer of the pure polysilicon has a thickness of about 300 ANGSTROM to 1000 ANGSTROM, the inorganic insulating pattern has a thickness of about 100 ANGSTROM to 500 ANGSTROM, and the interlayer insulating film has a thickness of each of the gate electrode and the gate insulating film, It is preferable to have a thickness larger than the sum of the thicknesses.

The step of forming the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, Wherein forming the second passivation layer having the drain contact hole comprises forming a gate pad contact hole exposing the gate pad electrode and a data pad contact exposing the data pad electrode, Wherein forming the pixel electrode comprises: forming a gate auxiliary pad electrode in contact with the gate pad electrode through the gate pad contact hole; and forming a gate contact pad electrode in contact with the data pad electrode through the data pad contact hole. And forming a data-assist pad electrode on the substrate.

An array substrate according to the present invention includes: a buffer layer formed on an entire surface of a substrate on which a pixel region and a switching region are defined, the inorganic insulating material being formed; A gate electrode and a gate insulating film of polysilicon sequentially stacked on the buffer layer and having the same planar shape as the island shape; An active layer of pure polysilicon formed in an island shape to expose an edge of the gate insulating film over the gate insulating film; An inorganic insulating pattern formed on the active layer and having the same planarity as the active layer and overlapped with the active layer and serving to prevent formation of a thermal oxidation film at the interface of the active layer; An interlayer insulating layer formed on the entire surface of the substrate, the interlayer insulating layer having an active contact hole exposing the active layer over the inorganic insulating pattern and serving as an etch stopper at a central portion of the active layer; A barrier pattern of pure amorphous silicon formed in contact with the active layer and spaced apart from the active region through the active contact hole over the interlayer insulating film in the switching region; An ohmic contact layer of impurity amorphous silicon formed on the upper portion of the barrier pattern; Source and drain electrodes spaced apart from the ohmic contact layer spaced apart from each other; A data line formed on the interlayer insulating film and connected to the source electrode at a boundary of the pixel region; A first protective layer formed on the data line with a gate contact hole exposing the gate electrode outside the inorganic insulating pattern; A gate line formed in contact with the gate electrode through the gate contact hole at a boundary of the pixel region on the first passivation layer and intersecting the data line; A second passivation layer formed on the gate line and having a drain contact hole exposing the drain electrode; And a pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole over the second passivation layer.

In this case, the gate electrode of the impurity polysilicon has a thickness of 500 ANGSTROM to 1000 ANGSTROM, the active layer of the pure polysilicon has a thickness of 300 ANGSTROM to 1000 ANGSTROM, the inorganic insulating pattern has a thickness of 100 ANGSTROM to 500 ANGSTROM, Is formed to have a thickness of 50 ANGSTROM to 300 ANGSTROM and the interlayer insulating film is formed to have a thickness thicker than the sum of the thickness of each of the gate electrode and the gate insulating film located under the interlayer insulating film.

A gate pad electrode connected to an end of the gate line and a data pad electrode connected to an end of the data line, the second passivation layer having a gate pad contact hole exposing the gate pad electrode, And the first passivation layer has a data pad contact hole exposing the data pad electrode, and a gate electrode which contacts the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode over the second passivation layer, An auxiliary pad electrode, and a data assist pad electrode contacting the data pad electrode through the data pad contact hole.

According to still another embodiment of the present invention, there is provided a method of manufacturing an array substrate, comprising: forming a buffer layer made of an inorganic insulating material, a doped amorphous silicon layer, a first inorganic insulating layer, a pure amorphous silicon layer, Sequentially stacking the silicon layers; (SPC) process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer, respectively, and simultaneously form a thermal oxide film having a first thickness on the pure polysilicon layer ; ≪ / RTI > Forming an impurity polysilicon gate electrode and a gate insulating film sequentially stacked on the buffer layer in the island shape and having the same planarity, exposing the edge of the gate insulating film over the gate insulating film, Forming an active layer and a thermal oxide film pattern of stacked pure polysilicon; Forming an insulating interlayer on the entire surface of the thermal oxide film pattern by depositing an inorganic insulating material on the entire surface of the thermal oxide film pattern; patterning the interlayer insulating film and the thermal oxide film pattern thereunder to expose both sides of the active layer, ; ≪ / RTI > A barrier pattern of pure amorphous silicon in contact with the active layer through the active contact holes and spaced apart from each other through the active interlayer insulating film; an ohmic contact layer of impurity amorphous silicon on the respective barrier patterns; Forming source and drain electrodes spaced apart from each other and simultaneously forming a data line connected to the source electrode on the boundary of the pixel region on the interlayer insulating film; A gate contact hole for exposing the gate electrode to the outside of the active layer by patterning the first passivation layer, the interlayer insulating film, and the gate insulating film; forming a first passivation layer over the data line and the source and drain electrodes; ; ≪ / RTI > Forming a gate interconnection that contacts the gate electrode through the gate contact hole as a metal material at the boundary of the pixel region on the first protective layer and crosses the data interconnection; Forming a second passivation layer on the entire surface of the substrate over the gate wiring, forming a drain contact hole exposing the drain electrode by patterning the second passivation layer and a first passivation layer under the gate electrode; And forming a pixel electrode in the pixel region over the second passivation layer, the pixel electrode being in contact with the drain electrode through the drain contact hole.

The solid phase crystallization (SPC) process may be a thermal crystallization process at a temperature of 600 ° C. to 800 ° C. and an oxygen (O ₂ ) gas atmosphere, or a thermal crystallization process at a temperature of 600 ° C. to 700 ° C. and oxygen (O ₂ ) It is preferable that the alternating magnetic field crystallization is performed using an alternating magnetic field crystallization apparatus in a gas atmosphere.

The first thickness is 50 ANGSTROM to 100 ANGSTROM.

In addition, the barrier pattern, the ohmic contact layer, and the source and drain electrodes are formed by patterning at the same time by performing the same mask process so as to have the same size, the same size, and the completely overlapped shape in plan view.

The active layer of the pure polysilicon is formed to have a thickness of about 300 Å to 1000 Å and the interlayer insulating film is formed to have a thicker thickness than the sum of the thicknesses of the gate electrode and the gate insulating film, .

The step of forming the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, Wherein forming the second passivation layer having the drain contact hole comprises forming a gate pad contact hole exposing the gate pad electrode and a data pad contact exposing the data pad electrode, Wherein forming the pixel electrode comprises: forming a gate auxiliary pad electrode in contact with the gate pad electrode through the gate pad contact hole; and forming a gate contact pad electrode in contact with the data pad electrode through the data pad contact hole. And forming a data-assist pad electrode on the substrate.

The array substrate according to the present invention can prevent the formation of a thermal oxide film on the surface of the crystallized active layer by forming an inorganic insulating layer on the amorphous silicon layer to be patterned to form an active layer, . Accordingly, since the BOE process for removing the thermal oxide film can be omitted, the productivity per unit time can be improved by reducing the material cost and simplifying the process.

In addition, according to the method of manufacturing an array substrate according to the present invention, since the active layer is not exposed to dry etching, its surface damage is not caused, and the characteristics of the thin film transistor are prevented from deteriorating.

Since the active layer is not affected by the dry etching, it is not necessary to consider the thickness of the active layer to be etched away. Thus, the thickness of the active layer is reduced to shorten the deposition time and improve the productivity.

The array substrate manufactured by the manufacturing method according to the present invention includes a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming the thin film transistor as a semiconductor layer There is an effect of improving mobility characteristics by several tens to several hundreds of times as compared with an array substrate.

Since the active layer of polysilicon is used as the semiconductor layer of the thin film transistor, doping of the impurity is not required, so that it is not necessary to invest new equipment for progressing the doping process, so that the initial investment cost can be reduced.

Further, since the gate electrode is formed of polysilicon containing impurities, problems such as deformation of the gate electrode or short-circuit between the gate electrode and the semiconductor layer occurring in the course of the crystallization process of the conventional array substrate in which the gate electrode of the metal material is formed There is an effect that solves the problem originally.

The solid-phase crystallization process is performed in an oxygen (O ₂ ) gas atmosphere to form a thermally oxidized film having a thickness of about 50 Å to 100 Å on the pure polysilicon layer so that the pure polysilicon layer is exposed to air, It is possible to further simplify the process by omitting the formation of a separate inorganic insulating layer for preventing the inorganic insulating layer.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

≪ Embodiment 1 >

4A to 4M are cross-sectional views illustrating a pixel region, a gate pad portion, and a data pad portion including a thin film transistor of an array substrate according to a first embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr connected to the gate and data lines in each pixel region P is to be formed is defined as a switching region TrA.

4A, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is deposited on a transparent insulating substrate 101, for example, a glass substrate to form a film having a thickness of about 1000 Å to 3000 Å The buffer layer 102 is formed. Solid phase crystallization (SPC) processes are performed in a later process due to the characteristics of the present invention. Such a solid phase crystallization (SPC) process requires a high temperature atmosphere of 600 ° C to 800 ° C. In this case, if the substrate 101 is exposed to a high-temperature atmosphere, alkali ions may be eluted from the surface of the substrate 10 to degrade the characteristics of the constituent elements made of polysilicon. To prevent this problem, Lt; / RTI >

Next, impurity amorphous silicon is deposited on the buffer layer 102 to form a first impurity-doped amorphous silicon layer 103 having a thickness of about 500 Å to 1000 Å. Thereafter, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the first impurity-doped amorphous silicon layer 103 to form a first inorganic insulating layer 108 having a thickness of about 500 Å to 4000 Å, Pure amorphous silicon is deposited on the first inorganic insulating layer 108 to form a pure amorphous silicon layer 111 having a thickness of about 300 Å to 1000 Å.

The pure amorphous silicon layer 111 is formed to have a thickness of 1000 ANGSTROM or more in consideration of removing a part of its thickness from its surface by being exposed to a dry etching process for forming an ohmic contact layer which is separated from the conventional one. However, in the embodiment of the present invention, since the active layer of polysilicon (115 of FIG. 4M) ultimately realized through the pure amorphous silicon layer 111 is not exposed to dry etching, its thickness is thinned by the dry etching There is no problem such as being lost. Therefore, the pure amorphous silicon layer 111 may be formed to have a thickness of 300 to 1000 angstroms which can serve as an active layer. In this case, the effect of reducing the material cost and shortening the unit processing time can be obtained.

Next, in the manufacturing method according to the embodiment of the present invention, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the pure amorphous silicon layer 111 to form a _second amorphous silicon layer An inorganic insulating layer 116 is formed. The reason why the second inorganic insulating layer 116 is formed on the pure amorphous silicon layer in this way is that the pure amorphous silicon layer 111 is not exposed to the atmosphere during the crystallization process requiring a high temperature atmosphere of 600 ° C to 800 ° C So as to prevent the formation of a thermal oxide film on the surface thereof.

On the other hand, when the process proceeds to the step of forming the second inorganic insulating layer 116, a total of five material layers 102, 103, 108, 111, and 116 are formed on the substrate 101. In this case, since the material layers 102, 103, 108, 111, and 116 of the five layers are all semiconductor materials or inorganic insulating materials, all of these materials can be formed by chemical vapor deposition ) Equipment (not shown), all of which are continuously formed without exposure to the air by changing only the reaction gas in the same one of the vacuum chambers 195. When the five-layered material layers 102, 103, 108, 111, and 116 are successively deposited in one vacuum chamber 195, the surface of the pure amorphous silicon layer 111, It is possible to prevent degradation of the characteristics of the thin film transistor due to surface contamination of the active layer.

Next, as shown in FIG. 4B, the pure amorphous silicon layer (111 in FIG. 4A) is formed by performing a solid phase crystallization (SPC) process to improve the mobility characteristics of the pure amorphous silicon layer (111 in FIG. Crystallized to form a pure polysilicon layer 112. In this case, the solid phase crystallization (SPC) process may be a thermal crystallization process through heat treatment in an atmosphere of 600 ° C. to 800 ° C., alternatively, alternating crystallization in an atmosphere of 600 ° C. to 700 ° C. using an alternating- It is preferably an alternating magnetic field crystallization process.

At this time, not only the pure amorphous silicon layer (FIG. 4A 111) but also the first impurity amorphous silicon layer 103 (FIG. 4A) is crystallized by the progress of the solid phase crystallization (SPC) process to form the impurity polysilicon layer 104 .

Next, as shown in FIG. 4C, a photoresist layer (not shown) is formed by applying a photoresist onto the second inorganic insulating layer 117, and a photoresist layer (not shown) (Not shown), and a slit shape. Alternatively, a plurality of coating films may be further provided to adjust the amount of light passing therethrough so that the light transmittance is smaller than the transmissive region (not shown) Diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a large semi-transmissive area (not shown).

Thereafter, by developing the exposed photoresist layer (not shown), a portion of the portion where the gate electrode (105 of FIG. 4M) is to be formed corresponding to the switching region TrA is formed on the second inorganic insulating layer 116 First and second photoresist patterns 191a and 191b having a first thickness are formed corresponding to the active layer (115 in Fig. 4M) of the formed pure polysilicon to be formed, and the gate electrode The third photoresist pattern 191c having a second thickness that is thicker than the first thickness corresponds to the portion where the active layer of the pure polysilicon (115 in FIG. . Accordingly, a third photoresist pattern 191c having a second thickness is formed corresponding to a part of the portion where the gate electrode (105 of FIG. 4M) is to be formed and overlapped with the active layer of the pure polysilicon (115 of FIG. And a region where the active layer of pure polysilicon (115 in FIG. 4M) is not formed in the portion where the gate electrode (105 of FIG. 4M) is to be formed is formed in the region where the first and second photoresist patterns 191a, The photoresist layer (not shown) is removed to expose the second inorganic insulating layer 116 to all the regions on the substrate 101 where the gate electrode (105 of FIG. 4m) is not formed, .

At this time, the first and second photoresist patterns 191a and 191b are exposed outside the third photoresist pattern 191c in the switching region TrA, and the first and second photoresist patterns 191a and 191b are exposed outside the third photoresist pattern 191c. And the first and second photoresist patterns 191a and 191b exposed to the second photoresist pattern have different widths. This is because the gate electrode (105 in FIG. 4M) of the impurity amorphous silicon patterned later and the gate insulating film (109 in FIG. 4M) and the active layer (115 in FIG. 4m) 118 is formed in a stepped shape so as to prevent breakage or lifting of an interlayer insulating film (122 of FIG. 4m) formed thereafter and further to prevent interconnection between the gate wiring (145 of FIG. 4m) and the inorganic insulating pattern The gate contact hole (142 in FIG. 4M) for contact with the gate electrode (114 in FIG. 4M) exposed to the outside of the gate electrode (118 in FIG. 4M).

Next, as shown in FIG. 4D, the second inorganic insulating layer (116 in FIG. 4C) exposed to the outside of the first, second and third photoresist patterns 191a, 191b and 191c and the second inorganic insulating layer The first inorganic insulating layer (108 in FIG. 4C) and the impurity polysilicon layer (104 in FIG. 4C) are sequentially etched and removed by removing the pure polysilicon layer (112 in FIG. 4C) The gate electrode 114, the gate insulating film 109, the pure polysilicon pattern 113, and the inorganic insulating material pattern 117 of the impurity polysilicon sequentially stacked in island form are formed on the buffer layer 102. At this time, the second inorganic insulating layer (116 in FIG. 4C), the pure polysilicon layer (112 in FIG. 4C), the first inorganic insulating layer (108 in FIG. 4C), and the impurity The polysilicon layer (104 in FIG. 4C) is completely removed and the buffer layer 102 is exposed.

In the embodiment of the present invention, the formation of the gate electrode 105 from the impurity polysilicon rather than the metal material occurs when the pure polysilicon pattern 113 located on the gate electrode 105 is formed It is to solve the problem. In the case of forming a thin film transistor having a bottom gate structure, a gate electrode is formed of a metal material on a substrate, and a pure amorphous silicon layer is formed thereon via a gate insulating film for forming a semiconductor layer. A relatively high temperature of 600 DEG C or more is required for solid-phase crystallization with a pure polysilicon layer. Therefore, in the course of the solid-phase crystallization process requiring such a relatively high temperature, the gate electrode made of a metal material may be deformed or a problem may arise such that a spike that contacts the crystallized pure polysilicon layer through the gate insulating film occurs .

Therefore, in the embodiment of the present invention, in order to solve the problem that occurs during the crystallization process by forming the gate electrode of the metal material, the impurity polysilicon which does not cause the above-described problems even when exposed to such a high- ).

On the other hand, in the case of the gate electrode 105 made of the impurity polysilicon, although the conductivity is lower than the metal material, when the thickness of the gate electrode 105 of the impurity polysilicon is 500 ANGSTROM to 1000 ANGSTROM, ) To about 230? / Sq (?), Which is similar to that of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) which is a transparent conductive material. Therefore, even if the gate electrode is formed of the impurity polysilicon, there is no problem in performing a role as a gate electrode such as forming a channel in the active layer sufficiently.

Next, as shown in Fig. 4E, the substrate 101 on which the gate electrode 105 of the impurity polysilicon, the gate insulating film 109, the pure polysilicon pattern 113 and the inorganic insulating material pattern 117 are formed is subjected to ashing the first and second photoresist patterns 191a and 191b are removed from the third photoresist pattern 191c in the switching region TrA by proceeding ashing to remove the first and second photoresist patterns 191a and 191b of FIG. Thereby exposing both side surfaces of the inorganic insulating material pattern 117. At this time, due to the ashing process, the third photoresist pattern 191c is also reduced in thickness but still remains on the inorganic insulating material pattern 117. [

 Next, as shown in FIG. 4F, the inorganic insulating material pattern 117 (FIG. 4E) exposed at the outside of the third photoresist pattern 191c and the pure polysilicon pattern (113 in FIG. 4E) So that the edge of the gate insulating film 109 corresponding to the gate electrode 105 is exposed. The gate insulating layer 109 exposed outside the third photoresist pattern 191c is different in width from the third photoresist pattern 191c. A gate wiring (145 in FIG. 4 (m)), which will later be in contact with the gate electrode 105, should be formed corresponding to the gate insulating film 109 having a wide width and exposed outside the third photoresist pattern 191c, It is for this reason. At this time, the pure polysilicon pattern 113 (FIG. 4E), which is not etched by the third photoresist pattern 191c but remains on the gate insulating film 109, forms an active layer 115 of pure polysilicon . At this time, the inorganic polysilicon turns 118 are formed on the active layer 115 of the pure polysilicon with the same planarity as the active layer 115 of the pure polysilicon and completely overlapping with the reduced area of the active polysilicon 115.

4G, the strip is moved to remove the third photoresist pattern (191c in FIG. 4F) remaining on the inorganic insulating pattern 118, so that the inorganic insulating pattern 118 is removed, Lt; / RTI >

Next, as shown in Fig. 4h, the inorganic insulating pattern 118 over the inorganic insulating material for the monolayer structure example deposited one of silicon oxide (SiO ₂₎ or silicon nitride (SiNx), a third inorganic insulating layer (Not shown) or a second inorganic insulating layer (not shown) of a bilayer structure is formed by continuously depositing the two materials. At this time, it is preferable that the third inorganic insulating layer (not shown) is formed so as to have a thickness larger than the sum of the thicknesses of the gate electrode 105 and the gate insulating film 109, .

The reason for forming the third inorganic insulating layer (not shown) so as to have a thickness larger than the sum of the thicknesses of the gate electrode 105 and the gate insulating film 109 in the patterned state, So that the gate electrode 105 and the gate insulating film 109 can be seamlessly formed at the stepped portion. Since the total thickness of the gate electrode 105 and the gate insulating film 109 is greater than the sum of the thickness of the active layer 115 of pure polysilicon and the thickness of the inorganic insulating pattern 118 thereon, The thickness of the third inorganic insulating layer 122 may be thicker than the sum of the thicknesses of the active layer 115 and the gate insulating layer 109, It is not a problem in the stepped portion by the stepped portion 118.

The thickness of the gate insulating layer 109 is 500 ANGSTROM to 4000 ANGSTROM so that the thickness of the third inorganic insulating layer (not shown) may be thicker than 1000 ANGSTROM to 5000 ANGSTROM . For example, if the gate electrode 105 has a thickness of about 1000 Å and the gate insulating layer 109 has a thickness of about 2000 Å, the third inorganic insulating layer (not shown) For example, to have a thickness of about 3100 ANGSTROM so as to have a thickness.

  Thereafter, the third inorganic insulating layer (not shown) formed on the entire surface of the substrate 101 is subjected to a series of unit processes such as coating of photoresist, exposure using an exposure mask, development of exposed photoresist, etching, and strip (Not shown) for exposing the inorganic insulating pattern 118 to both sides of the active layer 115 of the pure polysilicon with respect to the center of the active layer 115, An insulating film 122 is formed. The inorganic insulating pattern 118 exposed in correspondence with the two contact holes (not shown) is successively removed by dry etching to finally expose the active layer 115 of the pure polysilicon, Thereby forming a hole 123.

At this time, the interlayer insulating layer 122 covers the active layer 115 of the pure polysilicon to serve as an etch stopper corresponding to the central part of the active layer 115 of the pure polysilicon, It functions as a layer.

Next, as shown in FIG. 4I, the active layer 115 has an active contact hole 123 exposing the active layer 115 corresponding to the active polysilicon layer 115, Pure amorphous silicon is deposited on the entire surface of the interlayer insulating film 122 serving as a stopper to further form a barrier layer (not shown) having a thickness of about 50 to 300 Å, and then impurity amorphous silicon is deposited continuously to form a barrier layer A second impurity amorphous silicon layer (not shown) having a thickness is formed. The reason for forming the barrier layer (not shown) made of pure amorphous silicon is that the bonding strength of the pure polysilicon to the active layer 115 is higher than that of the impurity amorphous silicon, ) Is interposed between the active layer 115 of the pure polysilicon and the impurity amorphous silicon layer (not shown), thereby improving the bonding force between the two layers 115 (not shown) and further lowering the contact resistance .

A first metal layer (not shown) may be formed by depositing a second metal material such as molybdenum (Mo), chromium (Cr), and molythiometry (MoTi) on the second impurity amorphous silicon layer .

On the other hand, a cleaning process (hereinafter referred to as BOE cleaning) using BOE (bufferd oxide etchant) is performed before the barrier layer (not shown) is formed on the interlayer insulating film 122 to form the active contact holes 123 It is necessary to remove the thermally oxidized film formed naturally on the surface of the active layer 115 of the pure polysilicon exposed during the crystallization process. However, in the production of the array substrate 101 according to the embodiment of the present invention, . The array substrate 101 according to the present invention can be continuously etched in the vacuum chamber (195 in FIG. 4A) of the chemical vapor deposition (CVD) equipment without exposure to the atmosphere above the pure amorphous silicon layer (SPC) process has been performed in a state where the second inorganic insulating layer 116 (FIG. 4A) covers the pure amorphous silicon layer 111 (FIG. 4A) No thermally oxidized film was formed on the surface of the active layer 115 of pure polysilicon, more precisely at the interface between the active layer 115 of the pure polysilicon and the inorganic insulating pattern 118.

Therefore, cleaning of buffer oxide etchant (BOE) for removing the thermal oxide film does not need to be performed separately. If a thermally oxidized film is formed on the surface of the active layer of pure polysilicon, this must be removed. This is because a thermal oxide film (not shown) serves as an element for lowering the ohmic characteristic when the active layer 115 of pure polysilicon contacts the barrier layer (not shown). Furthermore, if a thin film transistor is formed without removing the thermal oxide film, the characteristics may be greatly reduced or the thin film transistor may not be operated at all. Therefore, a barrier layer (not shown) must be formed in a state in which the thermal oxide film is removed do.

Next, a mask process is performed to pattern the first metal layer (not shown), a second impurity-amorphous silicon layer (not shown) and the barrier layer (not shown) located below the first metal layer And a data pad electrode 138 connected to one end of the data line 130 is connected to a data pad unit DPA where one end of the data line 130 is located, ).

At the same time, in the switching region TrA, source and drain electrodes 133 and 136 spaced from each other are formed on the interlayer insulating film 122, and impurity amorphous silicon is formed in the lower portions of the source and drain electrodes 133 and 136 And a barrier pattern 125 of pure amorphous silicon is formed below the ohmic contact layer 127. At this time, the barrier patterns 125 of the pure amorphous silicon are brought into contact with the active layer 115 of the pure polysilicon through the active contact holes 123, respectively.

The source electrode 133 and the data line 130 formed in the switching region TrA are formed to be connected to each other and the source and drain electrodes 133 and 136, The ohmic contact layer 127 and the barrier pattern 125 are formed in the same planar shape and planar shape as the source and drain electrodes 133 and 136, respectively.

 A first dummy pattern 128 made of impurity amorphous silicon and a second dummy pattern 126 made of pure amorphous silicon are formed under the data line 130 and the data pad electrode 138 by the above- .

In the exemplary embodiment of the present invention, in the process of forming the data line 130, the source and drain electrodes 133 and 136, the ohmic contact layer 127, and the barrier pattern 125, Since the inorganic insulating pattern 118 and the interlayer insulating film 122 serving as etch stoppers are formed corresponding to the central portion of the active layer 115 of the ohmic contact layer 115, The active layer 115 of the pure polysilicon is not affected at all during dry etching for patterning the barrier pattern 125 and the barrier pattern 125.

Therefore, it can be seen that there is no surface damage of the active layer due to the dry etching progress, which is a problem mentioned in the related art, and since the thickness of the active layer 115 of the pure polysilicon is not reduced, And the active layer 115 of the pure polysilicon has a constant thickness.

The gate electrode 105 of the impurity polysilicon sequentially stacked in the switching region TrA, the gate insulating film 109, the active layer 115 of pure polysilicon, The inorganic insulating pattern 118, the interlayer insulating film 122, the barrier pattern 125 of pure amorphous silicon, the ohmic contact layer 127 of the impurity amorphous silicon, and the source and drain electrodes 133 and 136, Thereby forming a transistor Tr.

Although not shown in the drawings, when the array substrate 101 described above is fabricated as an array substrate for an organic electroluminescence device, the data lines 130 are formed in the same layer on which the data lines 130 are formed, A gate wiring (145 in FIG. 4M) to be fabricated in the data wiring 130 and a subsequent process is formed in each pixel region P, and a power wiring (not shown) (Not shown) having the same structure and connected to the power supply line and the switching thin film transistor Tr may be further formed in addition to the thin film transistor Tr (which forms a switching thin film transistor) connected to the switching TFT.

Next, as shown in FIG. 4J, a substrate having the data line 130, the data pad electrode 138, the source and drain electrodes 133 and 136, the ohmic contact layer 127 and the barrier pattern 125 formed thereon by about 101), depositing the source and drain electrodes (133, 136) and the data line 130 and the data pad electrode 138 over the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) the The first passivation layer 140 and the interlayer insulating layer 122 and the gate insulating layer 109 are patterned by forming a first passivation layer 140 on the active layer 115, A gate contact hole 142 exposing the gate electrode 105 is formed.

Next, as shown in FIG. 4K, a second metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), etc. is formed on the first passivation layer 140 having the gate contact hole 142, ), A copper alloy, molybdenum (Mo), and chromium (Cr) are deposited to form a second metal layer (not shown). Thereafter, the second metal layer (not shown) is patterned by a mask process to contact the exposed gate electrode 105 at the boundary of each pixel region P over the first passivation layer 140, And a gate wiring 145 which intersects with the gate wiring 130 is formed.

At the same time, a gate pad electrode 147 connected to one end of the gate wiring 145 is formed in the gate pad portion GPA where one end of the gate wiring 145 is located.

At this time, the gate wiring 145 and the gate pad electrode 147 may be formed of only one metal material of the second metal material to form a single layer structure, or may be formed of two or more different second metal materials To form a double layer or a triple layer structure. For example, the gate wiring 145 and the gate pad electrode 147 may be formed of an aluminum alloy (AlNd) / molybdenum (Mo) when forming the double layer structure. When the gate wiring 145 and the gate pad electrode 147 are formed of a triple layer structure, / Aluminum alloy (AlNd) / molybdenum (Mo). In the drawing, a gate wiring 145 and a gate pad electrode 147 having a single layer structure are shown.

Next, as shown in Fig. 4l, the gate wiring 145 and the gate pad electrode 147 over the inorganic insulating material, for example silicon oxide on the front (SiO ₂₎ or the second protection by depositing a silicon nitride (SiNx) Layer 150 is formed. Thereafter, the masking process is performed to pattern the second passivation layer 150 and the first passivation layer 140 under the second passivation layer 150 to form drain contact holes (not shown) for exposing the drain electrodes 136 in the respective switching areas TrA And a gate pad contact hole 154 exposing the gate pad electrode 147 is formed in the gate pad portion GPA. At the same time, a data pad contact hole 156 exposing the data pad electrode 138 is formed in the data pad unit DPA.

Next, as shown in FIG. 4M, a transparent conductive material, for example, indium (In) is deposited on the entire surface of the second passivation layer 150 having the drain contact hole 152 and the gate and data pad contact holes 154 and 156, (Not shown) is formed by depositing a transparent conductive material layer (not shown) by depositing ITO or ITO to form a transparent conductive material layer The pixel electrode 170 is formed to be in contact with the drain electrode 136 through the through hole 152.

At the same time, in the gate pad portion GPA, a gate assistant pad electrode 172 is formed on the second passivation layer 150 to contact the gate pad electrode 147 through the gate pad contact hole 154 A data auxiliary pad electrode 174 contacting the data pad electrode 138 through the data pad contact hole 156 is formed on the second passivation layer 150 in the data pad unit DPA, Thereby completing the array substrate 101 according to the first embodiment of the present invention.

Though not shown in the drawing, when a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr (formed of a switching thin film transistor) formed in the switching region TrA A drain electrode (not shown) of the driving thin film transistor (not shown) is connected to the pixel electrode 170 and a drain electrode (not shown) of the driving thin film transistor (not shown) And are electrically connected to each other through a drain contact hole (not shown) formed. At this time, the thin film transistor Tr formed in the switching region TrA is completely covered with the first and second protective layers 140 and 150 without forming the drain contact hole 152. [ When a thin film transistor Tr (forming a switching thin film transistor) connected to the gate and data lines 145 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the switching region TrA, Thereby forming an array substrate for an organic electroluminescence element rather than an array substrate for a liquid crystal display.

≪ Embodiment 2 >

5A to 5F are cross-sectional views illustrating a pixel region, a gate pad portion, and a data pad portion including a thin film transistor of an array substrate according to a second embodiment of the present invention. Here, for convenience of description, a portion where the thin film transistor Tr connected to the gate and data lines in each pixel region P is to be formed is defined as a switching region TrA. For the same components as in the first embodiment, 100 were added and designated by reference numerals.

In the method of manufacturing an array substrate according to the second embodiment of the present invention, steps subsequent to the solid-phase crystallization process are performed in the same manner as in the first embodiment described above.

First, as shown in FIG. 5A, by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on a transparent insulating substrate 101, for example, a glass substrate, The buffer layer 202 is formed.

Next, impurity amorphous silicon is deposited on the buffer layer 202 to form a first impurity-doped amorphous silicon layer 203 having a thickness of about 500 Å to 1000 Å. Thereafter, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the first impurity-doped amorphous silicon layer 203 to form a first inorganic insulating layer 208 having a thickness of about 500 Å to 4000 Å, A pure amorphous silicon layer 211 having a thickness of about 300 Å to 1000 Å is formed by depositing pure amorphous silicon on the first inorganic insulating layer 208.

In the case of the second embodiment of the present invention, the active layer of polysilicon (215 in FIG. 5F) finally realized through the pure amorphous silicon layer 211 is not exposed to dry etching, so that the thickness thereof is thin There is no problem such as being lost. Therefore, the pure amorphous silicon layer 211 may be formed to have a thickness of 300 to 1000 angstroms which can serve as an active layer. In this case, the material amorphous silicon layer 211 has the effect of reducing the material cost and shortening the unit processing time.

On the other hand, as described above, the buffer layer 202, the impurity amorphous silicon layer 203, the first inorganic insulating layer 208, and the pure amorphous silicon layer 211, which are sequentially formed on the substrate 201, It can be seen that the middle layer of material is all a semiconductor material or an inorganic insulating material, all of which are all connected to the same single vacuum chamber 295 through chemical vapor deposition (CVD) equipment (not shown) And is continuously formed without exposure to the atmosphere by changing only the reaction gas in the atmosphere.

Next, as shown in FIG. 5B, the pure amorphous silicon layer 211 (FIG. 5A) is formed by performing a solid phase crystallization (SPC) process to improve the mobility characteristics of the pure amorphous silicon layer 211 (FIG. 5A) Is crystallized to form a pure polysilicon layer (212).

At this time, as the most characteristic in the second embodiment of the present invention, the solid phase crystallization (SPC) process, temperature, and oxygen of 600 ℃ to 800 ℃ for example (O ₂₎ Thermal through a heat treatment in a gas atmosphere crystallization (Thermal Crystallization ) Process or an alternating magnetic field crystallization process in an atmosphere of oxygen (O ₂ ) gas at a temperature of 600 ° C. to 700 ° C. using an alternating magnetic field crystallization apparatus.

When the thermal crystallization or the alternating magnetic field crystallization process is performed in the oxygen (O ₂ ) gas atmosphere, the pure amorphous silicon layer (211 in FIG. 5A) is crystallized and converted into the pure polysilicon layer 212, And a thermal oxide film 291 having a thickness of about 50 Å to 100 Å is formed by reacting with oxygen (O ₂ ) gas. In this case, the thermal oxide film 291 is formed by reacting with a pure oxygen (O ₂ ) gas which does not contain a contaminant present in the general atmosphere, and thus has a very good film quality.

Generally, the thermal crystallization is carried out by heating to a temperature of 600 ° C to 800 ° C in a chamber or furnace having a typical atmospheric atmosphere. In this case, the thermal oxide film formed by reacting with the oxygen contained in the general atmosphere includes contaminants, and oxygen contained in the air has a relatively low density, so that the thickness of the thermally oxidized film formed on the surface of the pure polysilicon layer Is less than 10 angstroms. Therefore, it is too thin to perform the role of protecting the pure polysilicon layer 212, so that it can not perform its role.

Alternating magnetic field crystallization usually proceeds in an atmosphere of nitrogen (N ₂ ) gas, which is an inert gas, or in an atmosphere of one atmosphere, such as the thermal crystallization. Therefore, when proceeding in a nitrogen (N ₂ ) gas atmosphere, A thermal oxide film is hardly formed on the upper part of the polysilicon layer 212 and the contaminant is contained or the thickness of the thermal oxide film is less than 10 angstroms when the device is operated in an ordinary atmospheric environment so that the pure polysilicon layer can not be protected do.

However, in the case of the second embodiment of the present invention, the progress of the thermal crystallization or alternating magnetic field crystallization process proceeds in a chamber 297 in which an oxygen (O ₂ ) gas atmosphere is formed. In this case, the oxygen (O ₂ ) gas is continuously supplied in the chamber 297 to have a constant density, so that the surface of the pure polysilicon layer 212 in the high temperature atmosphere has a thickness of about 50 Å to 100 Å, The thermally oxidized film 291 is formed in such a manner that the silicon oxide layer 291 can smoothly perform the function of protecting the silicon layer 212. In this case, since contaminants are not contained in the thermally oxidized film 291, There is no problem such as contamination.

Meanwhile, not only the pure amorphous silicon layer (FIG. 5A 211) but also the first impurity amorphous silicon layer (203 in FIG. 5A) is crystallized by progressing the solid phase crystallization (SPC) process in the atmosphere of pure oxygen (O ₂ ) Impurity polysilicon layer 204 is formed.

4C to 4G of the first embodiment, the substrate 201 on which the pure thermally-oxidized film 212 having a thickness of about 50 ANGSTROM to about 100 ANGSTROM is formed is subjected to the same process as shown in FIG. 5C, A gate insulating film 209 completely overlapping with the gate electrode 205 of the impurity polysilicon as an island shape and the same plane as the gate electrode 205 is formed on the buffer layer 202 in the switching region TrA on the substrate 201, An active layer 215 of pure polysilicon exposing the edge of the active layer 215 and a thermally oxidized film pattern 292 having the same planarity as the active layer 215 and completely overlapping are formed.

In this process, the active layer 215 of the pure polysilicon is covered with the thermally oxidized film pattern 292 having a thickness of about 50 Å to 100 Å, so that the active layer 215 is not exposed to air and thus protected from contamination.

Then isolated, and the third arms of the single-layer structure by depositing one of said thermal oxide film pattern 292 over the inorganic insulating material, for example, silicon oxide (SiO ₂₎ or silicon nitride (SiNx), as shown in Figure 5d A third inorganic insulating layer (not shown) of a bilayer structure is formed by forming a layer (not shown) or continuously depositing the two materials. At this time, the third inorganic insulating layer (not shown) is formed so as to have a thickness larger than the sum of the thicknesses of the gate electrode 205 and the gate insulating film 209 which are formed in the same plane and completely overlap each other. The reason for this formation is omitted in the first embodiment because it is already mentioned.

Thereafter, the third inorganic insulating layer (not shown) formed on the entire surface of the substrate 201 is subjected to a series of unit processes such as coating of photoresist, exposure using an exposure mask, development of exposed photoresist, etching, and strip And an interlayer insulating film (not shown) having two holes hl for exposing the thermally-oxidized film pattern 292 on both sides of the central portion of the active layer 215 of the pure polysilicon 222 are formed.

Next, as shown in FIG. 5E, the thermal oxidation film pattern 292 exposed in correspondence with the two holes (h1 in FIG. 5D) is removed by dry etching, Two active contact holes 223 are formed to expose the active layer 215 of pure polysilicon.

At this time, the interlayer insulating layer 222 and the thermal oxide film pattern 292 remaining on the interlayer insulating layer 222 cover the active layer 215 of the pure polysilicon corresponding to the central portion of the active layer 215 of the pure polysilicon. Therefore, it functions as an etch stopper, and serves as an insulating layer corresponding to other areas.

5D) in which the thermal oxide film pattern 292 is exposed and the thermal oxide film pattern 292 exposed in the hole (hl in FIG. 5D) are formed in the interlayer insulating film 222, The step of forming the active contact hole 223 for exposing the active layer 215 is shown as proceeding separately in the figure, but it proceeds substantially continuously. That is, since the interlayer insulating film 222 is also made of an inorganic insulating material, patterning of the interlayer insulating film 222 is also performed by dry etching. Therefore, the holes (h1 in FIG. 5D) and the active contact holes 223 are continuously formed in the chamber (not shown) for the dry etch process without any movement. In this case, when the material forming the thermal oxidation film pattern 292 is different from that of the interlayer insulating film 222, only the reaction gas in the chamber (not shown) may be changed. For this reason, The formation of the second interlayer insulating film 223 can be continuously performed by dry etching.

5F, the active contact holes 223 are formed on the interlayer insulating film 222 in the switching region TrA by proceeding in the same manner as the process according to the first embodiment described with reference to FIGS. 4I to 4M, A barrier pattern 225 of pure amorphous silicon separated from each other and an ohmic contact layer 227 and source and drain electrodes 233 and 236 of the impurity amorphous silicon are formed. At this time, the gate electrode 205 of the impurity polysilicon, the gate insulating film 209, the active layer 215 of pure polysilicon, the inorganic insulating pattern 218, and the gate electrode 205, which are sequentially stacked in the switching region TrA, The interlayer insulating film 222, the barrier pattern 225 of pure amorphous silicon, the ohmic contact layer 227 of the impurity amorphous silicon and the source and drain electrodes 233 and 236 constitute the thin film transistor Tr.

A data line 230 is formed on the boundary of each pixel region P on the interlayer insulating layer 222 and the data line 230 is connected to a data pad portion DPA where one end of the data line 230 is located. A data pad electrode 238 is formed.

The source and drain electrodes 233 and 236 and the substrate 201 having the ohmic contact layer 227 and the barrier pattern 225 are formed on the data line 230 and the data pad electrode 238 and the source and drain electrodes 233 and 236, The first passivation layer 240 is formed by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) over the electrodes 233 and 236, the data line 230 and the data pad electrode 238 The gate electrode 205 is formed outside the active layer 215 of the pure polysilicon by patterning the first passivation layer 240, the interlayer insulating film 222 and the gate insulating film 209 by a mask process. Thereby forming a gate contact hole 242 to expose.

The gate electrode 205 is formed on the gate electrode 205 and the gate electrode 205. The gate electrode 205 is formed on the first passivation layer 240 having the gate contact hole 242, A gate wiring 245 is formed.

At the same time, a gate pad electrode 247 connected to one end of the gate wiring 245 is formed in the gate pad portion GPA where one end of the gate wiring 245 is located.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited over the gate wiring 245 and the gate pad electrode 247 to form the second passivation layer 250. Then, a mask process is performed to pattern the second passivation layer 250 and the first passivation layer 240 under the drain electrode 236 to expose the drain electrode 236 in each switching region TrA And a gate pad contact hole 254 exposing the gate pad electrode 247 is formed in the gate pad portion GPA. At the same time, a data pad contact hole 256 exposing the data pad electrode 238 is formed in the data pad unit DPA.

Then, a transparent conductive material such as indium-tin-oxide (ITO) or the like is deposited on the entire surface of the second passivation layer 250 having the drain contact hole 252 and the gate and data pad contact holes 254 and 256, (Not shown) is formed by depositing indium-zinc-oxide (IZO) on the pixel region P and then patterned by performing a masking process. Thus, The pixel electrode 270 is formed in contact with the pixel electrode 236.

At the same time, in the gate pad portion GPA, a gate auxiliary pad electrode 272 is formed on the second passivation layer 250 to contact the gate pad electrode 247 through the gate pad contact hole 254 A data auxiliary pad electrode 274 contacting the data pad electrode 238 is formed on the second passivation layer 250 through the data pad contact hole 256 in the data pad unit DPA, Thereby completing the array substrate 201 according to the second embodiment of the present invention.

The array substrate 201 according to the second embodiment manufactured by this step is formed by performing a solid phase crystallization (SPC) process in an oxygen (O ₂ ) gas atmosphere to intentionally deposit on a pure polysilicon layer By forming a thermally oxidized film (291 in FIG. 5B) having a thickness enough to serve as an insulating layer, an additional additional second inorganic insulating layer formation as compared with the first embodiment is eliminated to further simplify the manufacturing process .

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device, in which one pixel region is cut including a thin film transistor. Fig.

FIGS. 2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate; FIGS.

3 is a cross-sectional view of a pixel region including the thin film transistor in an array substrate having a thin film transistor having a conventional polysilicon semiconductor layer.

FIGS. 4A to 4M are cross-sectional views illustrating a pixel region including a thin film transistor of an array substrate according to a first embodiment of the present invention, a gate pad portion, and a data pad portion according to manufacturing steps.

5A to 5F are cross-sectional views illustrating a pixel region including a thin film transistor of an array substrate according to a second embodiment of the present invention, a gate pad portion, and a data pad portion according to manufacturing steps.

Description of the Related Art

101: substrate 102: buffer layer

104: impurity polysilicon layer 108: first inorganic insulating layer

112: pure polysilicon layer 116: second inorganic insulating layer

DPA: Data pad part GPA: Gate pad part

P: pixel region Tr: thin film transistor

TrA: switching area

Claims (16)

Depositing a buffer layer made of an inorganic insulating material, a doped amorphous silicon layer, a first inorganic insulating layer, a pure amorphous silicon layer, and a second inorganic insulating layer in this order on a substrate on which a pixel region and a switching region are defined; Crystallizing the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer by performing a solid phase crystallization (SPC) process; Forming an impurity polysilicon gate electrode and a gate insulating film sequentially stacked on the buffer layer in the island shape and having the same planarity, exposing the edge of the gate insulating film over the gate insulating film, Forming an active layer of stacked pure polysilicon and an inorganic insulating pattern; Forming an insulating interlayer on the entire surface of the inorganic insulating pattern by depositing an inorganic insulating material on the entire surface of the inorganic insulating pattern; patterning the inorganic insulating pattern on the interlayer insulating layer to expose both sides of the active insulating layer, ; ≪ / RTI >  A barrier pattern of pure amorphous silicon in contact with the active layer through the active contact holes and spaced apart from each other through the active interlayer insulating film; an ohmic contact layer of impurity amorphous silicon on the respective barrier patterns; Forming source and drain electrodes spaced apart from each other and simultaneously forming a data line connected to the source electrode on the boundary of the pixel region on the interlayer insulating film; A gate contact hole for exposing the gate electrode to the outside of the active layer by patterning the first passivation layer, the interlayer insulating film, and the gate insulating film; forming a first passivation layer over the data line and the source and drain electrodes; ; ≪ / RTI > Forming a gate interconnection that contacts the gate electrode through the gate contact hole as a metal material at the boundary of the pixel region on the first protective layer and crosses the data interconnection; Forming a second passivation layer on the entire surface of the substrate over the gate wiring, forming a drain contact hole exposing the drain electrode by patterning the second passivation layer and a first passivation layer under the gate electrode; Forming a pixel electrode in the pixel region on the second passivation layer in contact with the drain electrode through the drain contact hole; Wherein a solid-phase crystallization process is performed in a state where the second inorganic insulating layer is formed, thereby preventing a thermal oxidation film from being formed at an interface between the pure polysilicon layer and the second inorganic insulating layer Gt; The method according to claim 1, A gate electrode of an impurity polysilicon layer which is sequentially stacked on the buffer layer and has the same planarity as an island shape and a gate insulating film are formed on the gate insulating film and an edge of the gate insulating film is exposed on the gate insulating film, The step of forming an inorganic insulating pattern with an active layer of successively stacked pure polysilicon, A first photoresist pattern having a first thickness corresponding to a portion where the active layer is formed in the switching region is formed on the second inorganic insulating layer, and a second photoresist pattern corresponding to the edge of the gate electrode exposed to the outside of the active layer Forming second and third photoresist patterns having a second thickness that is less than the first thickness and different widths from each other; The second inorganic insulating layer exposed to the outside of the first to third photoresist patterns and the pure polysilicon layer, the first inorganic insulating layer, and the impurity polysilicon layer below the first inorganic insulating layer are sequentially removed, Forming a gate electrode of the impurity polysilicon, a gate insulating film, a pure polysilicon pattern, and an inorganic insulating material pattern having the same planarity and sequentially stacked; Exposing an edge of the inorganic insulating material pattern to the outside of the first photoresist pattern by ashing and removing the second and third photoresist patterns; Removing the inorganic insulating material pattern exposed outside the first photoresist pattern and the pure polysilicon pattern thereunder to expose the edges of the gate insulating film on the gate insulating film, Forming an active layer of the pure polysilicon and an inorganic insulating pattern; Removing the first photoresist pattern Wherein the substrate is a substrate. The method according to claim 1, The buffer layer, the impurity amorphous silicon layer, the first inorganic insulating layer, the pure amorphous silicon layer, and the second inorganic insulating layer are continuously formed in the same vacuum chamber through chemical vapor deposition (CVD) equipment Wherein the substrate is a substrate. The method according to claim 1, Wherein the solid phase crystallization (SPC) process is an alternating magnetic field crystallization process using a thermal crystallization or an alternating magnetic field crystallization apparatus through a heat treatment in a temperature range of 600 ° C to 800 ° C. Way. The method according to claim 1, Wherein the barrier pattern, the ohmic contact layer, and the source and drain electrodes are formed by patterning at the same time by performing the same mask process so that the barrier pattern, the ohmic contact layer, and the source and drain electrodes have the same shape, the same size, and the completely overlapped shape. The method according to claim 1, Wherein the active layer of the pure polysilicon has a thickness of about 300 ANGSTROM to 1000 ANGSTROM, the inorganic insulating pattern has a thickness of about 100 ANGSTROM to 500 ANGSTROM, and the interlayer insulating film has a thickness of the gate electrode and the gate insulating film, Wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer. The method according to claim 1, Wherein forming the data line with the source and drain electrodes comprises forming a data pad electrode connected to one end of the data line, Wherein forming the gate wiring includes forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode, Wherein the forming of the pixel electrode comprises forming a gate assist pad electrode contacting the gate pad electrode through the gate pad contact hole and a data assist pad electrode contacting the data pad electrode through the data pad contact hole, Wherein the substrate is a substrate. A buffer layer formed of an inorganic insulating material on the entire surface of the substrate on which the pixel region and the switching region are defined; A gate electrode and a gate insulating film of polysilicon sequentially stacked on the buffer layer and having the same planar shape as the island shape; An active layer of pure polysilicon formed in an island shape to expose an edge of the gate insulating film over the gate insulating film; An inorganic insulating pattern formed on the active layer and having the same planarity as the active layer and overlapped with the active layer and serving to prevent formation of a thermal oxidation film at the interface of the active layer; An interlayer insulating layer formed on the entire surface of the substrate, the active layer having an active contact hole exposing the active layer on the inorganic insulating pattern and serving as an etch stopper at a central portion of the active layer;  A barrier pattern of pure amorphous silicon formed in contact with the active layer and spaced apart from the active region through the active contact hole over the interlayer insulating film in the switching region; An ohmic contact layer of impurity amorphous silicon formed on the upper portion of the barrier pattern; Source and drain electrodes spaced apart from the ohmic contact layer spaced apart from each other; A data line formed on the interlayer insulating film and connected to the source electrode at a boundary of the pixel region; A first protective layer formed on the data line with a gate contact hole exposing the gate electrode outside the inorganic insulating pattern; A gate line formed in contact with the gate electrode through the gate contact hole at a boundary of the pixel region on the first passivation layer and intersecting the data line; A second passivation layer formed on the gate line and having a drain contact hole exposing the drain electrode; And a drain electrode formed on the second protective layer, the drain electrode being in contact with the drain electrode through the drain contact hole, ≪ / RTI > 9. The method of claim 8, Wherein the gate electrode of the impurity polysilicon has a thickness of 500 ANGSTROM to 1000 ANGSTROM and the active layer of the pure polysilicon has a thickness of 300 ANGSTROM to 1000 ANGSTROM and the inorganic insulating pattern has a thickness of 100 ANGSTROM to 500 ANGSTROM, And the interlayer insulating film is formed to have a thickness greater than the sum of the thicknesses of the gate electrode and the gate insulating film located below the interlayer insulating film. 10. The method of claim 9, A gate pad electrode connected to an end of the gate line, and a data pad electrode connected to an end of the data line, Wherein the second passivation layer has a gate pad contact hole exposing the gate pad electrode and the second and first passivation layers have data pad contact holes exposing the data pad electrode, A gate auxiliary pad electrode which is in contact with the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer and a data auxiliary electrode which contacts the data pad electrode through the data pad contact hole, Pad electrode ≪ / RTI > Depositing a buffer layer made of an inorganic insulating material, an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer sequentially on a substrate on which a pixel region and a switching region are defined; (SPC) process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer, respectively, and simultaneously form a thermal oxide film having a first thickness on the pure polysilicon layer ; ≪ / RTI > Forming an impurity polysilicon gate electrode and a gate insulating film sequentially stacked on the buffer layer in the island shape and having the same planarity, exposing the edge of the gate insulating film over the gate insulating film, Forming an active layer and a thermal oxide film pattern of stacked pure polysilicon; Forming an insulating interlayer on the entire surface of the thermal oxide film pattern by depositing an inorganic insulating material on the entire surface of the thermal oxide film pattern; patterning the interlayer insulating film and the thermal oxide film pattern thereunder to expose both sides of the active layer, ; ≪ / RTI >  A barrier pattern of pure amorphous silicon in contact with the active layer through the active contact holes and spaced apart from each other through the active interlayer insulating film; an ohmic contact layer of impurity amorphous silicon on the respective barrier patterns; Forming source and drain electrodes spaced apart from each other and simultaneously forming a data line connected to the source electrode on the boundary of the pixel region on the interlayer insulating film; A gate contact hole for exposing the gate electrode to the outside of the active layer by patterning the first passivation layer, the interlayer insulating film, and the gate insulating film; forming a first passivation layer over the data line and the source and drain electrodes; ; ≪ / RTI > Forming a gate interconnection that contacts the gate electrode through the gate contact hole as a metal material at the boundary of the pixel region on the first protective layer and crosses the data interconnection; Forming a second passivation layer on the entire surface of the substrate over the gate wiring, forming a drain contact hole exposing the drain electrode by patterning the second passivation layer and a first passivation layer under the gate electrode; Forming a pixel electrode in the pixel region on the second passivation layer in contact with the drain electrode through the drain contact hole; And forming a plurality of arrays on the array substrate. 12. The method of claim 11, The solid phase crystallization (SPC) process, temperature, and oxygen of 600 ℃ to 800 ℃ (O ₂₎ Thermal through a heat treatment in a gas minutes crisis crystallization or (Thermal Crystallization) or 600 ℃ to 700 ℃ temperature and oxygen (O ₂₎ of the gas Wherein the alternating magnetic field crystallization is performed using an alternating magnetic field crystallization apparatus in an atmosphere. 12. The method of claim 11, Wherein the first thickness is 50 to 100 Angstroms. 12. The method of claim 11, Wherein the barrier pattern, the ohmic contact layer, and the source and drain electrodes are formed by patterning at the same time by performing the same mask process so as to have the same size, the same size, and the completely overlapped shape . 12. The method of claim 11, Wherein the active layer of the pure polysilicon has a thickness of about 300 ANGSTROM to 1000 ANGSTROM and the interlayer insulating film is formed to have a thicker thickness than the sum of the thicknesses of the gate electrode and the gate insulating film, / RTI > 12. The method of claim 11, Wherein forming the data line with the source and drain electrodes comprises forming a data pad electrode connected to one end of the data line, Wherein forming the gate wiring includes forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode, Wherein the forming of the pixel electrode comprises forming a gate assist pad electrode contacting the gate pad electrode through the gate pad contact hole and a data assist pad electrode contacting the data pad electrode through the data pad contact hole, Wherein the substrate is a substrate.

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