KR20030058631A - Forming method for field oxide of semiconductor device - Google Patents
Forming method for field oxide of semiconductor device Download PDFInfo
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- KR20030058631A KR20030058631A KR1020010089155A KR20010089155A KR20030058631A KR 20030058631 A KR20030058631 A KR 20030058631A KR 1020010089155 A KR1020010089155 A KR 1020010089155A KR 20010089155 A KR20010089155 A KR 20010089155A KR 20030058631 A KR20030058631 A KR 20030058631A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 150000004767 nitrides Chemical class 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 8
- 239000002002 slurry Substances 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
Description
본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 보다 상세하게 트렌치 식각 공정 후 소자분리마스크인 질화막을 소정 두께 리세스시킴으로써 질화막 제거 후 실시되는 세정공정으로 소자분리절연막의 가장자리가 함몰되는 모우트(moat)현상이 발생하는 것을 방지하는 반도체소자의 소자분리절연막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and more particularly, a recess in which an edge of the device isolation insulating film is recessed in a cleaning process performed after removing the nitride film by recessing a nitride film, which is a device isolation mask, by a predetermined thickness after the trench etching process. The present invention relates to a device isolation insulating film formation method of a semiconductor device which prevents occurrence of moat phenomenon.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소 정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension, and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅 현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있기 때문에 게이트전극의 선폭이 0.18㎛ 이하인 DRAM에서는 얕은 트렌치를 이용한 소자분리(shallow trench isolation, STI)공정이 적용되고 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method is a gate electrode because there is a limitation in application in a giga DRAM class due to the problem of thinning the device isolation layer and the buzz big phenomenon. A shallow trench isolation (STI) process using shallow trenches is applied to DRAMs having a line width of 0.18 mu m or less.
이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1a 내지 도 1f 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 패드산화막(13)과 질화막(15)을 순차적으로 형성한다. (도 1a 참조)First, the pad oxide film 13 and the nitride film 15 are sequentially formed on the semiconductor substrate 11. (See Figure 1A)
다음, 소자분리 마스크를 식각마스크로 이용하여 상기 질화막(15)과 패드산화막(13)을 식각하여 질화막패턴(16)과 패드산화막패턴(14)을 형성한다.Next, the nitride layer pattern 16 and the pad oxide layer pattern 14 are formed by etching the nitride layer 15 and the pad oxide layer 13 using the device isolation mask as an etching mask.
그 다음, 상기 질화막패턴(16)을 식각마스크로 상기 반도체기판(11)을 소정 두께 제거하여 트렌치(17)를 형성한다. (도 1b 참조)Next, the trench 17 is formed by removing the semiconductor substrate 11 by a predetermined thickness using the nitride film pattern 16 as an etching mask. (See FIG. 1B)
다음, 전체표면 상부에 매립절연막(19)을 증착한다. 이때, 상기 매립절연막(19)은 고밀도 플라즈마 산화막(hign density plasma oxide)으로 형성된다. (도 1c 참조)Next, a buried insulating film 19 is deposited over the entire surface. In this case, the buried insulating film 19 is formed of a high density plasma oxide film. (See Figure 1C)
그 다음, 상기 매립절연막(19)은 상기 질화막패턴(16)을 연마장벽으로 이용한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 반도체기판(11)의 활성영역을 분리시키는 소자분리절연막(21)을 형성한다. (도 1d 참조)Then, the buried insulating film 19 is a device for separating the active region of the semiconductor substrate 11 by removing the nitride film pattern 16 by a chemical mechanical polishing (hereinafter referred to as CMP) process using a polishing barrier The isolation insulating film 21 is formed. (See FIG. 1D)
다음, 상기 질화막패턴(16)을 습식식각공정으로 제거한다. 이때, 상기 습식식각공정은 인산용액을 식각용액으로 이용하여 실시된다. (도 1e 참조)Next, the nitride film pattern 16 is removed by a wet etching process. In this case, the wet etching process is performed using a phosphoric acid solution as an etching solution. (See Figure 1E)
그 다음, 세정공정을 실시한다. 이때, 상기 소자분리절연막(21)과 패드절연막패턴(14)가 소정 두께 리세스되어 상기 소자분리절연막(21)은 상기 반도체기판(11)의 활성영역 높이로 형성되지만, 그 가장자리가 함몰되어 활성영역보다 낮게 형성된다. (도 1f 참조)Next, a washing process is performed. In this case, the device isolation insulating film 21 and the pad insulating film pattern 14 are recessed to a predetermined thickness so that the device isolation insulating film 21 is formed to the height of the active region of the semiconductor substrate 11, but the edges thereof are recessed to be active. It is formed lower than the area. (See Figure 1f)
상기와 같이 종래기술에 따른 반도체소자의 소자분리절연막 형성방법은, CMP공정으로 소자분리절연막을 형성하고 소자분리마스크 및 CMP공정의 연마장벽으로 사용되는 질화막을 제거한 후 세정공정을 실시하였다. 그러나, 상기 세정공정은 등방성으로 실시되기 때문에 도 1f 의 ⓧ부분과 같이 소자분리절연막의 가장자리 부분이 함몰되는 모우트(moat) 현상이 발생하게 된다. 이로 인하여 상기 함몰부분에서 게이트 절연막의 두께가 얇게 형성되고, 게이트 전극 형성 후 상기 함몰부분에 전기장이 크게 걸려 제너레이션(generation)된 핫캐리어(hot carrier)량이 증가하여 트랜지스터의 라이프 타임(lifetime)을 감소시키는 문제점이 있다. 또한, 문턱전압(threshold voltage)을 감소시키고 누설전류를 증가시키는 등 소자의 전기적 특성을 감소시키고, 게이트전극 형성 후 함몰 부분에 게이트전극 물질이 잔존하여 소자 간에 브리지를 유발하는 문제점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the related art, a device isolation insulating film is formed by a CMP process, and a cleaning process is performed after removing the device isolation mask and the nitride film used as the polishing barrier of the CMP process. However, since the cleaning process is performed isotropically, a moat phenomenon occurs in which the edge portion of the device isolation insulating film is recessed, as shown in FIG. 1F. As a result, the thickness of the gate insulating layer is thinly formed in the recessed portion, and a large electric field is applied to the recessed portion after formation of the gate electrode, thereby increasing the amount of generated hot carriers, thereby reducing the lifetime of the transistor. There is a problem. In addition, there is a problem of reducing the electrical characteristics of the device, such as reducing the threshold voltage and increasing the leakage current, and the gate electrode material remains in the recessed portion after forming the gate electrode, causing a bridge between the devices.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치 식각 후 질화막을 소정 두께 리세스시킨 후 소자분리절연막을 형성하여 상기 소자분리절연막의 가장자리가 반도체기판의 활성영역 상에 형성되도록 함으로써 후속 세정공정에서 소자분리절연막의 가장자리가 함몰되는 것을 방지하여 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.According to the present invention, in order to solve the problems of the prior art, after the trench is etched, the nitride film is recessed to a predetermined thickness, and a device isolation insulating film is formed so that the edge of the device isolation insulating film is formed on the active region of the semiconductor substrate. It is an object of the present invention to provide a method for forming a device isolation insulating film of a semiconductor device to prevent the edge of the device isolation insulating film from being recessed in the process to improve electrical characteristics and reliability of the device.
도 1a 내지 도 1f 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
도 2a 내지 도 2g 는 본 발명에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 101 : 반도체기판 13, 103 : 패드산화막11, 101: semiconductor substrate 13, 103: pad oxide film
14, 104 : 패드산화막패턴 15, 105 : 질화막14, 104: pad oxide film pattern 15, 105: nitride film
16, 106 : 질화막패턴 17, 107 : 트렌치16, 106: nitride film pattern 17, 107: trench
19, 109 : 매립절연막 21, 111 : 소자분리절연막19, 109: buried insulating film 21, 111: device isolation insulating film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,Method for forming a device isolation insulating film of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 활성영역을 정의하는 패드산화막패턴과 질화막패턴의 적층구조를 형성하는 공정과,Forming a stacked structure of a pad oxide film pattern and a nitride film pattern defining an active region on the semiconductor substrate;
상기 질화막패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the nitride film pattern as an etching mask;
상기 질화막패턴을 소정 두께 리세스시켜 상기 활성영역의 가장자리를 노출시키는 공정과,Exposing the edge of the active region by recessing the nitride film pattern by a predetermined thickness;
전체표면 상부에 매립절연막을 형성하는 공정과,Forming a buried insulating film over the entire surface;
상기 매립절연막을 화학적 기계적 연마공정으로 제거하여 상기 활성영역을 분리하는 소자분리절연막을 형성하되, 상기 소자분리절연막의 가장자리를 상기 활성영역 상에 형성하는 공정과,Removing the buried insulating film by a chemical mechanical polishing process to form a device isolation insulating film for separating the active region, and forming an edge of the device isolation insulating film on the active region;
상기 질화막패턴을 제거하는 공정과,Removing the nitride film pattern;
세정공정을 실시하여 상기 패드산화막패턴 및 소정 두께의 소자분리절연막을 제거하는 공정을 포함하는 것과,Performing a cleaning process to remove the pad oxide film pattern and the device isolation insulating film having a predetermined thickness;
상기 패드산화막패턴은 50 ∼ 100Å 두께로 형성되는 것과,The pad oxide film pattern is formed to a thickness of 50 ~ 100Å,
상기 질화막패턴은 400 ∼ 1500Å 두께로 형성되는 것과,The nitride film pattern is formed to a thickness of 400 ~ 1500Å,
상기 트렌치는 2300 ∼ 10000Å 깊이로 형성되는 것과,The trench is formed to a depth of 2300 ~ 10000Å,
상기 질화막패턴은 인산용액을 이용한 습식식각공정으로 20 ∼ 500Å 두께 리세스되는 것과,The nitride layer pattern may be 20 to 500 mm thick recessed by a wet etching process using a phosphate solution,
상기 매립절연막은 고밀도 플라즈마 산화막으로 4000 ∼ 15000Å 두께 형성되는 것과,The buried insulating film is formed of a high density plasma oxide film 4000 ~ 15000Å thick,
상기 화학적 기계적 연마공정은 질화막과 산화막의 연마선택비가 1 : 10 ∼ 1 : 200인 고선택비 슬러리를 사용하여 실시되는 것과,The chemical mechanical polishing process is carried out using a high selectivity slurry having a polishing selectivity of 1: 10 to 1: 200 of the nitride film and the oxide film,
상기 슬러리는 SiO2, CeO2, Al2O3또는 Zr2O3를 연마제로 사용하고 산도가 pH2 ∼ 12인 것을 특징으로 한다.The slurry is characterized by using SiO 2 , CeO 2 , Al 2 O 3 or Zr 2 O 3 as an abrasive and having an acidity of pH 2 to 12.
본 발명의 원리는 트렌치 식각 후 질화막을 소정 두께 리세스시킴으로써 소자분리절연막의 가장자리가 반도체기판의 활성영역에 형성되도록 하여 후속 세정공정으로 소자분리절연막의 가장자리가 반도체기판의 활성영역보다 낮게 형성되는 것을 방지하는 것이다.The principle of the present invention is that the edge of the isolation layer is formed in the active region of the semiconductor substrate by recessing the nitride film by a predetermined thickness after the trench etching, so that the edge of the isolation layer is formed lower than the active region of the semiconductor substrate by a subsequent cleaning process. To prevent.
이하, 첨부된 도면을 참고로 하여 본 발명에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the present invention.
도 2a 내지 도 2g 는 본 발명에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the present invention.
먼저, 반도체기판(101) 상부에 패드산화막(103)과 질화막(105)을 형성한다. 이때, 상기 패드산화막(103)은 50 ∼ 100Å 두께로 형성되고, 상기 질화막(105)은 400 ∼ 1500Å 두께로 형성된다. (도 2a 참조)First, a pad oxide film 103 and a nitride film 105 are formed on the semiconductor substrate 101. In this case, the pad oxide film 103 is formed to a thickness of 50 to 100 kPa, and the nitride film 105 is formed to a thickness of 400 to 1500 kPa. (See Figure 2A)
다음, 소자분리 마스크로 식각마스크로 상기 질화막(105)과 패드산화막(103)을 식각하여 질화막패턴(106)과 패드산화막패턴(104)을 형성한다.Next, the nitride layer pattern 105 and the pad oxide layer 103 are etched using an etching mask to form the nitride layer pattern 106 and the pad oxide layer pattern 104.
그 다음, 상기 질화막패턴(106)을 식각마스크로 상기 반도체기판(11)을 식각하여 트렌치(107)를 형성한다. 이때, 상기 트렌치는 2300 ∼ 10000Å 깊이로 형성한다. (도 2b 참조)Next, the semiconductor substrate 11 is etched using the nitride film pattern 106 as an etch mask to form the trench 107. At this time, the trench is formed to a depth of 2300 ~ 10000Å. (See Figure 2b)
다음, 상기 질화막패턴(106)을 소정 두께 리세스한다. 이때, 상기 질화막패턴(106)은 인산용액을 이용한 습식식각공정으로 200 ∼ 500Å 두께 리세스시킨다. 상기 습식식각공정은 등방성으로 실시되기 때문에 질화막패턴(106)의 상부 및 측벽이 모두 식각되어 활성영역 가장자리가 소정 두께 노출된다. (도 2c 참조)Next, the nitride film pattern 106 is recessed by a predetermined thickness. At this time, the nitride film pattern 106 is recessed 200 to 500 mm thick by a wet etching process using a phosphoric acid solution. Since the wet etching process is isotropic, both the top and sidewalls of the nitride film pattern 106 are etched to expose the edge of the active region by a predetermined thickness. (See Figure 2c)
그 다음, 전체표면 상부에 매립절연막(109)을 형성한다. 상기 매립절연막(109)은 고밀도 플라즈마 산화막으로 4000 ∼ 15000Å 형성된다. (도 2d 참조)Next, a buried insulating film 109 is formed over the entire surface. The buried insulating film 109 is formed of a high density plasma oxide film of 4000 to 15000 Å. (See FIG. 2D)
다음, 상기 매립절연막(109)을 CMP공정으로 평탄화시켜 상기 활성영역을 분리시키는 소자분리절연막(111)을 형성한다. 이때, 상기 CMP공정 후 상기 소자분리절연막(111)의 가장자리 부분이 활성영역 상에 형성된다.Next, the buried insulating film 109 is planarized by a CMP process to form a device isolation insulating film 111 that separates the active region. In this case, an edge portion of the isolation layer 111 is formed on the active region after the CMP process.
여기서, 상기 CMP공정은 상기 질화막패턴(106)을 연마장벽으로 사용하여 실시된다. 그리고, 상기 CMP공정은 컨벤셔날(conventional) 산화막용 슬러리로서, 질화막과 산화막의 연마선택비가 1 : 10 ∼ 1 : 200인 고선택비 슬러리를 사용하여 실시된다. 상기 슬러리는 SiO2, CeO2, Al2O3또는 Zr2O3를 연마제로 사용하고 산도가 pH 2 ∼ 12이다. (도 2e 참조)In this case, the CMP process is performed using the nitride film pattern 106 as an abrasive barrier. The CMP process is carried out using a high selectivity slurry having a polishing selectivity ratio of 1: 10 to 1: 200 as a slurry for a conventional oxide film. The slurry uses SiO 2 , CeO 2 , Al 2 O 3, or Zr 2 O 3 as an abrasive and has an acidity of pH 2 to 12. (See Figure 2E)
그 다음, 상기 질화막패턴(106)을 습식식각공정에 의해 제거한다. 이때, 상기 질화막패턴(106)은 인산용액을 식각용액으로 이용하고, 상기 소자분리절연막(111)과의 식각선택비 차이를 이용하여 선택적으로 제거된다. (도 2f 참조)Next, the nitride film pattern 106 is removed by a wet etching process. In this case, the nitride film pattern 106 is selectively removed by using a phosphoric acid solution as an etching solution and by using a difference in etching selectivity from the device isolation insulating layer 111. (See Figure 2f)
그 후, 세정공정을 실시한다. 이때, 상기 세정공정은 산화막 제거용액인 HF용액 또는 BOE 용액을 이용하여 실시되기 때문에 상기 패드산화막패턴(104) 및 소정 두께의 소자분리절연막(111)이 제거된다.Thereafter, a washing step is performed. At this time, since the cleaning process is performed using an HF solution or a BOE solution, which is an oxide film removing solution, the pad oxide film pattern 104 and the device isolation insulating film 111 having a predetermined thickness are removed.
여기서, 상기 세정공정이 등방성으로 실시되어도 상기 소자분리절연막(111)의 가장자리 부분이 활성영역 상에 형성되어 있으므로 소자분리절연막(111)의 가장자리 부분이 함몰되는 현상이 발생하지 않는다.Here, even if the cleaning process is performed isotropically, since the edge portion of the device isolation insulating film 111 is formed on the active region, the edge portion of the device isolation insulating film 111 does not occur.
상기 세정공정 후 상기 소자분리절연막(111)과 활성영역 간의 높이가 거의 비슷하게 형성된다. 이때, 상기 소자분리절연막(111)의 높이가 상기 활성영역을 기준으로 하여 -50 ∼ 100Å이 되도록 조절한다. (도 2g 참조)After the cleaning process, the height between the device isolation insulating layer 111 and the active region is formed to be almost the same. In this case, the height of the device isolation insulating film 111 is adjusted to be -50 to 100 kW based on the active region. (See Figure 2g)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 트렌치 식각공정을 실시하고, 소자분리마스크로 사용되는 질화막을 인산을 이용한 습식식각공정으로 소정 두께 리세스시켜 후속공정으로 형성되는 소자분리절연막의 가장자리가 반도체기판의 활성영역 상에 형성되게 함으로써 상기 질화막 제거 후 실시되는 세정공정에서 상기 소자분리절연막의 가장자리가 함몰되는 것을 방지하여 게이트전극 형성 후 소자 간에 브리지가 발생하는 것을 방지하고, 문턱전압의 증가 및 누설전류의 감소 등 소자의 전기적 특성을 향상시키는 이점이 있다.As described above, in the method of forming a device isolation insulating film of the semiconductor device according to the present invention, a trench etching process is performed, and a nitride film used as the device isolation mask is recessed by a wet etching process using phosphoric acid to be formed in a subsequent process. The edge of the isolation layer is formed on the active region of the semiconductor substrate to prevent the edge of the isolation layer from being recessed in the cleaning process performed after the nitride film is removed, thereby preventing the bridge between the elements after the gate electrode is formed. In addition, there is an advantage of improving the electrical characteristics of the device, such as increasing the threshold voltage and reducing the leakage current.
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| KR19990000764A (en) * | 1997-06-10 | 1999-01-15 | 문정환 | Device isolation method of semiconductor device |
| KR19990005813A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Trench type isolation film formation method of semiconductor device |
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