KR20000045372A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000045372A KR20000045372A KR1019980061930A KR19980061930A KR20000045372A KR 20000045372 A KR20000045372 A KR 20000045372A KR 1019980061930 A KR1019980061930 A KR 1019980061930A KR 19980061930 A KR19980061930 A KR 19980061930A KR 20000045372 A KR20000045372 A KR 20000045372A
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- trench
- oxide
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000011800 void material Substances 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 트렌치를 이용한 소자분리공정에서 다수개의 산화막 스페이서를 사용하여 트렌치의 측면 프로파일을 완만하게 형성하여 누설전류 특성을 향상시키고, 상기 트렌치를 매립하는 공정시 보이드가 발생하는 것을 방지함으로써 소자의 공정수율 및 특성을 향상시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device. In particular, in a device isolation process using a trench, the side profile of the trench is smoothly formed by using a plurality of oxide spacers to improve leakage current characteristics and to fill the trench. The present invention relates to a method for manufacturing a semiconductor device which improves the process yield and characteristics of the device by preventing the generation of voids.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.
이하, 도시되어 있지는 않지만 종래기술에 대하여 설명하기로 한다.Hereinafter, although not shown, the prior art will be described.
먼저, 반도체기판 상부에 패드산화막과 질화막의 적층구조를 형성하고, 상기 질화막 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴을 형성한다.First, a stack structure of a pad oxide film and a nitride film is formed on the semiconductor substrate, and a photosensitive film pattern is formed on the nitride film to expose a predetermined portion as a device isolation region.
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 질화막과 패드산화막 및 소정 두께의 반도체기판을 제거하여 트렌치를 형성한다. 상기 식각공정시 상기 감광막 패턴의 상부에 폴리머를 적층시켜 트렌치의 하부가 라운드하게 형성되도록 한다.Next, the trench is formed by removing the nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness using the photoresist pattern as an etching mask. During the etching process, a polymer is stacked on the photoresist pattern so that the bottom of the trench is rounded.
그 다음, 상기 폴리머 및 감광막 패턴을 제거한다.Then, the polymer and photoresist pattern are removed.
다음, 상기 트렌치의 표면을 열산화시켜 희생산화막을 성장시킨 후 습식식각을 실시하여 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.Next, the surface of the trench is thermally oxidized to grow a sacrificial oxide film and then wet etched to remove defects on the trench surface generated during the trench formation process.
그 후, 다시 열산화공정을 실시하여 상기 트렌치의 표면에 산화막을 형성한다.Thereafter, a thermal oxidation process is performed again to form an oxide film on the surface of the trench.
다음, 전체표면 상부에 상기 트렌치를 매립하는 산화막을 형성한다.Next, an oxide film filling the trench is formed on the entire surface.
그 다음, 상기 산화막을 상기 질화막을 식각방지막으로 사용하여 화학적기계적연마(chemical mechanical polishing, 이하 CMP 라함)공정을 실시하여 제거하여 소자분리절연막을 형성한다.Then, the oxide film is removed by performing a chemical mechanical polishing (CMP) process using the nitride film as an etch stop layer to form a device isolation insulating film.
다음, 소자분리영역과 반도체기판과의 단차를 줄이기 위하여 상기 소자분리절연막을 습식식각방법으로 제거한다.Next, in order to reduce the step difference between the device isolation region and the semiconductor substrate, the device isolation insulating film is removed by a wet etching method.
그 후, 상기 질화막을 제거한다.Thereafter, the nitride film is removed.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자분리를 위해 형성하는 트렌치의 프로파일이 버티칼(vertical)하게 형성되어 누설전류가 발생하기 쉽고, 또한 반도체소자가 고집적되어감에 따라 애스펙트비(aspect ratio)가 증가하여 소자분리를 위해 형성된 트렌치를 산화막으로 매립할때 보이드가 발생하여 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the method of manufacturing a semiconductor device according to the related art has a vertical profile of a trench formed for device isolation so that a leakage current is likely to occur, and as the semiconductor device becomes highly integrated, an aspect ratio ( As the aspect ratio increases, voids are generated when the trench formed for device isolation is filled with an oxide film, thereby deteriorating device characteristics and reliability.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 패드산화막/질화막/제1산화막의 적층구조를 형성하고, 상기 적층구조의 측벽에 제2산화막 스페이서를 형성한 다음, 상기 반도체기판을 소정 두께 식각하여 제1트렌치를 형성하고, 다시 상기 제2산화막 스페이서와 제1트렌치의 측벽에 제3산화막 스페이서를 형성한 다음, 상기 반도체기판을 식각하여 제2트렌치를 형성한 후, 상기 제1산화막, 제2산화막 스페이서 및 제3산화막 스페이서를 제거하여 측벽 프로파일이 완만한 트렌치를 형성하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, a stacked structure of a pad oxide film / nitride film / first oxide film is formed on the semiconductor substrate to expose a predetermined portion as a device isolation region. After forming the second oxide spacers, the semiconductor substrate is etched by a predetermined thickness to form a first trench, and then a third oxide spacer is formed on the sidewalls of the second oxide spacer and the first trench, and then the semiconductor substrate is etched. The purpose of the present invention is to provide a method of manufacturing a semiconductor device in which a trench having a smooth sidewall profile is formed by removing the first oxide film, the second oxide spacer and the third oxide spacer after forming the second trench.
도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 8 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film
15 : 질화막 17 : 제1산화막15 nitride film 17 first oxide film
19 : 제2산화막 20 : 제1트렌치19: second oxide film 20: first trench
21 : 제3산화막 22 : 제2트렌치21: third oxide film 22: second trench
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 패드산화막과 질화막 및 제1산화막의 적층구조를 형성하는 공정과,Forming a stacked structure of a pad oxide film, a nitride film, and a first oxide film exposing a portion intended as an isolation region on a semiconductor substrate;
상기 구조 상부에 제2산화막을 형성한 다음, 전면식각하여 상기 적층구조의 측벽에 제2산화막 스페이서를 형성하는 공정과,Forming a second oxide film on the structure, and then etching the entire surface to form a second oxide spacer on the sidewall of the stacked structure;
상기 제2산화막 스페이서와 적층구조를 식각마스크로 사용하여 상기 반도체기판을 소정 두께 식각하여 제1트렌치를 형성하는 공정과,Forming a first trench by etching the semiconductor substrate by a predetermined thickness using the second oxide spacer and the stacked structure as an etching mask;
상기 구조 상부에 제3산화막을 형성한 다음, 전면식각하여 상기 제2산화막 스페이서 및 제1트렌치의 측벽에 제3산화막 스페이서를 형성하는 공정과,Forming a third oxide film on the structure and then etching the entire surface to form a third oxide film spacer on sidewalls of the second oxide film spacer and the first trench;
상기 적층구조 및 제3산화막 스페이서를 식각마스크로 사용하여 상기 제1트렌치의 하부를 식각하여 제2트렌치를 형성하는 공정과,Forming a second trench by etching the lower portion of the first trench using the stacked structure and the third oxide spacer as an etch mask;
상기 제1산화막 및 제2,제3산화막 스페이서를 제거하여 트렌치의 측벽 프로파일이 완만하게 형성되도록 하는 공정을 포함하는 것을 특징으로 한다.And removing the first oxide layer and the second and third oxide layer spacers so that the sidewall profile of the trench is formed smoothly.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 8 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11) 상부에 패드산화막(13)과 질화막(15) 및 제1산화막(17)의 적층구조를 형성한다.First, a stacked structure of the pad oxide film 13, the nitride film 15, and the first oxide film 17 is formed on the semiconductor substrate 11.
다음, 소자분리영역으로 예정되는 부분을 노출시키는 소자분리마스크를 식각마스크로 이용하여 상기 적층구조를 식각하여 상기 반도체기판(11)을 노출시킨다.Next, the semiconductor substrate 11 is exposed by etching the stacked structure by using an element isolation mask that exposes a portion intended to be an element isolation region as an etching mask.
그 다음, 상기 구조 전표면에 제2산화막(19)을 소정 두께 형성한다.Next, a second thickness of the second oxide film 19 is formed on the entire surface of the structure.
그리고, 상기 제2산화막(19)을 전면식각하여 상기 적층구조의 측벽에 제2산화막(19) 스페이서를 형성한다.The second oxide film 19 is etched entirely to form a second oxide film 19 spacer on the sidewall of the stacked structure.
다음, 상기 적층구조 및 제2산화막(19) 스페이서를 식각마스크로 사용하여 상기 노출된 반도체기판(11)을 소정 두께 식각하여 제1트렌치(20)를 형성한다. 이때, 상기 제1트렌치(20)는 형성하고자 하는 트렌치의 깊이의 1/2 ∼ 1/3 정도이다.Next, the exposed semiconductor substrate 11 is etched by a predetermined thickness using the stacked structure and the second oxide film 19 spacer as an etching mask to form the first trench 20. At this time, the first trench 20 is about 1/2 to 1/3 of the depth of the trench to be formed.
그 다음, 상기 구조 전표면에 제3산화막(21)을 100 ∼ 300Å 두께로 형성한다.Next, a third oxide film 21 is formed on the entire surface of the structure to a thickness of 100 to 300 Å.
그리고, 전면식각공정으로 상기 제3산화막(21)을 식각하여 상기 제2산화막(19) 스페이서 및 제1트렌치(20)의 측벽에 제3산화막(21) 스페이서를 형성한다.The third oxide layer 21 is etched through a front surface etching process to form a third oxide layer 21 spacer on sidewalls of the second oxide layer 19 spacer and the first trench 20.
다음, 상기 적층구조 및 제3산화막(21) 스페이서를 식각마스크로 사용하여 상기 제1트렌치(20)를 식각하여 경사를 갖는 제2트렌치(22)를 형성한다. 상기 식각공정시 상기 반도체기판(11)은 상기 적층구조 및 제3산화막(21) 스페이서에 대하여 3 ∼ 6의 식각선택비를 갖도록 식각조건을 설정한다.Next, the first trench 20 is etched using the stacked structure and the third oxide film 21 spacer as an etch mask to form a second trench 22 having an inclination. During the etching process, the semiconductor substrate 11 sets etching conditions such that the semiconductor substrate 11 has an etching selectivity of 3 to 6 with respect to the stacked structure and the spacer of the third oxide film 21.
그 다음, 상기 제3산화막(21) 스페이서, 제2산화막(19) 스페이서 및 제1산화막(17)을 비.오.이.(buffered oxide etchant, 이하 BOE 라 함)용액으로 제거하되, 200 ∼ 600Å 두께가 제거되도록한다. 상기 BOE용액은 100 : 1 ∼ 300 : 1 의 낮은 농도로 상기 산화막에 대해 낮은 식각율을 갖도록하여 상기 패드산화막(13)이 식각되지 않도록한다.Then, the third oxide film 21 spacer, the second oxide film 19 spacer, and the first oxide film 17 are removed with a buffered oxide etchant (hereinafter referred to as BOE) solution. Allow 600Å of thickness to be removed. The BOE solution may have a low etching rate with respect to the oxide film at a low concentration of 100: 1 to 300: 1 to prevent the pad oxide film 13 from being etched.
다음, 상기 제2트렌치(22)의 표면을 열산화시켜 희생산화막을 성장시킨 후 습식식각을 실시하여 제거함으로써 상기 트렌치 형성공정시 발생된 상기 제2트렌치(22) 표면의 결함을 제거한다.Next, the surface of the second trench 22 is thermally oxidized to grow a sacrificial oxide film and then wet etched to remove defects on the surface of the second trench 22 generated during the trench formation process.
한편, 2개 이상의 산화막 스페이서를 사용하여 반도체기판을 식각하여 트렌치를 형성함으로써 상기 트렌치의 프로파일을 완만하게 형성할 수 있다.On the other hand, by forming a trench by etching the semiconductor substrate using two or more oxide film spacers, the trench profile can be formed smoothly.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 트렌치를 이용한 소자분리공정에서 다수개의 산화막 스페이서를 이용하여 트렌치의 프로파일을 완만하게 형성하여 누설전류 특성을 향상시키고, 후속공정으로 상기 트렌치를 매립하는 산화막형성시 보이드가 발생하는 것을 방지하여 공정수율을 향상시키며 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in the device isolation process using a trench, a trench profile is gently formed by using a plurality of oxide spacers to improve leakage current characteristics, and the trench is subsequently processed. The voids are prevented from forming when the oxide film is buried to improve the process yield, thereby improving the characteristics and reliability of the semiconductor device.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100396382B1 (en) * | 2001-11-12 | 2003-09-02 | 아남반도체 주식회사 | Formation method of trench in semiconductor device |
| KR100470160B1 (en) * | 1998-12-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Device isolation film formation method of semiconductor device |
| KR100772709B1 (en) * | 2005-12-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with isolation |
| KR100966957B1 (en) * | 2008-02-22 | 2010-06-30 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| KR100967201B1 (en) * | 2003-02-05 | 2010-07-05 | 매그나칩 반도체 유한회사 | Method for forming isolation of semiconductor device |
| US8598043B2 (en) | 2006-04-11 | 2013-12-03 | Micron Technology Inc. | Methods of forming semiconductor constructions |
| US8829643B2 (en) | 2005-09-01 | 2014-09-09 | Micron Technology, Inc. | Memory arrays |
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- 1998-12-30 KR KR1019980061930A patent/KR20000045372A/en not_active Application Discontinuation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100470160B1 (en) * | 1998-12-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Device isolation film formation method of semiconductor device |
| KR100396382B1 (en) * | 2001-11-12 | 2003-09-02 | 아남반도체 주식회사 | Formation method of trench in semiconductor device |
| KR100967201B1 (en) * | 2003-02-05 | 2010-07-05 | 매그나칩 반도체 유한회사 | Method for forming isolation of semiconductor device |
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| US11171205B2 (en) | 2005-09-01 | 2021-11-09 | Micron Technology, Inc. | Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions |
| US8829643B2 (en) | 2005-09-01 | 2014-09-09 | Micron Technology, Inc. | Memory arrays |
| US9559163B2 (en) | 2005-09-01 | 2017-01-31 | Micron Technology, Inc. | Memory arrays |
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| KR100772709B1 (en) * | 2005-12-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with isolation |
| US8598043B2 (en) | 2006-04-11 | 2013-12-03 | Micron Technology Inc. | Methods of forming semiconductor constructions |
| KR100966957B1 (en) * | 2008-02-22 | 2010-06-30 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| US7932159B2 (en) | 2008-02-22 | 2011-04-26 | Hynix Semiconductor Inc. | Flash memory device and method of fabricating the same |
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