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KR101586850B1 - Static random access memory - Google Patents

Static random access memory Download PDF

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Publication number
KR101586850B1
KR101586850B1 KR1020150079815A KR20150079815A KR101586850B1 KR 101586850 B1 KR101586850 B1 KR 101586850B1 KR 1020150079815 A KR1020150079815 A KR 1020150079815A KR 20150079815 A KR20150079815 A KR 20150079815A KR 101586850 B1 KR101586850 B1 KR 101586850B1
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South Korea
Prior art keywords
memory cell
cell array
dummy memory
potential
output
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KR1020150079815A
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Korean (ko)
Inventor
김선정
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주식회사 써니아이씨
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The controller 150 includes a pulse generator for receiving a clock signal CLK to generate a pulse signal and a P-channel MOSFET Q4 connected between a power supply terminal VCC and a ground terminal GND, Channel MOSFET Q5 and an inverter INV2 for inverting and outputting the potential at one end of the P-channel MOSFET Q4 and an output terminal TP for outputting the output of the output terminal TP for a predetermined time And an inverting section for inverting and inverting the potential of the output terminal TP held for a certain time by the holding section.

Description

[0001] STATIC RANDOM ACCESS MEMORY [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (hereinafter referred to as SRAM), and more particularly, to an SRAM capable of shortening an operation time in all operations of the SRAM.

The SRAM is a semiconductor memory device capable of holding memory data while the power is turned on and drives a word line corresponding to an input address signal to a bit line of a memory cell connected to a selected word line And the read micro-potential is amplified by the sense amplifier and output.

In the SRAM, in order to solve the problem of unevenness of the read time due to non-uniformity of the process or change of the ambient temperature, for example, a margin sufficient for the width of various drive signals for operating the SRAM, such as a word line drive signal for selecting a word line However, there is a problem in that the operation speed of the SRAM is slowed down because the word line selection time is unnecessarily long.

As a technique for solving such a problem, there is a technique described in Patent Document 1. 1 is a circuit diagram of a conventional SRAM.

1 (a), a conventional SRAM has a plurality of word lines MWL and a plurality of bit line pairs BL and BLB arranged in a direction crossing each other, and a plurality of word lines MWL and BLW, A memory cell array (10) comprising a plurality of memory cells (MC) arranged corresponding to intersections where pairs (BL, BLB) intersect; a decoder (11) for forming select signals for selecting the plurality of word lines; A driver circuit (12) for selecting and driving any one of the plurality of word lines to a predetermined level based on a signal decoded by the decoder (11) And a plurality of dummy memory cells DMC selectively driven at the same time when a word line in the memory cell array 10 is selectively driven to output a predetermined read signal.

The dummy memory cells DMC are provided in the same number as the number of memory cells MC belonging to the same column and the input and output terminals of the dummy memory cells DMC are connected to the dummy bit line pairs DBL and DBLB, The level detection inverter INV1 is connected to any one of the line pairs DBL and DBLB.

The control signal YS is set to a high level to turn on the column selection switch Qy and deactivate the sense amplifier SA so that the equalizer signal SA is generated in response to the rise of the potential of the word line MWL The equalizing MOSFET Qe and the precharge MOSFETs Qp1 and Qp2 between the bit line pair BL and BLB are turned on at the timing t1 in Fig. The bit line pair BL and BLB and the dummy bit line pair DBL and DBLB are charged to Vdd in the precharge period Tpo and the output of the level detection inverter INV1 becomes low level, The decoder 12 is enabled to select and drive the word line by the signal from the decoder 11. [

Subsequently, the potential of the bit line pair (BL, BLB) starts to change in accordance with the stored data of the selected memory cell MC of the equalized MOSFET Qe and the precharge MOSFETs Qp1, Qp2, and the dummy bit line DBL And the column selection switch Qy is turned off by lowering the control signal YS when the potential of the bit line pair BL and BLB is open to some extent (timing t2) Then, the sense amplifier SA is activated to amplify the potential difference between the bit line pair (BL, BLB) and prepare for the next read operation.

At this time, if the potential of the dummy bit line DBL becomes lower than the threshold voltage of the level detection inverter INV1, the output of the level detection inverter INV1 is inverted to the low level and the NOR gate G1 of the driver circuit 12 is inverted. Regardless of the presence or absence of a signal from the decoder 11, the output of the decoder 11 changes to the low level, so that the word line changes to the inactive state.

As described above, in Patent Document 1, since the sense amplifier is activated immediately after data is read from the selected memory cell, it is possible to shorten the reading time.

However, in the SRAM, such a problem may arise not only when the word line is selected by the row decoder but also when the bit line is selected by the column decoder and the selection operation of the sense amplifier is performed. In the prior art, only the word line drive is targeted, the application range is extremely limited, and the effect of shortening the operation time is not large.

In addition to Patent Document 1, for example, Patent Document 2 discloses a technique of operating a sense amplifier in accordance with the selection drive of a word line in a dummy memory cell. However, since this technique also applies to only a sense amplifier, there is a problem.

Patent Document 1: Japanese Patent Application Laid-Open No. 11-339476 (published on December 10, 1999) Patent Document 1: Japanese Patent Laid-Open No. 2002-367377 (published on December 20, 2002)

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and it is an object of the present invention to provide an SRAM capable of shortening the operation time in the entire process of operating the SRAM.

According to an aspect of the present invention, there is provided an SRAM including: a memory cell array having a plurality of memory cells arranged in a crossing region where a plurality of word lines and a plurality of bit line pairs intersect; A word line dummy memory cell array having a plurality of dummy memory cells; a column line dummy memory cell array arranged in a direction parallel to the bit line pairs and having a plurality of dummy memory cells; A sense amplifier for amplifying and outputting the potential of the selected bit line pair among the plurality of bit line pairs, and a sense amplifier for amplifying the potential of the selected bit line pair, An input / output circuit, and a column selection decoder, a column selection decoder, And a control section for outputting a control potential for controlling the operation of the amplifier and the input / output circuit, wherein the control section responds to a time for guaranteeing the operation of all of the plurality of memory cells, regardless of the fall of the clock signal to the inactivation level And outputs the control potential only for a period of time.

Preferably, the word line dummy memory cell array has the same number of dummy memory cells as the number of memory cells in the row direction of the memory cell array, and the column line dummy memory cell arrays are arranged in the column direction And has the same number of dummy memory cells as the number of memory cells.

Preferably, the control unit includes: a pulse generator that receives a clock signal and generates a pulse signal; a discharging unit that forms a discharge path between a power supply end and a ground end; and a control unit that inverts and outputs the potential of one end of the discharge unit A holding unit for holding the output potential of the output terminal for a predetermined time and an inverting unit for feeding back the potential of the output terminal held for a predetermined time by the holding unit and inverting the potential.

Preferably, the pulse generator receives the inverted clock signal, the non-inverted clock signal, and the inverted chip enable signal, and generates and outputs a pulse signal in accordance with the potential level of the input signal.

Preferably, a time corresponding to a time for assuring operation of all of the plurality of memory cells is a time for assuring operation of the plurality of dummy memory cells of the word line dummy memory cell array and the column line dummy memory cell array, The holding unit holds the output of the output stage for a period of time ensuring operation of the plurality of dummy memory cells of the word line dummy memory cell array and the column line dummy memory cell array.

According to the present invention, since the output potential of the control section for selectively driving each section of the SRAM is maintained at a high level only for a time period during which the operation of all the memory cells of the memory cell array can be guaranteed, the memory of the memory cell array constituting the SRAM It is possible to shorten the operation time in all processes of writing information in the cell or reading the written information.

1 is a circuit diagram of a conventional SRAM,
2 is a circuit configuration diagram of an SRAM according to a preferred embodiment of the present invention,
FIG. 3 is a detailed circuit diagram of the control unit of FIG. 2,
4 is a timing chart showing the operation timing of the circuit diagram of Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the overall structure of the SRAM of the present invention will be described. FIG. 2 is a circuit block diagram of an SRAM according to a preferred embodiment of the present invention, and FIG. 3 is a detailed circuit diagram of the control block of FIG.

2, the SRAM 100 of the present embodiment includes a plurality of word lines WLm (m = 0 to i) and a plurality of bit line pairs BLn and BLnB (n = 0 to j) And a memory cell array 110 having a plurality of memory cells MC arranged in a matrix in an intersecting region where a plurality of word lines WLm and a plurality of bit line pairs BLn and BLnB cross each other.

Although not shown in FIG. 2, the memory cell MC has six transistors, and two CMOS inverters are cross-connected to constitute a latch circuit. A pair of nodes of the latch circuit are connected to two transfer gates ) Transistors to the bit line pairs BLn and BLnB, and the gate of the transfer gate transistor is connected to the word line WLm. However, the structure of the memory cell MC is not limited to this, and may be a memory cell of another structure.

The row selection decoder 120 is connected to a plurality of word lines WLm and selectively drives any one of the plurality of word lines WLm under the control of the control unit 150 to be described later, The transfer gate transistors of the connected memory cells MC are turned on and the bit line pairs BLn and BLnB are driven by the latch circuits in the memory cells MC so that a constant potential difference is generated in the bit line pairs.

The column selection decoder 130 is connected to a plurality of bit line pairs BLn and BLnB and selects one of a plurality of bit line pairs BLn and BLnB under the control of a control unit 150 The selected bit line pair is connected to the sense amplifier and the input / output circuit 140. The sense amplifier and the input / output circuit 140 amplify the voltage of the selected bit line pair (BLn, BLnB) under the control of the control unit 150 Output.

2, in addition to the function of amplifying the voltage of the selected bit line pair (BLn, BLnB) by the sense amplifier and the input / output circuit 140, a function as an input / output circuit for controlling the input and output of data to the memory cell array 110 However, this is for the convenience of description of the present invention, and the input and buffer circuits having the input and buffer functions and the output and buffer circuits having the output and buffer functions may be separately configured. In addition, And thus may further include other circuits.

The SRAM 100 according to the present embodiment includes a word line dummy memory cell array 160 arranged outside the memory cell array 110 in parallel with the word lines WLm and a bit line memory cell array 160 arranged outside the memory cell array 110, And a column line dummy memory cell array 170 arranged in parallel with the line pairs BLn and BLnB.

The word line dummy memory cell array 160 has a dummy word line DWL arranged in a direction parallel to the word line WLm and the dummy word line DWL is connected to the memory cell array 110 in the row direction of the memory cell array 110. [ The same number of dummy memory cells DMC as the number of cells MC are connected. Both ends A and B of the dummy word line DWL of the word line dummy memory cell array 160 are connected to the control unit 150 described later.

The column line dummy memory cell array 170 has dummy bit line pairs DBL and DBLB arranged in the same direction as the bit line pairs BLn and BLnB and the dummy bit line pairs DBL and DBLB are connected to the memory cell array The same number of dummy memory cells DMC as the number of memory cells MC in the column direction of the memory cell array 110 are connected. Both ends C and D of the dummy bit line DBL among the dummy bit line pairs DBL and DBLB of the column line dummy memory cell array 170 are connected to the control unit 150 to be described later, DBLB) is not used.

The control unit 150 is connected to the row selection decoder 120 and the column selection decoder 130 and the sense amplifier and the input and output circuit 140. The control unit 150 operates in accordance with the clock signal CLK input from the outside, ), The column select decoder 130, the sense amplifier, and the input / output circuit 140, and is responsible for the power consumption reduction function of the present invention.

In the actual SRAM, various control signals including address information for selecting a plurality of word lines (WLm) and a plurality of bit line pairs (BLn, BLnB) are input to the control section together with the clock signal (CLK) The operations of the row selection decoder 120, the column selection decoder 130, the sense amplifier, and the input / output circuit 140 are controlled by the synchronization of the various control signals and the clock signal CLK. However, Detailed description of various control signals including these address information will be omitted.

Next, details of the control unit 150 will be described with reference to FIG.

The controller 150 includes a pulse generator that receives a clock signal CLK and generates a pulse signal and a pulse generator that is connected between a power supply terminal VCC and a ground terminal GND to form a discharge path, An output terminal TP (including a discharging means in which an N-channel MOSFET Q5 is connected in series) and an inverter INV2 for inverting the potential at the connection end of the P-channel MOSFET Q4 and the N-channel MOSFET Q5 of the discharging means A holding section for holding the output potential of the output terminal TP for a predetermined time and an inverting section for feeding back the output potential of the output terminal TP held for a certain time by the holding section and inverting the output potential. In FIG. 3, an output terminal TP is shown at four places, but this is for convenience of illustration, and the four output terminals TP are one interconnected stage.

The pulse generator is composed of a NAND gate NAND1 (hereinafter referred to as a NAND gate NAND1) for generating a pulse signal with an inverted signal obtained by inverting the clock signal CLK by the inverter INV1 and a non-inverted signal not inverted by the inverter INV1 ) Is referred to as a node P), and the node P is connected to the gate terminal of the N-channel MOSFET Q5 constituting the discharging means to be described later.

The discharging means has a configuration in which one P-channel MOSFET Q4 and an N-channel MOSFET Q5 are connected in series between the power supply terminal (VCC) and the ground terminal (GND), and the gate terminal of the P- And the gate terminal of the N-channel MOSFET Q5 is connected to the node P.

The output stage TP includes an inverter INV2 for inverting and outputting the potential at the connection point of the P-channel MOSFET Q4 and the N-channel MOSFET Q5, and the output of the output stage TP is connected to the row selection decoder 120 ), The column selection decoder 130, the sense amplifier and the input / output circuit 140, and is also fed back to the inputs of the inverting and holding units. The inverters INV6 and INV7 connected to the output terminal TP are means for preventing each MOSFET of the discharging means from becoming a floating state.

The holding section inverts the potentials of the P-channel MOSFET Q1 and the N-channel MOSFET Q2 and the output terminal TP connected in series between the power supply terminal (VCC) and the ground terminal (GND) An inverter INV5 for inverting the potential at the output terminal TP and a word line dummy memory for inputting the inverted potential of the inverter INV5 to the gate terminal of the N-channel MOSFET Q2 with a predetermined time delay, And a column line dummy memory cell array 170 for delaying the potential of the connection end of the cell array 160, the P-channel MOSFET Q1, and the N-channel MOSFET Q2 by a predetermined time and inputting them to the inverting unit.

Here, both ends of the word line dummy memory cell array 160 are connected to the A and B terminals of the word line dummy memory cell array 160 of FIG. 2, respectively, and both ends of the column line dummy memory cell array 170 are connected to the The column line dummy memory cell array 170 is connected to the C and D terminals of the column line dummy memory cell array 170, respectively. The N-channel MOSFET Q3 is a stabilizing unit for stabilizing the operation of the holding unit.

The inverting unit inputs the potential of the output stage TP held for a predetermined time by the holding unit to the inverted potential obtained by inverting the output of the inverter INV3 (hereinafter referred to as node M) and the potential of the output stage TP And a NAND gate NAND2 (hereinafter referred to as node Q) for outputting the inverted potential.

Next, the operation of the control unit 150 having the above configuration will be described in detail with reference to FIG. 3 and FIG.

At time t1 in Fig. 4, the clock signal CLK, the potential of the node M and the output terminal TP are maintained at the low level, and the potential of the node Q is set at the high level.

As the clock signal CLK rises from the low level to the high level at the time t2, the gate Q of the P-channel MOSFET Q4 of the discharge path and the gate ends of the N-channel MOSFET Q2 and the N-channel MOSFET Q3 A high level potential is applied.

At a time t3 delayed by a certain time from the rise of the clock signal CLK, a high-level pulse signal is output to the node P, which is the output terminal of the pulse generator. By this, the N-channel MOSFET Q5 is activated, The potential of the output terminal TP rises from the low level to the high level, so that the control unit 150 can control the row selection decoder 120, the column selection decoder 130, The sense amplifier and the input / output circuit 140 are selectively controlled to start necessary operations.

The high level potential of the output terminal TP is fed back to the inputs of the holding part and the inverting part. That is, the high-level output of the output terminal TP turns the P-channel MOSFET Q1 in the inactive state via the inverter INV4 of the holding part and is also turned off by the inverter INV5 and the word line dummy memory cell array 160 The N channel MOSFET Q2 is activated with a predetermined delay, so that the output of the holding unit is lowered to the low level with a predetermined time delay by the column line dummy memory cell array 170 (time t4).

At time t4, as the output of the holding part falls to the low level, the potential of the node M, which is the output terminal of the inverter INV3 of the inverting part, rises to the high level and the potential of the node Q which is the output of the inverting part falls to the low level, The potential of the output terminal TP falls to the low level at time t4 to stop the supply of the operation voltage supplied to the row selection decoder 120, the column selection decoder 130, the sense amplifier, and the input / output circuit 140.

Subsequently, at time t5, the clock signal CLK falls to the low level.

The output of the control unit for controlling the operation of the row selection decoder 120, the column selection decoder 130 and the sense amplifier and the input / output circuit 140 is indicated by a dotted line in Fig. 4 And falls to the low level in synchronization with the fall of the clock signal CLK to the low level (time t5). In other words, when there is no control unit 150 of the present embodiment, the output of the control unit changes in synchronization with the clock signal CLK.

However, according to the control section 150 of the present embodiment, the output potential of the control section 150 is supplied to the word line dummy memory cell array 160 and the column line dummy memory cell array (not shown) regardless of the falling timing of the clock signal CLK 170 is maintained at a high level only for a period of time that can guarantee the operation of all the dummy memory cells DMC.

In the present embodiment, the number of dummy memory cells DMC of the word line dummy memory cell array 160 and the column line dummy memory cell array 170 is the same as the number of dummy memory cells DMC in the row direction and column direction memory The control unit 150 outputs a high level potential only for a period of time that can guarantee the operation of all the memory cells MC of the memory cell array 110, The output of the output terminal TP of 4 is shortened by the time indicated by the dotted line (time between time t4 and time t5).

Therefore, according to the SRAM 100 of the present invention, in all the operations of writing information to the memory cell MC of the memory cell array 110 and reading the written information, the dotted line (output waveform of TP) The operation time corresponding to the displayed time can be shortened.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and variations are possible within the scope of the technical idea described in the claims.

For example, although the chip enable signal CEN is a negative signal in the above embodiment, the signal may be a positive signal in accordance with the specification of the SRAM. Accordingly, the specific circuit configuration of each section of the control section 150 is appropriately changed and modified Can be achieved.

Also, for example, it is possible to change the types of MOSFETs constituting the control unit 150.

100 SRAM
110 memory cell array
120 row select decoder
130 column select decoder
140 sense amplifier and input / output circuit
150 control unit
160 word line dummy memory cell array
170 column line dummy memory cell array
MC memory cell
DMC dummy memory cell

Claims (5)

A memory cell array having a plurality of memory cells arranged in an intersecting area where a plurality of word lines and a plurality of bit line pairs intersect;
A word line dummy memory cell array arranged in a direction parallel to the word lines and having a plurality of dummy memory cells;
A column line dummy memory cell array arranged in a direction parallel to the pair of bit lines and having a plurality of dummy memory cells;
A row selection decoder for selectively driving any one of the plurality of word lines,
A column selection decoder for selectively driving any one of a plurality of bit line pairs,
A sense amplifier and an input / output circuit for amplifying and outputting the potential of the selected bit line pair among a plurality of bit line pairs,
And a control section for outputting a control potential for controlling operations of the row selection decoder, the column selection decoder, the sense amplifier, and the input / output circuit in synchronization with a clock signal applied from the outside,
Wherein,
A pulse generator that receives a clock signal and generates a pulse signal;
A discharge means for forming a discharge path between the power supply terminal and the ground terminal,
An output terminal for inverting and outputting the potential at one end of the discharging means,
A holding unit for holding the output potential of the output terminal for a predetermined time;
And an inverting unit for inverting the potential of the output terminal held for a predetermined time by the holding unit,
Wherein the holding section holds the output of the output stage for a period of time to assure operation of the plurality of dummy memory cells of the word line dummy memory cell array and the column line dummy memory cell array irrespective of falling of the clock signal to the inactivation level To the static random access memory. The method according to claim 1,
The word line dummy memory cell array has the same number of dummy memory cells as the number of memory cells in the row direction of the memory cell array,
Wherein the column line dummy memory cell array has the same number of dummy memory cells as the number of memory cells in the column direction of the memory cell array. delete The method according to claim 1,
Wherein the pulse generator generates a pulse signal in accordance with a potential level of the input signal and receives the inverted clock signal obtained by inverting the clock signal and the clock signal. delete
KR1020150079815A 2015-06-05 2015-06-05 Static random access memory KR101586850B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11339476A (en) 1998-05-29 1999-12-10 Hitachi Ltd Semiconductor memory device
JP2002367377A (en) 2001-06-12 2002-12-20 Fujitsu Ltd Static ram
JP2003323792A (en) * 2002-04-30 2003-11-14 Mitsubishi Electric Corp Semiconductor storage device
KR20090077834A (en) * 2006-10-25 2009-07-15 콸콤 인코포레이티드 Memory device with configurable delay tracking
KR101253533B1 (en) * 2007-05-31 2013-04-11 퀄컴 인코포레이티드 Memory device with delay tracking for improved timing margin

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11339476A (en) 1998-05-29 1999-12-10 Hitachi Ltd Semiconductor memory device
JP2002367377A (en) 2001-06-12 2002-12-20 Fujitsu Ltd Static ram
US6556472B2 (en) * 2001-06-12 2003-04-29 Fujitsu Limited Static RAM with optimized timing of driving control signal for sense amplifier
JP2003323792A (en) * 2002-04-30 2003-11-14 Mitsubishi Electric Corp Semiconductor storage device
KR20090077834A (en) * 2006-10-25 2009-07-15 콸콤 인코포레이티드 Memory device with configurable delay tracking
KR101253533B1 (en) * 2007-05-31 2013-04-11 퀄컴 인코포레이티드 Memory device with delay tracking for improved timing margin

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