JP2007019997A - Field-effect transistor circuit and designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set a threshold voltage according to the operation state of a field-effect transistor. <P>SOLUTION: This field-effect transistor circuit has a plurality of field-effect transistors. The field-effect transistor circuit includes field-effect transistors having a plurality of threshold voltages in which each threshold voltage is set according to periods of an on-operation state and an off-operation state on a time-axis of the field-effect transistor or in a stochastic way, so that a leak current at the off-time of the field-effect transistor can be reduced, and operation speed can be improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor circuit having a threshold voltage and a design method thereof, and in particular, sets Multi-Vth (multi-threshold voltage) of a field effect transistor based on a period of an operating state of the circuit.

Introducing Multi-Vth (multi-threshold voltage) technology, the amount of delay has been calculated in the past, and a field effect Tr (transistor) with a low threshold voltage is provided for the delay (delay) in the path where the delay (delay) is not sufficient. Patent Document 1 discloses a technique for reducing leakage current and power consumption by using a field effect transistor having a high threshold voltage for a certain path.
However, in a fully optimized circuit block such as a static random access memory (SRAM) circuit, all are critical paths, and thus there is a problem that the multi-Vth technique cannot be applied.

In a conventional SRAM, for example, a word line (line) driver circuit (word line drive circuit) or the like is divided into, for example, p (p is a positive integer) word line groups, and this word line group includes q ( q is a positive integer) word line. One specific word line group is selected from p by the predecoder, and one word line is selected by a word address decoded using a part of the data of the word address.
At this time, since only one specific word line group is in an active state, it is not necessary to simultaneously activate other q-1 word line groups, so that the power consumption is reduced to 1 / pq in total. Reduced.
However, the threshold voltages of the field effect transistors (transistors) constituting the word line driver circuit of the selected word line group are all set to the same value in each conductivity type. For this reason, when the OFF period is long, there is a leakage current associated with the threshold voltage of the output (field effect) transistor. In particular, when the threshold voltage is low, the leakage current increases and the current consumption increases accordingly. There are increasing disadvantages.

In the above example, if the threshold voltage of all output (field effect) transistors is varied, for example, if the threshold voltage is increased, the leakage current at the time of OFF is suppressed, but the operation speed becomes slow and it takes time to select a word line or the like. There is a problem that the writing / reading speed becomes slow.
On the other hand, when the threshold voltage is reduced, the operating speed is increased, but the leakage current at OFF is increased.
As described above, when the threshold voltage of the field effect transistor is uniformly increased or decreased in the circuit, it is impossible to achieve both reduction of the circuit leakage current and improvement of the operation speed.
Japanese Patent Laid-Open No. 11-195976 JP-A-10-199247

The transition state of the circuit, for example, on the time axis or the stochastic ON state and OFF state of the field effect transistor constituting the circuit is investigated, and the field effect transistor having a long ON state period is set to a low threshold voltage (Low Vth), Further, by applying a high threshold voltage (High Vth) to each of the field effect transistors having a long OFF state, leakage current and current consumption are reduced.
In the case of a circuit synchronized with a pulse-type clock, the field effect transistors in the circuit are turned on only when the clock pulse is active (short time), and are turned off at other times. Yes. For such a field effect transistor, a high Vth (Hvth; high threshold voltage) field effect transistor is applied to reduce leakage current.
On the other hand, a field effect transistor of Low Vth (Lvth; low threshold voltage) is applied to a field effect transistor that is in an OFF state when the clock pulse is Active and is in an ON state at other times, thereby improving speed. Do.

The field effect transistor circuit according to the present invention is a field effect transistor circuit having a plurality of field effect transistors, wherein the threshold voltage depends on the time axis of the field effect transistor or the period between the on operation state and the off operation state. And a plurality of threshold voltage field effect transistors.
The field effect transistor circuit of the present invention is a field effect transistor circuit having a plurality of field effect transistors, wherein the field effect transistor circuit has an electric field having an off operation period longer than the on operation period on the time axis or stochastically. The effect transistor is a field effect transistor having a high threshold voltage, and a field effect transistor having a low threshold voltage is used for a field effect transistor having a longer on-operation period than an off-operation period. It has a field effect transistor with a threshold voltage.
The field effect transistor circuit design method of the present invention includes a first step of verifying a circuit transition state, and a field effect transistor having a long on or off operation state on the time axis or probabilistically by the verification. And a third step of setting a threshold voltage of the specified field effect transistor corresponding to the period of the on / off operation state.

  By applying the Multi-Vth technology to the output transistor of the drive circuit, for example, even when the circuit block is sufficiently optimized and all are critical paths, a field effect transistor such as a Multi-Vth CMOS (Complementary Metal Oxide Semiconductor) is used. The leakage current can be reduced by the transistor, the current consumption can be reduced, and the speed can be improved.

FIG. 1 shows a configuration of a circuit block of an SRAM (Static Random Access Memory) 10 as an embodiment.
An SRAM (circuit) 10 shown in FIG. 1 includes a word line driver (Word Driver) circuit 20, a decoder (Decode) / control (control) circuit 30, a write buffer (Write Buffer) / sense amplifier (SenseAmp) 50, a memory. The cell unit 40 is configured.
In Figure 1, for simplicity, although only one word line driver (Word Driver) circuit 20 and the memory block BLK1 not shown, actually a memory block in which the word lines are arranged ^{2 3} units (BLK1) is There are 2 ⁿ / 2 ³ pieces. In Figure 1, the word line is present ^{2 3} in the block (BLK1～BLKn) of the word line driver, a memory cell MC (41 against Yes illustrated with WLO to WL7, also each of the word lines (lines) -00, 41-10, ..., 41-70, ...) are connected.
The decoder / control circuit 30 comprises a predecoder, an internal timing control circuit, etc., receives address data and decodes it, and generates an internal clock signal, a control signal, etc. with reference to the external clock CK.
In the Decode circuit, there is no predecoder, and there is a method of directly decoding with an internal address signal generated in an address buffer.
However, in order to reduce the number of transistors constituting the decoder, reduce the area, and operate at high speed, a predecoder method is generally used for the purpose of increasing the storage capacity, increasing the speed, and reducing the power consumption.
When a multi-bit address is input, this pre-decoder decodes (pre-decodes), for example, into groups of 2 bits or 3 bits, selects a specific group from the group, and selects the selected group. In this configuration, one word line is selected from 2-bit or 3-bit word lines. Thereby, power consumption is reduced.
In addition, if the number of bits in the selected decoding unit is reduced, the load on the address buffer can be reduced and the operation speed can be increased. On the other hand, if the number of bits in the decoding unit is increased, the wiring area can be reduced. The load increases and the operation speed slows down. For this reason, the word lines in one block constituted by the word line driver circuit 20 often have 2 or 3 bit configurations as described above.
In addition to the row address decoder, there is a column address decoder. The column address decoder selects a column (column direction) address based on the input address data.
When the external control signal Control and the clock CK signal are supplied, the timing control circuit of the Control (control) circuit decodes, for example, a control signal (WE; write enable signal) and supplies it to the predecoder and the word line driver circuit 20. The address signals A [0] to A [n] are decoded to output a signal for activating or deactivating the word line.
In addition to this, a clock PCLK is generated, a control signal WE (write enable) signal is output to a write buffer (write buffer), and the write timing is controlled.
In addition, a SenseAmp enable signal is output to a SenseAmp circuit 50 that amplifies data on the bit line pair BL, XBL (inversion of BL).
Further, a timing signal for controlling the column addresses [An + 1] to [Am] (data) output from the column decoder is output.

One word line driver (Word Driver) circuit 20 is selected by the predecoder, and clocks PCLK and DATA output from the decoder / control circuit 30 are supplied to the selected specific word line driver circuit 20.
In the selected block of the word line driver circuit 20, for example, when the unit of the decoder is 3 bits, by supplying an “H” (high) level voltage from 8 word lines to one word line, One of the memory cells MC (41-00 to 41-70) 40 is activated (activated). At the same time, the other seven word lines are supplied with an "L" (low) level voltage and are deactivated.
Each word line driver circuit has a NAND circuit and a NOT circuit as shown in FIGS. 1 and 2 as an example.
In the word line driver circuit 20, the control signal (clock) PCLK and data DATA output from the decoder / control circuit 30 are supplied to the NAND circuit and operated, and then the logical result is inverted by the NOT circuit to be converted into the memory cell MC ( 41-00, 41-10,...) To the word lines WL0 to WL7 that drive the unit 40.

A write buffer circuit constituting a part of the write buffer / sense amplifier (circuit) 50 is supplied with a write enable (WE) signal and a column selection signal from a column decoder. When a specific column is selected, input data Din (In (Complementary) data is output to the bit line pair BL, XBL in the memory cell MC.
As described above, for example, based on a signal from the internal timing control circuit, the data of the selected memory cell MC is output onto the bit line pair BL, XBL, and this data is amplified by the sense amplifier circuit (50). Dout (output) data is output through the output buffer of the write buffer / sense amplifier circuit 50.
On the other hand, at the time of writing, the data signal In is supplied to the write buffer / sense amplifier circuit 50 via the input terminal. When the bit line pair BL, XBL is selected by the column selection signal, data is written into the memory cell MC via the write buffer circuit.

In the memory cell (MC) unit 40, for example, a plurality of memory cells MC41-00 to MC41-nm such as SRAM cells and ROM cells are arranged in a matrix, and MC41-00 to MC41-0m are generally connected to the same word line. MC-00 to MC-n0 are connected to the bit line pair BL, XBL, and the bit line pair BL, XBL is connected to the sense amplifier (50).
The example of the memory cell (MC) unit 40 in FIG. 1 shows only one column of SRAM, and a plurality of columns are configured, and the memory cells MC41-00 to MC41-nm have a CMOS circuit configuration. .
Memory cells MC41-00 to MC41-nm are composed of P-channel MOS (Metal Oxide Semiconductor) transistors 43, 45 and N-channel MOS transistors 42, 44, 46, 47.
The word lines (WL0 to WL7) are connected to the gates of the NMOS transistors 42 and 47, and the bit lines BL and XBL are connected to the drains / sources of the NMOS transistors 42 and 47.
The source of the PMOS transistor 43 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor 44 and the source / drain of the NMOS transistor 42. The source of the NMOS transistor 44 is connected to a reference potential such as GND (ground).
Similarly, the source of the PMOS transistor 45 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor 46 and the source / drain of the NMOS transistor 47. The source of the NMOS transistor 46 is connected to a reference potential such as GND (ground).
The gates of the PMOS transistor 43 and the NMOS transistor 44 are commonly connected, and the commonly connected gate is connected to the drain to which the PMOS transistor 45 and the NMOS transistor 46 are commonly connected.
The gates of the PMOS transistor 45 and the NMOS transistor 46 are commonly connected, and the commonly connected gate is connected to the drain to which the PMOS transistor 43 and the NMOS transistor 44 are commonly connected.
The memory cell MC stores data statically by this cross-coupled circuit configuration.

Next, the operation of the SRAM circuit 10 shown in FIG. 1 will be described.
When address data, a clock PCLK, and a control signal are supplied to the decoder / control circuit 30, a predecoder circuit, a 3to8 decoder circuit, a column decoder circuit, and the like are driven, and the result is a word line driver (circuit) 20 and a write buffer / This is supplied to the sense amplifier circuit 50.
Specifically, the clocks PCLK and DATA are output from the decoder / control circuit 30 to the word line driver. In the predecoder circuit of the decoder circuit, one block is selected from the word line blocks BLK1 to BLKn.
In addition, the decoding operation of the decoder / control circuit 30, the word line driver block word line (line), for example one in 2 ³ eight is selected.
Therefore, the leakage current can be reduced by changing the threshold voltage of the transistor having the long OFF period and the OFF period constituting the word line driver circuit 20. Details will be described later.
When one block is selected from each block of the word line driver, PCLK and DATA are input to the NAND circuit 21 and the output of the NAND circuit 21 is inverted by the NOT circuit 22 as shown in FIG. is, the row direction of the address in the block is selected one from the 2 ^{3 (=} 8) present, the word line is to "H" (a high-) level and the activation.
When there are eight word lines, only one word line is selected and the remaining seven are deactivated. Therefore, the number of probabilistically activated lines is 1/8.
As described above, where there are many circuit blocks that are stochastically inactivated, for example, as an example of the SRM circuit 10, the threshold value of a transistor having a probability of a long OFF period among transistors constituting a word line driver. By varying the voltage, leakage current can be reduced. This will be described in detail later with reference to the drawings.

In the column direction, a bit line pair selected by a column address is selected, and a memory cell MC to be read (or written) is selected.
For example, in the case of data reading, when a sense amplifier enable signal is output from the internal timing control circuit, the data of the specified memory cell MC is output to the bit line pair BL, XBL. The sense amplifier amplifies the data of the memory cell MC output to the bit line pair BL, XBL. The amplified data is output as output data (Dout) through the buffer.
For data writing, only one row is selected by the row decoder, and one column is selected by the column decoder circuit to specify the memory cell MC. When the input data In is input from the write buffer / sense amplifier circuit 50, the input data In is transferred to the bit line pair BL, XBL in response to a write enable (WE; writable) signal, and the selected memory cell MC ( 41-00, 41-10, ...).
In this case, since the amplitude level of the data is large, the sense amplifier is not used unlike reading.

FIG. 2 shows a more detailed circuit configuration regarding the decoder (/ control) circuit 30 and the word line driver circuit (20) shown in FIG.
In FIG. 2, the decoder (/ control) circuit 30 includes a predecoder circuit 152, a 3 to 8 decoder (circuit) 151, and a column decoder (circuit) 153.
Each word line driver block is selected by a predecoder circuit 152. The word line driver circuit 20 is composed of, for example, a drive circuit for driving each of 2 ³ (3 bit addresses; 8) word lines.
One block is selected from among BLK1 (120-1) to BLKn (120-n) based on the address signal, and the word line in the selected block is further replaced with a 3 (bit) to8 decoder circuit 151. One of the books is selected, and an “H” level voltage is output to the word lines (WL0 to WL7) to be activated.
The eight row selection lines 0 to 7 output from the 3to8 decoder circuit 151 are connected to all the blocks BLK1 (120-1) to BLKn (120-n) shown in FIG. 2 and output address data (DATA). To do. This DATA is NAND-processed and NOT-processed in synchronization with the timing clock output from the timing generator (TG) 110, PCLK, and as a result, only one of the eight is activated.
The column decoder circuit 153 is decoded by the address data An + 1 to Am to select a column. In the output circuit of the column decoder circuit 153, as in the above-described word line driver circuit, by changing the threshold voltage of a transistor having a long OFF operation period stochastically, for example, by increasing the transistor constituting the transistor, Leakage current can be reduced, and accordingly, current consumption (power consumption) can be reduced.

FIG. 3 shows a decoder circuit 200 according to an embodiment of the present invention and its circuit configuration.
As shown in FIG. 3A, the decoder circuit 201 (200) receives 3-bit input data In300, In301, and In302. The 3-bit input data is decoded, and eight output data (signals) Out303,..., Out310 are output. Of the eight output data, only one is selected and, for example, an “H” level voltage is output.
The “H” level voltage is output as DATA to the word line driver circuit, where it is input to the NAND circuit together with PCLK, and the “H” level voltage is output to the word line via the NOT circuit and activated.

The circuit configuration of the output stage of the decoder (Decode) circuit 201 (200) is, for example, an INV (inverter) circuit, as shown in FIGS.
For example, when the INV circuit has a CMOS circuit configuration, the source of the PMOS transistor 210 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 211, and the gate is commonly connected to the gate of the NMOS transistor 211. The source of the NMOS transistor 211 is connected to a reference potential such as GND (ground).
FIG. 3B and FIG. 3C show the operation states of the transistors corresponding to the input and output states of the INV circuit.
First, when an “L” level signal (data) is supplied to the input, the PMOS transistor 210 is in the ON operation state, while the NMOS transistor 211 is in the OFF operation state, and as a result, the output is in the “H” level state (FIG. 3 (B)).
On the other hand, when an “H” level signal (data) is supplied to the input, the PMOS transistor 210 is in the OFF operation state, while the NMOS transistor 211 is in the ON operation state, and as a result, the output is in the “L” level state ( FIG. 3 (C)).

As described above, eight inverter (INV) circuits in the output section of the decoder circuit 201 are configured, and one selected from the output data Out303 to Out310 is at “H” level according to the input data IN300 to In302 ( 3 (B)) and the remaining seven are at the “L” level (FIG. 3C).
More specifically, since seven of the eight inverter circuits of the output circuit of the decoder circuit 201 are at the “L” level, the seven PMOS transistors 210 are in the OFF operation state. The NMOS transistor 211 is in an ON operation state.

As described above, when the output circuit of the decoder circuit 201 has an inverter circuit configuration and a CMOS circuit, most of the inverter circuits that drive the word line driver circuit are OFF, and a certain conductivity type that constitutes the inverter circuit. In the case of a transistor or CMOS transistor configuration, most of the PMOS transistors are in the OFF state.
As described above, the INV circuit of the output circuit that constitutes the decoder circuit 201 has a large number of transistors that are stochastically in the OFF operation state, or has a long period of being in the OFF operation state when the total is added.
3B and 3C, when the threshold voltage is increased for a transistor having a long OFF operation period, for example, the PMOS transistor 210, the current at a predetermined gate bias increases as the threshold voltage increases. As a result, the leakage current at OFF also decreases.
On the other hand, seven of the eight inverter circuits are in the OFF state. In the seven output CMOS circuits, the NMOS transistor 211 is in the ON operation state.
The total ON period of the seven NMOS transistors 211 stochastically increases the ON operation state time. For the NMOS transistor 211, the operation speed can be reduced by lowering the threshold voltage than reducing the leakage current. Speed up and speed improvement.

FIG. 4 shows a circuit configuration of a word line driver circuit (250) which is another embodiment.
4, the word line driver circuit 250 includes a NAND circuit 21 (NAND1-0 to NAND1-7,..., NANDn-0 to NANDn-7) and a NOT circuit 22 (NOT1). -0 to NOT1-7, ..., NOTn-0 to NOTn-7).
This word line driver circuit 250 is constituted by a CMOS circuit of a PMOS transistor and an NMOS transistor.
In the NAND circuit (NAND1-0 to NAND1-7,..., NANDn-0 to NANDn-7), the source of the PMOS transistor 251 is connected to the power supply VDD, and the drain is the drain of the NMOS transistor 252 and the drain of the PMOS transistor 253. It is connected to the.
The gate of the NMOS transistor 252 is connected to the gate of the PMOS transistor 251, and the drain is connected to the drain of the NMOS transistor 254.
The source of the NMOS transistor 254 is connected to a reference potential, for example, GND, and the gate is connected to the gate of the PMOS transistor 253.
The source of the PMOS transistor 253 is connected to the power supply VDD, and the drain is connected to the gate of the PMOS transistor 255 and the gate of the NMOS transistor 256.

For example, PCLK data is input to the commonly connected gates of the PMOS transistor 251 and the NMOS transistor 252 constituting the NAND circuit, and DATA (data) is input to the commonly connected gates of the PMOS transistor 253 and the NMOS transistor 254. The
The threshold voltage of the PMOS transistor 251 constituting the NAND circuit (NAND1-0 to NAND1-7,..., NANDn-0 to NANDn-7) is lowered (Lvth), while the threshold voltage of the NMOS transistor 252 is reduced. Is set high (Hvth).
The PCLK data corresponds to a clock output from the timing generator 110 shown in FIG. 2, and DATA corresponds to data for word line selection output from the 3to8 decoder circuit 151.

The PMOS transistor 255 and the NMOS transistor 256 constitute a NOT circuit, the source of the PMOS transistor 255 is connected to the power supply VDD, and the drain is connected to the drain of the NMOS transistor 256 and the output terminal (OUT). The source of 256 is connected to a reference potential such as GND.
The input of the NOT circuit, that is, the gates of the PMOS transistor 255 and the NMOS transistor 256 are connected in common, and the output data of the NAND circuit is supplied to this gate.

Next, operations of the NAND circuit and the NOT circuit included in the word line driver circuit 250 will be described with reference to a timing chart shown in FIG.
Prior to time t0, both PCLK and DATA are at “L” level (FIGS. 5A and 5B), and “L” level data (voltage) of PCLK is applied to the gates of PMOS transistor 251 and NMOS transistor 252. To be supplied. As a result, the PMOS transistor 251 is turned on and the NMOS transistor 252 is turned off.
On the other hand, the “L” level voltage of DATA is supplied to the gate of the PMOS transistor 253 and the gate of the NMOS transistor 254 at this time. As a result, the PMOS transistor 253 is turned on and the NMOS transistor 254 is turned off.
Accordingly, the NMOS transistors 252 and 254 are in the OFF operation state, and the PMOS transistors 251 and 253 are in the ON operation state, so that the output of the NAND circuit becomes “H” level.
However, since the “H” level voltage output from the NAND circuit is inverted by the NOT circuit configured by the PMOS transistor 255 and the NMOS transistor 256, the output level of the NOT circuit output (OUT) is the “L” level. (FIG. 5C).

At time t0 to t1, PCLK is at “L” level, but DATA transits from “L” level to “H” level (FIGS. 5A and 5B).
Since PCLK is at the “L” level, the operation state of the PMOS transistor 251 and the NMOS transistor 252 is the same as before time t0. On the other hand, since DATA becomes “H” level, the operations of the PMOS transistor 253 and the NMOS transistor 254 change.
That is, since DATA is at the “H” level, the gate of the PMOS transistor 253 is at the “H” level and is in the OFF operation state. Since the gate of the NMOS transistor 254 is at the “H” level, the ON operation state is possible. However, since the NMOS transistor 252 is in the OFF operation state at this time, both the NMOS transistors 252 and 254 are in the OFF operation state.
As a result, the PMOS transistor 253 is in the OFF operation state, but since the PMOS transistor 251 is in the ON operation state, the NAND circuit output becomes “H” level. Since this “H” level voltage is supplied to the NOT circuit, its output OUT becomes the “L” level (FIG. 5C).

At time t1, PCLK changes from the “L” level to the “H” level (FIG. 5A). At this time, DATA maintains the “H” level (FIG. 5B).
Since the “H” level voltage of PCLK is supplied to the gates of the PMOS transistor 251 and the NMOS transistor 252, the PMOS transistor 251 enters the OFF operation state, and the NMOS transistor 252 transitions to the ON operation state.
At this time, since DATA is at the “H” level, the NMOS transistor 254 is in an ON operable state, so that the NMOS transistors 252 and 254 transition to the ON operating state. Further, since the “H” level voltage is supplied to the gate of the PMOS transistor 253, the PMOS transistor 253 is in the OFF operation state.
As a result, the NAND output transits from the “H” level to the “L” level, and maintains that state until time t3.
Since the “L” level voltage of the NAND circuit output is inverted by the NOT circuit, the output OUT becomes the “H” level. However, in FIG. 5C, DATA and PCLK are signal propagation delays and time constants from the decoder (3 to 8 decoder circuit 151) or the timing generator 110 to the input terminal of the NAND circuit due to wiring capacitance, wiring resistance, and the like. As a result, the rising and falling waveform of the signal deteriorates, and the waveform (time t2 in FIG. 5C) highlighting the influence of the delay is shown in the timing chart.

At time t3, PCLK changes from the “H” level to the “L” level (FIG. 5A), but DATA remains at the “H” level (FIG. 5B).
The conditions for this input data are the same as at times t0 to t1. Since PCLK is at “L” level, the PMOS transistor 251 is in the ON operation state, while the NMOS transistor 252 is in the OFF operation state. At this time, since DATA is at “H” level, the gate of the PMOS transistor 253 is at “H” level and is in an OFF operation state, and since the gate of the NMOS transistor 254 is at “H” level, an ON operation state is possible. It becomes. However, at this time, since the NMOS transistor 252 is in the OFF operation state, both the NMOS transistors 252 and 254 are in the OFF operation state.
Although the PMOS transistor 253 is in the OFF operation state, the PMOS circuit 251 is in the ON operation state, so that the NAND circuit output is at the “H” level. Since this “H” level voltage is supplied to the NOT circuit, the output OUT of the NOT circuit becomes the “L” level (FIG. 5C). Again, taking into account the delay time, the output OUT of the NOT circuit shows a waveform that transitions to the “L” level at time t4 (FIG. 5C).

  From time t3 to t5, the input condition is the same as that at time t3. PCLK remains at “L” level, and DATA maintains “H” level. The output waveform of the NOT circuit at that time is at the “L” level as shown in the timing chart of FIG.

At time t5, PCLK is at the “L” level, while DATA changes from the “H” level to the “L” level. The input condition of the NAND circuit at this time is the same as the input condition before time t0 described above.
PCLK is at “L” level together with DATA (FIGS. 5A and 5B), the PMOS transistor 251 is in the ON operation state, and the NMOS transistor 252 is in the OFF operation state.
On the other hand, the PMOS transistor 253 is turned on, and the NMOS transistor 254 is turned off.
As a result, the NMOS transistors 252 and 254 are in the OFF operation state, and the PMOS transistors 251 and 253 are in the ON operation state, so that the NAND circuit output becomes the “H” level.
Then, the “H” level voltage of the NAND output is inverted by the NOT circuit composed of the PMOS transistor 255 and the NMOS transistor 256, so that the output level of the NOT circuit output (OUT) becomes the “L” level ( FIG. 5C).

  As described above, the SRAM word line driver circuit 250 shown in FIG. 4 includes a NAND circuit and a NOT circuit during a long period in which the clock pulse of PCLK is inactive, that is, at “L” level, as shown in FIG. Among these transistors, the NMOS transistor 252 and the PMOS transistor 255 are in an OFF operation state, and the PMOS transistor 251 and the NMOS transistor 256 are in an ON operation state.

  In the word line driver circuit 250 and its timing chart shown in FIGS. 4 and 5, the threshold voltages of the transistors in the OFF operation state for a long time, the NMOS transistor 252 and the PMOS transistor 255 are set high (Hvth), respectively, The threshold voltages of the transistors that have been in the ON operation state for a long time, the PMOS transistor 251 and the NMOS transistor 256, are set low (Lvth).

As described above, by considering the duration of the ON operation time and the OFF operation time on the time axis, the transistor in the OFF operation state for a long time, the NMOS transistor 252 and the PMOS transistor 255 have a high threshold voltage transistor. Can be applied to reduce the leakage current during the OFF operation period.
In addition, a transistor having a low threshold voltage is applied to the transistors in the ON operation state for a long time, that is, the PMOS transistor 251 and the NMOS transistor 256, so that the delay time at the fall of the output signal (OUT) can be reduced. it can.
Although the CMOS circuit configuration using the NMOS transistor and the PMOS transistor has been described, it is apparent that other field effect transistors can be configured, and similar effects can be obtained.
As described above, the decoder circuit and the word line driver circuit related to the row address have been mainly described. However, the same circuit configuration and operation can be applied to the column decoder circuit 153 shown in FIG. , Power consumption can be reduced. At the same time, the operation speed can be improved.

  Up to now, the SRAM circuit has been described as an example. However, the present invention should not be limited to these example embodiments, but can be used in a memory or other products and is sufficiently optimized. The technical idea of the present invention can also be applied to circuit blocks, all of which are critical path circuits.

  As described above, in a circuit in which an OFF operation period and an ON operation period of a field effect transistor are required probabilistically or on a time axis, the threshold voltage of the field effect transistor is set according to the operation state, thereby causing leakage. The current can be reduced (power consumption can be reduced), and the operation speed can be improved.

1 is a circuit diagram illustrating a circuit configuration of an SRAM according to an embodiment of the present invention. FIG. 2 is a diagram showing a decoder circuit and a word line driver circuit of the SRAM shown in FIG. 1. FIG. 6 is a circuit diagram of a decoder circuit according to another embodiment of the present invention. It is a circuit diagram of the word line driver circuit of the other embodiment of the present invention. 6 is a timing chart for explaining the operation of the word line driver circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... SRAM circuit 20, 120-1-120-n ... Word line driver circuit, 21 ... NANAD circuit, 22 ... NOT circuit, 30 ... Decoder circuit / control circuit, 40 ... Memory cell (MC ) Section, 50... Write buffer / sense amplifier circuit, 110... Timing generator, 150... Decoder circuit, 151, 201 3 to 8 decoder circuit, 152. Predecoder circuit, 153 column decoder circuit 210, 251, 253, 255 ... PMOS transistors, 211, 252, 254, 256 ... NMOS transistors.

Claims (8)

In a field effect transistor circuit having a plurality of field effect transistors,
A field effect transistor circuit comprising: a plurality of threshold voltage field effect transistors in which threshold voltages are set on the time axis of the field effect transistor or stochastically according to a period between an on operation state and an off operation state. The field effect transistor circuit according to claim 1, wherein the field effect transistor circuit is a word line driver circuit of a semiconductor memory device. The field effect transistor circuit according to claim 1, wherein the field effect transistor circuit is a decoder circuit of a semiconductor memory device. In a field effect transistor circuit having a plurality of field effect transistors,
On the time axis of the field effect transistor circuit or on a stochastic basis, a field effect transistor having a longer period of the off operation state than the period of the on operation state uses a field effect transistor having a high threshold voltage, and is more A field effect transistor having a low threshold voltage is used as a field effect transistor having a long on-operation period.
A field effect transistor circuit having a field effect transistor having a plurality of threshold voltages. The field effect transistor circuit according to claim 4, wherein the field effect transistor circuit is a word line driver circuit of a semiconductor memory device. The field effect transistor circuit according to claim 4, wherein the field effect transistor circuit is a decoder circuit of a semiconductor memory device. A first step of verifying the transition state of the circuit;
A second step of identifying a field effect transistor having a long period of an on or off operation state on the time axis or probabilistically by the verification;
And a third step of setting a threshold voltage of the identified field effect transistor corresponding to the period of the on / off operation state. 8. The threshold voltage is set such that a high threshold voltage is set for a field effect transistor having a long off-operation period and a low threshold voltage is set for a field effect transistor having a long on-operation period. Field effect transistor circuit design method.

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