JP2009043302A - Data writing circuit and semiconductor memory device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data writing circuit capable of reducing a leakage current and a semiconductor memory device using the same. <P>SOLUTION: The data writing circuit is provided with a buffer circuit including serially connected first and second output transistors and for outputting a write signal to write data in a memory cell, and a control circuit for controlling the buffer circuit. This control circuit controls one of the transistors of the buffer circuit so as to be ON and the other to be OFF according to data to be written, and controls both transistors of the buffer circuit so as to be OFF when no data is written in the memory cell. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data write circuit and a semiconductor memory device using the same, and more particularly to a semiconductor memory device using a data write circuit capable of reducing leakage current.

  As semiconductor manufacturing technology has advanced in recent years, semiconductor devices have been miniaturized, and semiconductor devices have been improved in performance. However, with such miniaturization of semiconductor devices, leakage current has increased. It has become a problem.

  This is the same in the field of semiconductor memory devices such as SRAM. For a circuit that operates at a low speed, the leakage current can be reduced by using a transistor with a high threshold (Vth). It has been difficult to reduce leakage current without reducing the speed of an operating circuit.

  In particular, in a data write circuit for writing data to a memory cell, a write buffer circuit that drives a bit line (global bit line) to which a plurality of memory cells are connected needs to increase the capacity of an internal transistor. Therefore, the W length (channel width) size has to be increased, and the leakage current flowing therethrough is large, which has been a major issue for reducing power consumption.

  Here, a conventional data write circuit will be described with reference to FIGS. FIG. 4 is a configuration diagram of a conventional data write circuit, and FIG. 5 is a diagram showing operation waveforms of the conventional data write circuit.

  As shown in FIG. 4, a conventional data write circuit 100 includes a precharge circuit 101 that precharges a bit line pair (a bit line BL and an inverted bit line BLX) and a column before data is written to the memory cell MC. A column select circuit 102 for controlling connection between the bit line BL and the local write data line WLD and between the inverted bit line BLX and the inverted local write data line WLDX based on the select signal CS [0: n]; A write buffer circuit 103 for setting the voltage of the local write data line WLD and the inverted local write data line WLDX to H level (high voltage level) or L level (low voltage level), and a write control circuit 104 for controlling the write buffer circuit 103 And have.

  In the data write circuit 100 configured as described above, the process in the write cycle, that is, the data write process to the memory cell MC is performed as follows. Here, the data write circuit 100 corresponds to the column select signal CS [0].

  First, as shown in FIG. 5, external input data Data is input at time t11 before the external clock CK rises. Thereafter, in synchronization with the rising of the external clock CK, the column select signal CS [n] falls and the column select signal CS [0] rises at time t12. When the column select signal CS [0] rises in this way, the column select circuit 102 is activated, the bit line BL and the local write data line WLD are connected, and the inverted bit line BLX and the inverted local write data line WLDX are connected. Is connected.

  Thereafter, at time t13, the precharge signal PR rises, and the precharge circuit 101 that has been in an operating state until then becomes inactive. That is, precharge to the bit line BL and the inverted bit line BLX by the precharge circuit 101 is stopped.

  When the write enable signal WRE rises at time t14, the write buffer circuit 103 enters an operating state, and the voltages of the local write data line WLD and the inverted local write data line WLDX are set to the H level and the L level according to the external input data Data, or Write signals that become L level and H level are output from the write buffer circuit 103. Since the local write data line WLD and the inverted local write data line WLDX are connected to the bit line BL and the inverted bit line BLX, respectively, data can be written to the memory cell MC by a write signal output from the write buffer circuit 103. Will be done.

  For example, when the external input data Data is an H level voltage, the inverter circuit 144 of the write control circuit 104 outputs an H level voltage, and the inverter circuit 145 outputs an L level voltage. When the H level voltage is output from the inverter circuit 144, the PMOS transistor 131 of the write buffer circuit 103 is turned off, the NMOS transistor 132 is turned on, and the L level voltage is applied to the bit line BL via the local write data line WLD. Is output. Further, when an L level voltage is output from the inverter circuit 145, the PMOS transistor 133 of the write buffer circuit 103 is turned on, the NMOS transistor 134 is turned off, and the H level voltage is inverted via the inverted local write data line WLDX. It is output to the bit line BLX. In this manner, a write signal in which the bit line BL and the inverted bit line BLX are at L level and H level voltages is output from the write buffer circuit, and data is written into the memory cell MC by this write signal.

  In this way, after the writing of data in the memory cell MC is completed, the write enable signal WRE falls at time t15, the write buffer circuit 103 becomes non-operating, and then the precharge signal PR falls, and the precharge circuit 101 becomes an operation state.

  At this time, the outputs of the inverter circuits 144 and 145 of the write control circuit 104 both become L level voltages, the NMOS transistors 132 and 134 of the write buffer circuit 103 are turned off, and the PMOS transistors 131 and 133 are turned on. For this reason, a leak current continues to flow from the PMOS transistor 131 to the NMOS transistor 132 and from the PMOS transistor 133 to the NMOS transistor 134, which is a problem of reducing power consumption in the semiconductor memory device.

  In order to avoid this problem of leakage current, a technique has been proposed in which a switch SW150 of a transistor is inserted between a power supply and PMOS transistors 131 and 133 and the switch SW150 is controlled as shown in FIG. (See "Prior Art" in Patent Document 1). That is, when it is desired to put the semiconductor memory device into a low leakage state, the standby control signal STBp having an H level voltage is input, the switch SW150 is turned off, and the PMOS transistor 131 to the NMOS transistor 132 and the PMOS transistor 133 to the NMOS transistor 134 are turned on. The leak current is suppressed.

  However, since the write buffer circuit 103 needs to pass a large current when data is written, the size of the transistor used as the switch SW150 must be increased, the mounting area is increased, and the current reduction effect is further reduced. End up. On the other hand, if the size of the transistor used as the switch SW150 is reduced, an increase in the mounting area can be suppressed, but the current driving capability is reduced and the circuit speed is reduced.

  Therefore, the applicant has proposed a data write circuit that can reduce the leakage current of the write buffer circuit by configuring the write control circuit as shown in FIG. 7 (see Patent Document 1).

  The write control circuit 204 of this data write circuit inputs the outputs of the AND circuits 241 and 242 to the gates of the NMOS transistors 132 and 134, respectively, and inputs them to one terminal of the OR circuits 244 and 245. The outputs of the circuits 244 and 245 are input to the gates of the PMOS transistors 131 and 133, respectively. The standby control signal STBp is input to the other input of the OR circuits 244 and 245 to reduce the leakage current.

That is, when the voltage of the write enable signal WRE is at the L level, the outputs of the AND circuits 241 and 242 in the write control circuit 204 are at the L level, and the NMOS transistors 132 and 134 are turned off. Further, by setting the standby control signal STBp to the H level voltage, the outputs of the OR circuits 244 and 245 become the H level voltage, and the PMOS transistors 131 and 133 are turned off. As described above, when it is desired to set the semiconductor memory device in a low leakage state, the standby control signal STBp is set to the H level voltage, thereby turning off all the transistors of the write buffer circuit 103 and reducing the leakage current.
JP 2006-92696 A

  As described above, the circuit proposed by the present applicant is excellent in that the increase in mounting area can be suppressed and a large leakage current can be reduced without affecting the operation speed of the circuit.

  However, when the write buffer circuit is controlled by the standby control signal STBp, a circuit for generating the standby control signal STBp and wiring from the circuit to the write control circuit are required. In addition, since the standby control signal STBp is not output during the write cycle, a leakage current occurs during a part of the write cycle.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a data write circuit capable of further reducing leakage current and a semiconductor memory device using the data write circuit.

  To achieve the above object, according to a first aspect of the present invention, there is provided a data write circuit for writing data to a memory cell, wherein the data write circuit includes a first output transistor and a second output transistor connected in series. And when writing data to the memory cell, one of the first output transistor and the second output transistor is controlled to be in an on state and the other is in an off state in accordance with the data to be written. And a control circuit for controlling both the first output transistor and the second output transistor to an off state when writing is not performed.

  According to a second aspect of the present invention, in the first aspect of the present invention, the data write circuit is provided between the memory cell and the buffer circuit, and the memory cell and the buffer circuit are in an operating state. A select circuit for connecting the buffer circuit to the buffer circuit and disconnecting the memory cell and the buffer circuit when the buffer circuit is in the non-operating state; and setting the select circuit to the operating state when writing data to the memory cell. The select circuit is set in a non-operating state when data is not written to the memory cell.

  According to a third aspect of the present invention, the first output transistor and the second output transistor are a PMOS transistor and an NMOS transistor, respectively, and the control circuit performs a signal corresponding to data to be written and its inversion at the time of data writing. Each of the signals is generated, one signal is input to the first output transistor, and the other signal is output to the second output transistor.

  According to a fourth aspect of the present invention, a plurality of bit line pairs composed of two bit lines, a plurality of memory cells connected to the bit line pair, and data to the memory cells via the bit line pairs. In the semiconductor memory device having a plurality of data write circuits for writing the data, the data write circuit has a pair of driver circuits each having a first output transistor and a second output transistor connected in series, and the data is A buffer circuit for outputting a write signal for writing to the memory cell to the bit line pair, and at the time of data writing to the memory cell, the first output transistor and the second output transistor of each driver circuit according to the data to be written One of the memory cells is turned on and the other is controlled to be turned off, and data is not written to the memory cell. To is characterized in that a control circuit for controlling the both turned off the first output transistor and the second output transistor of each of said driver circuits.

  According to the first and fourth aspects of the invention, in the write cycle, all the transistors of the buffer circuit can be turned off at times other than the data write time. Even during the write cycle, the leakage current during periods other than the write operation can be reduced.

  According to the second aspect of the present invention, since the memory cell and the buffer circuit can be separated in the write cycle except when data is written, the precharge circuit for precharging the memory cell can be separated. It is possible to suppress leakage current from flowing to the transistor of the buffer circuit.

  According to the third aspect of the present invention, the buffer circuit can be a CMOS type in which a PMOS transistor and an NMOS transistor are connected in series.

  The semiconductor memory device according to the embodiment of the present invention has a data write circuit for writing data to a memory cell, and the data write circuit has a first output transistor and a second output transistor connected in series. And a buffer circuit for outputting a write signal for writing data to the memory cell, and a control circuit for controlling the buffer circuit. Here, the first output transistor is a PMOS transistor, and the second output transistor is an NMOS transistor.

  In addition, when writing data to the memory cell, the control circuit controls one of the first output transistor and the second output transistor to be in an on state and the other to be in an off state in accordance with the data to be written, thereby writing the data into the memory cell. When not being performed, both the first output transistor and the second output transistor are controlled to be in the OFF state.

  Therefore, in the write cycle, all the transistors in the buffer circuit can be turned off at times other than data write, so that not only during standby operation and read cycle, but also during write cycle other than during write operation. Leakage current during the period can be reduced.

  In addition, since the number of circuit elements does not increase as compared with the conventional data writing circuit, an increase in mounting area can be suppressed.

  The data write circuit is provided between the memory cell and the buffer circuit, and connects the memory cell and the buffer circuit in an operating state, and disconnects the memory cell and the buffer circuit in a non-operating state. A select circuit for connection is provided, and the select circuit is set to an operating state when data is written to the memory cell, and the select circuit is set to a non-operating state when data is not written to the memory cell.

  Therefore, the memory cell and the buffer circuit can be separated in a write cycle other than at the time of data writing, so that a leak current flows from the precharge circuit for precharging the memory cell to the transistor of the buffer circuit. Can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory device according to the present embodiment, and an SRAM (Static Random Access Memory) will be described as an example.

  A semiconductor memory device 1 shown in FIG. 1 includes a plurality of word line driver (Word Driver) circuits 2, a decoder (Decode) / control (Control) circuit 3, a plurality of memory cell units 4, a write buffer (Write Buffer) / sense amplifier. (Sense Amp) 5 etc.

Here, for simplification of explanation, only one word line driver (consisting of a NAND circuit and an inverter circuit) and one memory block BKL ₁ are shown, but in reality, a predetermined number of word lines (WL0, WL1,... There are a predetermined number of memory blocks (BKL ₁ ,..., BKL _n ) arranged in units of. Memory cells MC (MC-01, MC-02,...) Are connected to each word line.

  The decoder / control circuit 3 includes a predecoder, an internal timing control circuit, and the like, decodes input address data, and generates an internal clock signal, a control signal, and the like based on the external clock ECK.

  In addition to the row address decoder, there is also a column address decoder. The column address decoder selects a column (column direction) address based on the input address data.

  Further, when the external control signal and the external clock ECK are supplied, the control circuit decodes the write enable signal WRE and supplies it to the predecoder and the word line driver circuit 2 to decode the address signal, for example. Activate or deactivate. Also, the clock CK is generated, the write enable signal WRE is output to the write buffer / sense amplifier 5, and the write timing is controlled. Further, a sense amplifier enable signal is output to a sense amplifier circuit that amplifies data on the bit line pair BL, BLX (BL inversion). Further, a timing signal for controlling the column address output from the column decoder is output.

  One word line driver circuit 2 is selected by the predecoder, and the selected specific word line driver circuit 2 is supplied with CK and DATA output from the decoder / control circuit 3. In the selected block of the word line driver circuit 2, for example, when the unit of the decoder is 3 bits, an H level voltage is supplied from 8 word lines to one word line to be activated (activated), At the same time, an L level voltage is supplied to the other word lines to deactivate them.

  In the memory cell unit 4, for example, a plurality of memory cells MC-00 to MC-nm such as SRAM cells and ROM cells are arranged in a matrix, and generally MC-00 to MC-0m are connected to the same word line. −00 to MC-n0 are connected to the same bit line pair BL, BLX.

  The write buffer / sense amplifier 5 is supplied with a write enable signal WRE, a column select signal CS [0: n], input data Data, and the like at the time of data writing. When the bit line pair BL, BLX is selected by the column select signal CS [0: n], data is written to the memory cell MC via the write buffer circuit. The write buffer / sense amplifier 5 amplifies the data output from the selected memory cell MC onto the bit line pair BL, BLX when reading data, and passes through the output buffer of the write buffer / sense amplifier 5. Output data.

  Next, the data write circuit of the semiconductor memory device 1 in this embodiment will be described with reference to the drawings. FIG. 2 is a diagram showing an outline of the configuration of the data write circuit of the semiconductor memory device 1 according to the embodiment of the present invention, and FIG. 3 is a diagram showing waveforms at various parts of the data write circuit shown in FIG. In the present embodiment, the write buffer / sense amplifier 5 of the semiconductor memory device 1 has a data write circuit for each bit pair BL, BLX.

  As shown in FIG. 2, the data write circuit WC of the semiconductor memory device 1 according to the present embodiment writes the data into the memory cell MC, and before writing the data into the memory cell MC, the bit line BL and the inverted bit line. Based on the precharge circuit 10 that precharges BLX and the column select signal CS [0: n], between the bit line BL and the local write data line WLD, between the inverted bit line BLX and the inverted local write data line WLDX. A column select circuit 20 (corresponding to an example of a select circuit) for controlling the connection between them, and a write buffer circuit 30 (the buffer circuit of the buffer circuit) for setting the local write data line WLD and the inverted local write data line WLDX to the H level or L level. Corresponding to an example) and a write control circuit for controlling the write buffer circuit 30. 40 and a (corresponding to an example of the control circuit).

  The precharge circuit 10 includes a PMOS transistor 11 having a source connected to a power line, a drain connected to the bit line BL, and a PMOS transistor 12 having a source connected to the power line and a drain connected to the inverted bit line BLX. , A PMOS transistor 13 having a drain and a source connected to the bit line BL and the inverted bit line BLX, respectively, and a precharge signal PR is input to the gates of the PMOS transistors 11 to 13 to control the on / off state. Is done.

  That is, when the precharge signal PR of L level voltage is input to the gates of the PMOS transistors 11 to 13, the PMOS transistors 11 to 13 are turned on, and the voltage from the power supply line to the bit line BL and the inverted bit line BLX. Is supplied, and the bit line BL and the inverted bit line BLX are precharged to a predetermined voltage. On the other hand, when a precharge signal PR having an H level voltage is input to the gates of the PMOS transistors 11 to 13, the PMOS transistors 11 to 13 are turned off, and the precharge to the bit line BL and the inverted bit line BLX is performed. Not done.

  The column select circuit 20 includes a transistor pair 21 provided between the bit line BL and the local write data line WLD and a transistor pair 22 provided between the inverted bit line BLX and the inverted local write data line WLDX. Have.

  The transistor pair 21 includes an NMOS transistor 23 and a PMOS transistor 24. The drain of the NMOS transistor 23 and the source of the PMOS transistor 24 are connected to the bit line BL, respectively, and the source of the NMOS transistor 23 and the drain of the PMOS transistor 24 are connected. Are connected to the local write data line WLD. The transistor pair 22 includes a PMOS transistor 25 and an NMOS transistor 26. The source of the PMOS transistor 25 and the drain of the NMOS transistor 26 are connected to the inverted bit line BLX, respectively. The drain of the PMOS transistor 25 and the NMOS transistor 26 sources are connected to the inverted local write data line WLDX, respectively.

  The column select signal CS [0: n] is input to the gates of the NMOS transistors 23 and 26, and the inverted signal of the column select signal CS [0: n] is input to the gates of the PMOS transistors 24 and 25 via the inverter circuit 27. Is entered. Therefore, when the column select signal CS [0: n] is at the L level, the transistors 23 to 26 are turned off, and the bit line BL and the inverted bit line BLX are connected to the local write data line WLD and the inverted local write data line. It is in a state of being disconnected from WLDX. On the other hand, when the voltage of the column select signal CS [0: n] is at the H level, the transistors 23 to 26 are turned on, the bit line BL is the local write data line WLD, and the inverted bit line BLX is the inverted local write data line. Each is connected to WLDX.

  The write buffer circuit 30 includes a first driver circuit 31 including a PMOS transistor 33 (corresponding to a first output transistor) and an NMOS transistor 34 (corresponding to a second output transistor) connected in series between a power supply line and a ground line. And a second driver circuit 32 comprising a PMOS transistor 35 (corresponding to a first output transistor) and an NMOS transistor 36 (corresponding to a second output transistor) connected in series between a power supply line and a ground line. Based on the control signal output from the write control circuit 40, a write signal is output to the local write data line WLD and the inverted local write data line WLDX.

  In the first driver circuit 31, the source of the PMOS transistor 33 is connected to the power supply line, and the source of the NMOS transistor 34 is connected to the ground line. The drains of the PMOS transistor 33 and the NMOS transistor 34 are connected to the local write data line WLD. Similarly, in the second driver circuit 32, the source of the PMOS transistor 35 is connected to the power supply line, and the source of the NMOS transistor 36 is connected to the ground line. The drains of the PMOS transistor 35 and the NMOS transistor 36 are connected to the inverted local write data line WLDX.

  The write control circuit 40 includes NAND circuits 41 and 42 and inverter circuits 43 to 45. The write control circuit 40 receives write buffer signals from the inverter circuits 44 and 45 according to the input write enable signal WRE and external input data Data. A control signal is output to the circuit 30.

  In particular, the write control circuit 40 controls one of the transistors of the driver circuits 31 and 32 of the write buffer circuit 30 to be in an on state and the other transistor to be in an off state only at the time of data writing in a write cycle, to the memory cell MC. On the other hand, except for the time of data writing, the transistors 33 to 36 of the write buffer circuit 30 are turned off to suppress leakage currents in the NMOS transistors 34 and 36. The configuration of the write control circuit 40 will be specifically described below.

  The write enable signal WRE is input to one data input node of the NAND circuits 41 and 42. Further, external input data Data is input to the other data input node of the NAND circuit 41, and external input data Data inverted by the inverter circuit 43 is input to the other data input node of the NAND circuit 42. Therefore, when the write enable signal WRE rises, a signal corresponding to the external input data Data and its inverted signal are output from the NAND circuits 41 and 42.

  Data output nodes of NAND circuits 41 and 42 are connected to input nodes of inverter circuits 44 and 45, respectively. The data output node of the inverter circuit 44 is connected to the gate of the NMOS transistor 34, and the data output node of the inverter circuit 45 is connected to the gate of the NMOS transistor 36. The data output node of the NAND circuit 41 is connected to the gate of the PMOS transistor 35, and the data output node of the NAND circuit 42 is connected to the gate of the PMOS transistor 33.

  In the data write circuit WC configured as described above, data write processing to the memory cell MC is performed as follows. Note that the data write circuit WC here corresponds to the column select signal CS [0].

  First, as shown in FIG. 3, before the clock CK rises, external input data Data is input at time t1. Thereafter, the precharge signal PR rises at time t2, and the precharge circuit 10 that has been on until then is turned off. That is, the precharge circuit 10 stops precharging the bit line BL and the inverted bit line BLX.

  Thereafter, the column select signal CS [0] and the write enable signal WRE rise at time t3. When the column select signal CS [0] rises, the column select circuit 20 is activated, the bit line BL and the local write data line WLD are connected, and the inverted bit line BLX and the inverted local write data line WLDX are connected. become.

  Further, when the write enable signal WRE rises, the write buffer circuit 30 is in an operating state, and the local write data line WLD and the inverted local write data line WLDX are set to the H level and L level voltages or the L level according to the external input data Data. A write signal having a level and an H level voltage is output from the write buffer circuit 103. Since the local write data line WLD and the inverted local write data line WLDX are connected to the bit line BL and the inverted bit line BLX, respectively, writing to the memory cell MC is performed by a write signal output from the write buffer circuit 30. It will be.

  For example, when the voltage of the external input data Data is H level, the H level voltage from the NAND circuit 42 and the inverter circuit 44 of the write control circuit 40 respectively, and the L level voltage from the NAND circuit 41 and the inverter circuit 45 respectively. Is output. When the H level voltage is output from the NAND circuit 42 and the inverter circuit 44, the PMOS transistor 33 of the write buffer circuit 30 is turned off and the NMOS transistor 34 is turned on, and the L level voltage is locally supplied from the first driver circuit 31. The data is output to the bit line BL via the write data line WLD. On the other hand, when an L level voltage is output from the NAND circuit 41 and the inverter circuit 45, the PMOS transistor 35 of the write buffer circuit 30 is turned on, the NMOS transistor 36 is turned off, and the second driver circuit 32 outputs an H level voltage. Is output to the inverted bit line BLX via the inverted local write data line WLDX. As described above, a write signal in which the voltages of the bit line BL and the inverted bit line BLX become L level and H level, respectively, is output from the write buffer circuit, and data is written into the memory cell MC by this write signal.

  Further, when the voltage of the external input data Data is L level, the L level voltage from the NAND circuit 42 and the inverter circuit 44 of the write control circuit 40 respectively, and the H level voltage from the NAND circuit 41 and the inverter circuit 45 respectively. Is output. When the L level voltage is output from the NAND circuit 42 and the inverter circuit 44, the PMOS transistor 33 of the write buffer circuit 30 is turned on, the NMOS transistor 34 is turned off, and the H level voltage is locally supplied from the first driver circuit 31. The data is output to the bit line BL via the write data line WLD. On the other hand, when an H level voltage is output from the NAND circuit 41 and the inverter circuit 45, the PMOS transistor 35 of the write buffer circuit 30 is turned off and the NMOS transistor 36 is turned on, and the second driver circuit 32 outputs an L level voltage. Is output to the inverted bit line BLX via the inverted local write data line WLDX. In this way, a write signal in which the voltages of the bit line BL and the inverted bit line BLX are at the H level and the L level, respectively, is output from the write buffer circuit, and data is written into the memory cell MC by this write signal.

  After the data writing of the memory cell MC is thus completed, the write enable signal WRE falls at time t4, the write buffer circuit 103 becomes inoperative, and the column select signal CS [0] falls, The select circuit 20 is deactivated. When the column select circuit 20 is deactivated, the bit line BL and the local write data line WLD are disconnected, and the inverted bit line BLX and the inverted local write data line WLDX are disconnected. Next, at time t5, the precharge signal PR falls, and the precharge circuit 101 enters an operating state.

  Here, when the voltage of the write enable signal WRE falls and becomes L level, the outputs of the NAND circuits 41 and 42 are both H level voltages, and the outputs of the inverter circuits 44 and 45 are both L level voltages. Accordingly, the gate voltages of the PMOS transistors 33 and 35 are both at the H level, the PMOS transistors 33 and 35 are turned off, and the gate voltages of the NMOS transistors 34 and 36 are both at the L level. 36 is turned off. That is, all the transistors 33 to 36 of the write buffer circuit 30 are turned off.

  Therefore, after the voltage of the write enable signal WRE falls to the L level, the leakage current from the PMOS transistor 33 to the NMOS transistor 34 and the leakage current from the PMOS transistor 35 to the NMOS transistor 36 do not flow.

  As described above, in the data write circuit WC in the present embodiment, the transistors 33 to 36 of the write buffer circuit 30 are in the off state except during the write operation in the write cycle, thereby suppressing the generation of leakage current as much as possible. It is said.

  Further, as described above, the column select signal CS [0: n] also falls when the write enable signal WRE falls, thereby turning off the column select circuit 20, and the bit line BL and the inverted bit line. BLX is separated from the local write data line WLD and the inverted local write data line WLDX.

  In the conventional data write circuit 100 (see FIG. 4), when the voltage of the column select signal CS [0] is switched from H level to L level, the voltage of the next column select signal CS [n] is changed from L level to H level. (See FIG. 5). Therefore, any one of the plurality of column select circuits is in an operating state. Therefore, after time t15 (see FIG. 5), the precharge signal PR falls and the precharge circuit is in an operating state, but the column select circuit is in an operating state. Leakage current flows to the NMOS transistor, which hinders low power consumption.

  However, in the data write circuit WC according to the present embodiment, the column select signal CS [0: n] is pulsed as described above, and is lowered at every data write operation of the write cycle. The circuit 20 is deactivated.

  Therefore, at time t5, the precharge signal PR falls, and the precharge circuit 10 enters the operating state. However, since the column select circuit 20 brings the precharge circuit 10 and the write buffer circuit 30 into a disconnected state, Leakage current does not flow from the circuit 10 to the NMOS transistor of the write buffer circuit 30, and power consumption can be reduced.

  As described above, in the data write circuit WC in the present embodiment, all the paths of the leak current flowing into the NMOS transistors 34 and 36 having a very large W length (channel width), which has been a problem in the past, are cut off. This reduces the leakage current. In addition, it is possible to reduce the leakage current not only during standby but also during operation other than the write operation (period Ta in FIG. 3) in the write cycle. Since the bit line pair BL, BLX is precharged every write cycle, there is no margin reduction (yield reduction) and speed reduction at the time of write operation or read operation, and the number of circuit elements is the same as that of the conventional circuit. Therefore, the mounting area does not increase.

  Here, the write control circuit 40 turns on one transistor of each of the first driver circuit 31 and the second driver circuit 32 at the time of data writing and turns off the other transistor. The circuit shown in FIG. 2 is not necessarily required as long as any of the 32 transistors is controlled to be turned off. However, the circuit configuration of FIG. 2 is one of the most preferable circuit configurations because it does not involve an increase in circuit elements.

  As shown in FIG. 2, the column select circuit 20 is preferably a CMOS type in which a PMOS transistor and an NMOS transistor are connected in series. However, the effect of the present invention can be achieved even if the column select circuit 20 is changed to an NMOS type in which two NMOS transistors are connected in series. It is possible to get

  Further, as described above, the column select signal CS [0: n] is pulsed and the column select circuit 20 is not inactivated in every write cycle. For example, the column select signal is only in a standby state by a chip enable signal. The voltage of CS [0: n] may be set to L level. In this case, the leakage current reduction effect is reduced (leakage current during the write cycle cannot be reduced), but leakage current during standby can be reduced.

  Although several embodiments of the present invention have been described in detail with reference to the drawings, these are merely examples, and the present invention can be implemented in other forms that are variously modified and improved based on the knowledge of those skilled in the art. It is possible to implement.

1 is a diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. 1 is a diagram showing a schematic configuration of a data write circuit of a semiconductor memory device according to an embodiment of the present invention. It is a figure which shows the waveform of each site | part of the data write circuit shown in FIG. It is a block diagram of the conventional data write circuit. It is a figure which shows the operation | movement waveform of the conventional data write circuit. It is a figure which shows the structure of a part of another conventional data write circuit. It is a figure which shows the structure of a part of other conventional data write circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Word line driver circuit 3 Decoder / control circuit 4 Memory cell part 5 Write buffer / sense amplifier 10 Precharge circuit 20 Word line driver circuit 30 Write buffer circuit 31 1st driver circuit 32 2nd driver circuits 33 and 35 PMOS transistors 34 and 36 NMOS transistor 40 Write control circuit MC Memory cell WC Write buffer circuit

Claims (4)

In a data writing circuit for writing data to a memory cell,
The data writing circuit includes:
A buffer circuit having a first output transistor and a second output transistor connected in series, and outputting a write signal for writing the data to the memory cell;
When writing data to the memory cell, one of the first output transistor and the second output transistor is controlled to be in an on state and the other is in an off state in accordance with the data to be written, so that the data is written to the memory cell. A data write circuit comprising: a control circuit that controls both the first output transistor and the second output transistor to be in an off state when there is not. The data writing circuit includes:
Provided between the memory cell and the buffer circuit, the memory cell and the buffer circuit are connected in an operating state, and the memory cell and the buffer circuit are disconnected in a non-operating state And a select circuit
2. The data write circuit according to claim 1, wherein when the data is written to the memory cell, the select circuit is in an operating state, and when the data is not written into the memory cell, the select circuit is in an inoperative state. The first output transistor and the second output transistor are a PMOS transistor and an NMOS transistor, respectively.
The control circuit includes:
A signal according to data to be written and an inverted signal thereof are respectively generated at the time of data writing, one signal is input to the first output transistor, and the other signal is output to the second output transistor. The data write circuit according to claim 1 or 2. A plurality of bit line pairs consisting of two bit lines;
A plurality of memory cells connected to the bit line pair;
In a semiconductor memory device having a plurality of data write circuits for writing data to the memory cells via the bit line pairs,
The data writing circuit includes:
A buffer circuit having a pair of driver circuits each having a first output transistor and a second output transistor connected in series, and outputting a write signal for writing the data to the memory cell to the bit line pair;
When writing data to the memory cell, one of the first output transistor and the second output transistor of each driver circuit is controlled to be in an on state and the other is in an off state in accordance with the data to be written. And a control circuit for controlling both the first output transistor and the second output transistor of each of the driver circuits to an off state when writing is not being performed.

Images