KR101038310B1 - Method for forming gate spacer of semiconductor device - Google Patents

Abstract

The present invention discloses a method of forming a gate spacer of a semiconductor device capable of improving the electrical characteristics of the device. The disclosed method includes providing a semiconductor substrate having defined cell regions and peripheral regions; Forming a first oxide film on the semiconductor substrate; Selectively etching the first oxide film to form a first oxide pattern to expose a portion of the substrate corresponding to a gate formation region; Sequentially forming a second oxide film, a polycrystalline silicon film, a tungsten film, and a hard mask film on the entire surface of the substrate product on which the first oxide film pattern is formed; Patterning the hard mask film, the tungsten film, and the polysilicon film to form a gate on the second oxide film between the first oxide film patterns; Selectively oxidizing a surface of the exposed second oxide film and sidewalls of the polysilicon film remaining after etching to form a third oxide film; Sequentially forming a first nitride film, a fourth oxide film, a second nitride film, and a fifth oxide film on the resultant product on which the third oxide film is formed; The fifth oxide film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film pattern of the peripheral area are selectively etched to form a first gate spacer on the gate sidewall of the peripheral area. Forming; Selectively removing the fifth oxide film of the cell region; Forming a third nitride film on a product from which the fifth oxide film of the cell region is selectively removed; And selectively etching the third nitride film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film of the cell region to form a second gate spacer on the gate sidewall of the cell region. Forming a step.

Description

Gate spacer formation method of semiconductor device TECHNICAL FIELD

1A to 1E are cross-sectional views of respective processes for explaining a method of forming a gate spacer of a semiconductor device according to the related art.

2A to 2F are cross-sectional views of respective processes for explaining a method of forming a gate spacer of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

40: semiconductor substrate 41: first oxide film

41a: first oxide film pattern 42: second oxide film

43 polycrystalline silicon film 44 tungsten film

45: hard mask film 46: gate

47: third oxide film 48: first nitride film

49: fourth oxide film 50: second nitride film

51: fifth oxide film 52: first gate spacer

53: third nitride film 54: second gate spacer

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate spacer of a semiconductor device for improving the electrical characteristics of the device.

As is well known, gate spacers have been formed for the formation of lightly doped drain (LDD), one method for preventing short channel effects.

However, as various process technologies have been developed in accordance with the demand for high integration of semiconductor devices, the gate spacers, as well as a function for forming LDD regions, have a function as an electrical blocking means between adjacent gate electrodes.

For example, the gate spacer gives a greater meaning to the function as an electrical blocking means between adjacent gate electrodes than as a means for forming an LDD region in a manufacturing process of a highly integrated semiconductor device to which a self-aligned contact process is applied. It's happening.

In order to form such a gate spacer, conventionally, a spacer film is deposited on a silicon substrate on which a gate electrode is formed and a blanket is etched to form a gate spacer on the side of the gate electrode.

1A to 1E are cross-sectional views of respective processes for describing a method of forming a gate spacer of a semiconductor device according to the related art, which will be described below.

In the conventional method of forming a gate spacer of a semiconductor device, as shown in FIG. 1A, a semiconductor substrate 10 in which a cell region and a peripheral region are defined is provided, and then a first oxide layer on the semiconductor substrate 10 is formed. 11), the polysilicon film 12, the tungsten film 13, and the hard mask film 14 are sequentially formed.

Next, as illustrated in FIG. 1B, the hard mask film 14, the tungsten film 13, and the polysilicon film 12 are selectively etched to form a gate 15, and then the gate 15. In order to recover damage due to the etching process for forming, a reoxidation process is performed on the semiconductor substrate 10 on which the gate 15 is formed. In this case, reference numeral 11b, which is not described in FIG. 1B, indicates the first oxide film remaining in the region where the gate is not formed.

Here, the reoxidation process is a heat treatment process in an oxidizing atmosphere, which is performed by a selective oxidation process in which only silicon is oxidized, and as a result of the selective oxidation process, the surface and gate of the remaining gate oxide film 11b are formed. (15) A second oxide film 16 is formed on the side of the polysilicon film 12 having a structure.

Thereafter, a first nitride film 17 is formed on the resultant to prevent oxidation of the tungsten film 13.

Subsequently, as illustrated in FIG. 1C, a third oxide film 18, a second nitride film 19, and a fourth oxide film 20 are sequentially formed on the first nitride film 17.

Then, as shown in FIG. 1D, the fourth oxide film 20, the second nitride film 19, the third oxide film 18, the first nitride film 17, the second oxide film 16, and the like in the peripheral region are formed. The first oxide film 11b is etched to form NONO (first nitride film 17 / third oxide film 18 / second nitride film 19 / fourth oxide film 20) on the sidewall of the gate 15 of the peripheral region. After forming the first gate spacer 21 having a structure, a high concentration of impurity ions are implanted into the semiconductor substrate 10 by using the gate 15 and the first gate spacer 21 of the peripheral region as a mask. A drain region (not shown) is formed. Subsequently, the fourth oxide film of the cell region is selectively removed.

Next, as shown in FIG. 1E, after the third nitride film 22 is formed on the resultant material, the third nitride film 22, the second nitride film 19, and the third oxide film 18 of the cell region are formed. The first nitride film 17, the second oxide film 16, and the first oxide film 11b are etched to form NON (first nitride film 17 / third oxide film 18 /) on the sidewall of the gate 15 of the cell region. A second gate spacer 23 having a second and third nitride film 19 and 22 structure is formed.

However, in the prior art, in the first and second gate spacers of the NONO and NON structures, charge trapping is performed at the interface between the first nitride film of the first and second gate spacers and the second oxide film below the first and second gate spacers. Phenomenon occurs, and the physical distance between the channel region and the region where the charge trapping occurs is only several tens of micrometers, and thus, the charge trapping phenomenon directly affects the channel region directly, resulting in hot carrier degradation. ) And the gate induced drain leakage (GIDL) is increased, the electrical characteristics of the device, such as the breakdown voltage (BV) of the junction (decreased) is reduced.

Therefore, the present invention has been made to solve the above problems, by increasing the physical distance between the channel region and the portion where the charge trapping phenomenon occurs, the charge trapping phenomenon directly affects the channel region electrically The purpose of the present invention is to provide a method of forming a gate spacer of a semiconductor device, which can prevent the increase of HCD and GIDL and at the same time prevent the reduction of junction BV, thereby improving the electrical characteristics of the device.

According to an aspect of the present invention, there is provided a method of forming a gate spacer of a semiconductor device, the method including: providing a semiconductor substrate in which a cell region and a peripheral region are defined; Forming a first oxide film on the semiconductor substrate; Selectively etching the first oxide film to form a first oxide pattern to expose a portion of the substrate corresponding to a gate formation region; Sequentially forming a second oxide film, a polycrystalline silicon film, a tungsten film, and a hard mask film on the entire surface of the substrate product on which the first oxide film pattern is formed; Patterning the hard mask film, the tungsten film, and the polysilicon film to form a gate on the second oxide film between the first oxide film patterns; Selectively oxidizing a surface of the exposed second oxide film and sidewalls of the polysilicon film remaining after etching to form a third oxide film; Sequentially forming a first nitride film, a fourth oxide film, a second nitride film, and a fifth oxide film on the resultant product on which the third oxide film is formed; The fifth oxide film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film pattern of the peripheral area are selectively etched to form a first gate spacer on the gate sidewall of the peripheral area. Forming; Selectively removing the fifth oxide film of the cell region; Forming a third nitride film on a product from which the fifth oxide film of the cell region is selectively removed; And selectively etching the third nitride film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film of the cell region to form a second gate spacer on the gate sidewall of the cell region. Forming a step.

Here, the first oxide film is formed to a thickness of 100 ~ 180Å, the second oxide film is formed to a thickness of 30 ~ 50Å. The polysilicon film is formed to a thickness of 400 to 700 kPa, and the tungsten film is formed to a thickness of 300 to 600 kPa.

In addition, the hard mask film is formed to a thickness of 2000 ~ 2500Å, the third oxide film is formed to a thickness of 20 ~ 50Å, the first nitride film is formed to a thickness of 70 ~ 100ÅÅ.

The fourth oxide film is formed to a thickness of 80 to 120 GPa, and the second nitride film is formed to a thickness of 90 to 150 GPa. In addition, the fifth oxide film is formed to a thickness of 400 ~ 600Å, the third nitride film is formed to a thickness of 100 ~ 150Å.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of respective processes for describing a method of forming a gate spacer of a semiconductor device according to an embodiment of the present invention.

In the method of forming the gate spacer of the semiconductor device according to the embodiment of the present invention, as shown in FIG. The first oxide film 41 is formed. Here, the first oxide film 41 is formed to a thickness of 100 ~ 180Å.

Subsequently, as illustrated in FIG. 2B, the first oxide layer is selectively etched to form a first oxide layer pattern 41a exposing a portion of the substrate corresponding to the gate formation region. Thereafter, the second oxide film 42, the polycrystalline silicon film 43, the tungsten film 44, and the hard mask film 45 are sequentially formed on the entire surface of the substrate product on which the first oxide film pattern 41a is formed. Here, the second oxide film 42 is formed to a thickness of 30 ~ 50 ~, the polysilicon film 43 is formed to a thickness of 400 ~ 700Å, the tungsten film 44 is formed to a thickness of 300 ~ 600Å do. In addition, the hard mask film 45 is formed to a thickness of 2000 ~ 2500Å.

Next, as shown in FIG. 2C, the hard mask layer 45, the tungsten layer 44, and the polysilicon layer 43 are patterned to form the second oxide layer 42 between the first oxide layer pattern 41a. After the gate 46 is formed on the semiconductor substrate 40, a reoxidation process is performed on the semiconductor substrate 40 on which the gate 46 is formed in order to recover damage caused by the etching process for forming the gate 46. Here, the reoxidation process is a heat treatment process in an oxidizing atmosphere, and is performed by a selective oxidation process in which only silicon is oxidized, and as a result of the selective oxidation process, the surface of the exposed second oxide film 42 is exposed. And a third oxide film 47 is formed on the side surface of the polysilicon film 43 remaining after etching. At this time, the third oxide film 47 is formed to a thickness of 20 ~ 50Å.

Then, the first nitride film 48 is formed on the resultant product on which the third oxide film 47 is formed to prevent oxidation of the tungsten film 44. Here, the first nitride film 48 is formed to a thickness of 70 ~ 100 ~.

Here, a charge trapping phenomenon occurs at an interface between the third oxide film 47 formed by the reoxidation process and the first nitride film 48. In this case, in the present invention, the charge trapping phenomenon generating portion and the Since the physical distance between the substrates 40 is about 100 to 200 microns, the thickness of the first, second, and third oxide films 41a, 42, and 47 combined, the charge trapping phenomenon is directly adversely affected by the channel region. This can minimize the effects of

Subsequently, as shown in FIG. 2D, a fourth oxide film 49, a second nitride film 50, and a fifth oxide film 51 are sequentially formed on the first nitride film 48. Here, the fourth oxide film 49 is formed to a thickness of 80 ~ 120Å, the second nitride film 50 is formed to a thickness of 90 ~ 150Å, the fifth oxide film 51 to a thickness of 400 ~ 600Å Form.

Then, as shown in Figure 2e, the fifth oxide film 51, the second nitride film 50, the fourth oxide film 49, the first nitride film 48, the third oxide film 47, The second oxide film 42 and the first oxide film pattern 41a are selectively etched to form NONO (first nitride film 48 / fourth oxide film 49 / second nitride film) on sidewalls of the gate 46 of the peripheral region. A first gate spacer 52 having a structure of 50) / fifth oxide film 51) is formed.

Thereafter, a high concentration of impurity ions are implanted into the semiconductor substrate 40 using the gate 46 and the first gate spacer 52 of the peripheral region to form a source / drain region (not shown). Subsequently, after the fifth oxide film of the cell region is selectively removed, a third nitride film 53 is formed on the resultant from which the fifth oxide film of the cell region is selectively removed. At this time, the third nitride film 53 is formed to a thickness of 100 ~ 150Å.

Then, as shown in FIG. 2F, the third nitride film 53, the second nitride film 50, the fourth oxide film 49, the first nitride film 48, the third oxide film 47, and the like in the cell region. The second oxide film 42 and the first oxide film 41a are selectively etched to form NON (first nitride film 48 / fourth oxide film 49 / second and third nitride film on sidewalls of the gate 46 of the cell region. The second gate spacer 54 of the structure (50, 53) is formed.

As described above, the present invention forms a first oxide film pattern exposing a gate formation region on a substrate, and performs a gate formation and reoxidation process on a substrate between the first oxide film patterns through a second oxide film. As compared with the related art, an oxide layer thickness (corresponding to a thickness of the first oxide layer pattern and the second and third oxide layers) under the first and second gate spacers of the NONO and NON structures may be formed thicker.

Accordingly, the present invention can increase the physical distance between the portion where the charge trapping phenomenon occurs, that is, the interface between the interface between the first and second gate spacers and the third oxide layer below the channel region and the channel region. It is possible to prevent the lapping phenomenon from directly adversely affecting the channel region to prevent an increase in HCD and GIDL, and to prevent a decrease in junction BV, thereby improving the electrical characteristics of the device.

Claims (12)

Providing a semiconductor substrate having a cell region and a peripheral region defined therein; Forming a first oxide film on the semiconductor substrate; Selectively etching the first oxide film to form a first oxide pattern to expose a portion of the substrate corresponding to a gate formation region; Sequentially forming a second oxide film, a polycrystalline silicon film, a tungsten film, and a hard mask film on the entire surface of the substrate product on which the first oxide film pattern is formed; Patterning the hard mask film, the tungsten film, and the polysilicon film to form a gate on the second oxide film between the first oxide film patterns; Selectively oxidizing a surface of the exposed second oxide film and sidewalls of the polysilicon film remaining after etching to form a third oxide film; Sequentially forming a first nitride film, a fourth oxide film, a second nitride film, and a fifth oxide film on the resultant product on which the third oxide film is formed; The fifth oxide film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film pattern of the peripheral area are selectively etched to form a first gate spacer on the gate sidewall of the peripheral area. Forming; Selectively removing the fifth oxide film of the cell region; Forming a third nitride film on a product from which the fifth oxide film of the cell region is selectively removed; And The third nitride film, the second nitride film, the fourth oxide film, the first nitride film, the third oxide film, the second oxide film, and the first oxide film of the cell region are selectively etched to form a second gate spacer on the gate sidewall of the cell region. And forming a gate spacer of the semiconductor device. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein the first oxide layer is formed to a thickness of about 100 to about 180 microns. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, wherein the second oxide layer is formed to a thickness of 30 to 50 GPa. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, wherein the polysilicon film is formed to a thickness of 400 ~ 700 GPa. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the tungsten film is formed to a thickness of 300 ~ 600Å. Claim 6 was abandoned when the registration fee was paid. 2. The method of claim 1, wherein the hard mask film is formed to a thickness of 2000 to 2500 mW. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the third oxide layer is formed to a thickness of 20 to 50 GPa. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, wherein the first nitride film is formed to a thickness of 70 ~ 100 GPa. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the fourth oxide layer is formed to a thickness of about 80 to about 120 microns. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, wherein the second nitride layer is formed to a thickness of about 90 to about 150 microns. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, wherein the fifth oxide film is formed to a thickness of 400 ~ 600Å. Claim 12 was abandoned upon payment of a registration fee. The method of claim 1, wherein the third nitride film is formed to a thickness of about 100 to about 150 microns.

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