JPH07263677A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To precisely form a fine gate electrode, in a; MOS transistor. CONSTITUTION:An oxide film pattern 11 is formed in the specified region on a semiconductor substrate 1, and a side wall constituted of a doped polysilicon film 8b turning to a gate electrode 8 is formed on the oxide film pattern 11, which is eliminated. Thereby a fine gate electrode 8 whose gate length is equal to the width of the side wall is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
Particularly, it relates to a fine MOS transistor.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing the basic structure of a conventional MOS transistor. In the figure, 1 is a semiconductor substrate made of silicon single crystal or the like (hereinafter referred to as a substrate), 2
Is a gate insulating film formed on the substrate 1, 3 is a gate electrode formed on the substrate 1 via the gate insulating film 2, and 4 is a source electrode formed on both sides of the substrate 1 with the gate electrode 3 interposed therebetween.
The drain regions 5 are element isolation insulating films.

Next, a manufacturing method will be described below with reference to FIG. First, the gate insulating film 2 is formed on the entire surface of the substrate 1 by oxidizing the substrate 1 on which the element isolation insulating film 5 is formed, and impurities are introduced into the entire surface of the gate insulating film 2 so as to have conductivity. The doped polysilicon film 3a is formed by the CVD method. Then, a photoresist film is formed on the entire surface of the doped polysilicon film 3a and patterned by a photolithography technique to form a resist pattern 6 (FIG. 10A). Next, the resist pattern 6
Using as a mask, the underlying doped polysilicon film 3a is removed by anisotropic etching to form the gate electrode 3 (FIG. 10B). Next, using the gate electrode 3 as a mask, impurity ions are implanted from above the substrate 1 to form the source / drain regions 4, and the MOS transistor shown in FIG. 9 is formed.

[0004]

Since the conventional MOS transistor is constructed as described above, the gate electrode 3
The gate length L is determined by the size of the resist pattern 6 formed by the photolithography technique. By the way, the driving capability of a MOS transistor increases as the gate length decreases. Therefore, making the gate length fine requires both miniaturization and improvement of the driving capability. However, in the current photolithography technology, in order to reduce the dimension of the resist pattern 6 to 0.3 μm or less, an expensive device such as an excimer laser is used as a light source, and even if such an expensive device is used. The dimensional accuracy was poor. Therefore, the conventional MOS transistor has a problem that there is a limit to miniaturization of the gate length.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a MOS transistor having a fine gate electrode with high dimensional accuracy.

[0006]

[Means for Solving the Problems] Claim 1 according to the present invention
In the semiconductor device described above, the gate electrode is formed as a sidewall in a self-aligned manner with the sidewall of the pattern formed on the semiconductor substrate.

In the semiconductor device according to the second aspect of the present invention, the planar arrangement of the gate electrodes is formed in an annular shape, and one of the source / drain regions is located outside the gate electrode in a region surrounded by the gate electrode. The other of the source / drain regions is arranged in the region.

A semiconductor device according to a third aspect of the present invention is formed as a sidewall in a self-aligned manner with a substrate convex pattern provided on a semiconductor substrate and a sidewall of the substrate convex pattern via a gate insulating film. A gate electrode, one of the source / drain regions formed in the upper layer portion of the substrate convex pattern, and the other of the source / drain regions formed in the semiconductor substrate outside the convex pattern of the substrate with the gate electrode interposed therebetween. It was done.

According to a fourth aspect of the present invention, in the semiconductor device according to the fourth aspect, the gate electrode is asymmetric with respect to the lengthwise direction of the gate electrode, and is tapered toward the upper side of the semiconductor substrate. One of the sidewalls formed of the insulating film is larger than the other.

A semiconductor device according to a fifth aspect of the present invention is an LDD formed adjacent to a source / drain region.
A region, a first sidewall made of an insulating film formed on the gate electrode and on the sidewall of the substrate convex pattern upper layer portion, and a second sidewall made of an insulating film formed on the gate electrode sidewall. The LDD region is vertically adjacent to one of the source / drain regions formed in the upper layer of the substrate convex pattern and laterally adjacent to the other source / drain region. It is disposed below the second sidewall.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming an insulating film pattern in a predetermined region on a semiconductor substrate, and a gate covering the entire surface of the semiconductor substrate covering the insulating film pattern. A step of forming an insulating film and further forming a conductive film on the entire surface, and etching back the conductive film by anisotropic etching to leave sidewalls on the sidewalls of the insulating film pattern to form a gate electrode. And a step of forming source / drain regions after removing the insulating film pattern.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a substrate convex pattern on a semiconductor substrate by etching while leaving a predetermined region of the semiconductor substrate surface, and the substrate convex pattern. A step of forming a gate insulating film on the entire surface of the semiconductor substrate covering the pattern and further forming a conductive film on the entire surface, and etching back the conductive film by anisotropic etching to form the sidewalls of the substrate convex pattern. And the step of forming a gate electrode by leaving the sidewalls left behind, and then forming the source / drain regions.

A method of manufacturing a semiconductor device according to an eighth aspect of the present invention is a method of forming an insulating film pattern in a predetermined region on a semiconductor substrate, and covering the insulating film pattern with a gate on the entire surface of the semiconductor substrate. A step of forming an insulating film and further forming a conductive film on the entire surface thereof; and a step of etching back the conductive film by anisotropic etching to form a gate electrode as a sidewall on the side wall of the insulating film pattern, After removing the insulating film pattern, a step of implanting impurity ions using the gate electrode as a mask, an insulating film is formed on the entire surface of the semiconductor substrate to cover the gate electrode, and the insulating film is anisotropically etched. By etching back the entire surface to form sidewalls made of an insulating film on the side walls on both sides of the gate electrode, and a side wall made of this insulating film. And the said gate electrode by implanting again impurity ions as a mask, and a step of forming the source and drain regions and LDD regions adjacent thereto by subsequent heat treatment.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a substrate convex pattern on a semiconductor substrate by etching while leaving a predetermined region of the semiconductor substrate surface, and the substrate convex pattern. A step of forming a gate insulating film on the entire surface of the semiconductor substrate covering the pattern and further forming a conductive film on the entire surface, and etching back the conductive film by anisotropic etching to form the sidewalls of the substrate convex pattern. A step of forming a gate electrode by leaving a sidewall on the substrate, a step of implanting impurity ions using the gate electrode as a mask, and an insulating film covering the entire surface of the semiconductor substrate covering the convex pattern of the substrate and the gate electrode. The insulating film is formed, and the entire surface is etched back by anisotropic etching to form a first side wall on the side wall of the upper layer of the substrate convex pattern. Forming a second sidewall to the gate electrode side wall and, first and second
Impurity ion is implanted again by using the side wall and the gate electrode as a mask, and the subsequent heat treatment is performed to form the source / drain regions and the LDD regions adjacent thereto.

[0015]

In the semiconductor device according to the present invention, the gate electrode is formed as a sidewall of the pattern side wall formed on the semiconductor substrate in a self-aligned manner. Therefore, the size is determined by the resist pattern size formed by the photolithography technique. It is possible to obtain a finer gate electrode with higher dimensional accuracy than the conventional one. Moreover, since the planar arrangement of the gate electrodes is formed in a ring shape, it is easy to form the temporary pattern as a sidewall.

Since the gate electrode is formed as a sidewall on the side wall of the convex pattern of the substrate, one of the source / drain regions is formed on the upper layer of the convex pattern of the substrate and the other is formed outside the convex pattern of the substrate with the gate electrode interposed therebetween. The direction of the channel connecting the drain regions is L-shaped, and the effective gate length is the sum of the gate length and the height of the gate electrode.
Therefore, the required effective gate length can be secured, the gate electrode can be formed in a fine region, and miniaturization and high integration can be promoted.

Further, the source / drain regions are adjacent to each other and L
A structure having a DD region (hereinafter referred to as an LDD structure),
Since the gate electrodes are asymmetrical to each other and the sidewalls made of an insulating film formed on both sides of the gate electrodes have different sizes, it is possible to easily form the LDD regions having different areas on the source side and the drain side. Therefore, if the larger LDD region is used as the drain side, the hot carrier effect can be suppressed and the resistance on the source side can be reduced.

Also, when the gate electrode is formed on the side wall of the convex pattern of the substrate as the side wall, the LDD structure can be applied, and the electric field near the drain during transistor operation is relaxed to suppress the hot carrier effect. A fine gate electrode having high dimensional accuracy can be obtained.
Further, since the areas of the LDD regions on the source side and the drain side are different, using the larger LDD region as the drain side has the effect of suppressing the hot carrier effect and lowering the resistance on the source side.

Further, in the method for manufacturing a semiconductor device according to the present invention, since the side wall of the conductive film is formed as the gate electrode on the insulating film pattern to be removed in the subsequent step, the gate electrode is remarkably different from the conventional one. It can be formed finely, has good dimensional accuracy, is inexpensive, and can be easily miniaturized.

Further, since the convex pattern of the substrate is formed and the side wall of the conductive film is formed on the convex pattern to serve as the gate electrode, the gate electrode can be easily formed in a fine region with good dimensional accuracy and at a low cost. Is L-shaped, and the effective gate length can be easily secured.

Further, since the gate electrode is formed as the sidewall of the insulating film pattern, the shape of the gate electrode is left-right asymmetric. Since the sidewalls of the insulating film are formed on the sidewalls on both sides of the gate electrode to form the LDD structure,
Sidewall and LDD on the source and drain sides
Those with different area sizes can be easily manufactured.

Ion implantation is performed after forming the gate electrode on the side wall of the convex pattern of the substrate, and ion implantation is performed again after forming the first and second sidewalls. Therefore, at the time of the previous ion implantation, the impurity ions implanted from the side wall of the upper layer portion of the substrate convex pattern where the gate electrode is not formed form an LDD region in a deep region adjacent to the source / drain formation region. Further, outside the convex pattern of the substrate, the LDD region is formed under the second sidewall formation region. Thus, in the portion where the channel direction is the vertical direction, the LDD region is adjacent to the source / drain region in the vertical direction, and in the portion where the channel direction is the horizontal direction, the LDD structure can be easily formed in the lateral direction. Furthermore, because of the difference between the vertical direction and the horizontal direction between the source side and the drain side, the sidewall and LD
Since the D region has a different shape, size, etc., if the larger LDD region is used as the drain side, the hot carrier effect can be suppressed and the resistance on the source side can be lowered.

[0023]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the same parts as those of the conventional technique will be appropriately omitted. 1 is a plan view showing a basic structure of a MOS transistor according to a first embodiment of the present invention, and FIG.
It is sectional drawing by the II line of FIG. In the figure, 1 and 5 are the same as the conventional ones, 7 is an active region surrounded by the element isolation insulating film 5, 8 is a gate electrode formed in a fine annular shape, 8a is a pad portion of the gate electrode, 9 Is the gate electrode 8
The gate insulating film formed on the substrate 1 immediately below is a source / drain region formed in the active region 7 surrounded by the ring-shaped gate electrode 8 while 10b is the outside of the ring-shaped gate electrode 8. It is the other of the source / drain regions formed in the region 7.

Next, the manufacturing method will be described below with reference to FIG. First, the substrate 1 on which the element isolation insulating film 5 is formed
An oxide film is deposited on the entire upper surface, a photoresist film is formed on the entire upper surface, and patterned by a photolithography technique. By etching the underlying oxide film with this resist pattern and then removing the photoresist film, an oxide film pattern 11 as an insulating film pattern is formed in a predetermined region on the substrate 1 (FIG. 3A). Next, the gate insulating film 9 is formed on the entire surface of the substrate 1, and the doped polysilicon film 8b as a conductive film is formed on the entire surface of the substrate 1 by the CVD method (FIG. 3B).

Next, in a later step, the gate electrode pad portion 8a is formed.
A resist pattern is formed in a region to be formed, and the doped polysilicon film 8b is etched back using anisotropic etching so that a predetermined overetch amount is obtained by using the resist pattern as a mask. Then, the gate electrode 8 is formed by leaving the sidewall on the sidewall of the oxide film pattern 11. Then, the resist pattern is removed. At this time, the width of the side wall having the gate length L is 80 to 90% of the film thickness when the doped polysilicon film 8b is formed (FIG. 3C). Then, using dry etching,
The oxide film pattern 11 and the gate insulating film 9 other than the region where the gate electrode 8 is formed are removed (FIG. 3D). Next, the source / drain regions 10a and 10b are formed by implanting impurity ions from the substrate 1 by the ion implantation method and diffusing them in the subsequent heat treatment. As a result, two MOS transistors having one of the source / drain regions 10a in common are formed (see FIG. 2). After that, after forming an interlayer insulating film, a contact hole is formed, and the gate electrode 8, the source / drain region 10a,
Forming a metal wiring layer connected to each 10b
Complete the transistor (not shown).

In the MOS transistor thus formed, the gate electrode 8 is formed as a sidewall of the oxide film pattern 11 which will be removed in a later step, and has a fine gate length L around the oxide film pattern 11. It is formed in a ring shape. The gate length L is formed to have a size of 80 to 90% of the film thickness when the doped polysilicon film 8b forming the gate electrode 8 is deposited, and can be formed to about 0.15 μm. This is because, when the resolution limit of lithography is 0.4 μm, the gate length dimension can be equal to or less than this resolution limit value, and can be remarkably miniaturized as compared with the conventional one. Further, the film thickness of the doped polysilicon film 8b can be kept uniform within about ± 5% at present, and the anisotropic etching during sidewall formation has little influence on the dimensions. The gate length L has good uniformity and can be formed with high precision.

Example 2. After forming the ring-shaped gate electrode 8, it may be partially removed using a resist mask to form a linear pattern as in the conventional case. In this case, the resolution limit value of lithography that cannot be obtained by the conventional method. The following linear gate electrode 8 having a fine and uniform gate length can be formed.

Example 3. The oxide film pattern 11 may be formed only in the central portion of the active region 7 and the gate electrode 8 may be formed only in the active region 7 as shown in the plan view of FIG. In this case, since the source / drain region 10b formed outside the gate electrode 8 is one region, the number of MOS transistors is one.

Example 4. Further, the MOS transistor may have an LDD structure having LDD regions 12a and 12b adjacent to the source / drain regions 10a and 10b, and this case is shown in FIG. In the same manner as in Example 1 above, the gate insulating film 9 and the gate electrode 8 are formed on the substrate 1,
Impurity ions are implanted from above the substrate 1 using oblique rotation ion implantation (FIG. 5A), and then CVD is performed on the entire surface of the substrate 1.
The oxide film 13 is formed as an insulating film using TEOS by the method (FIG. 5B). Next, the entire surface of the oxide film 13 is etched back by anisotropic etching to form second side walls 13a and 13b on the side walls of the gate electrode 8, and then impurity ions are injected again from above the substrate 1 and then diffused. Source / drain regions 10a, 10b and L
DD regions 12a and 12b are formed (FIG. 5C).

MOS of LDD structure formed in this way
In the transistor, since the gate electrode 8 is formed as the sidewall, the transistor has a laterally asymmetrical shape and has a shape that tapers upward. Therefore, the second sidewalls 13a and 13b formed on the sidewalls of the gate electrode 8 are the sidewalls 1 formed on the oxide film pattern 11 forming region.
3a becomes larger in height and width, and the lengths of the LDD regions 12a and 12b in the channel direction are also larger in the LDD region 1.
2a is longer. Therefore, such a MOS transistor has the same effect as that of the first embodiment, and the LD
When the one having the D region 12a is used as the drain region 10a, the electric field relaxation in the vicinity of the drain can be achieved by lowering the resistance on the source side, which is particularly effective.

Example 5. Next, a MOS transistor according to a fifth embodiment of the present invention will be described with reference to FIG. In the figure, reference numerals 1, 5 and 7 are the same as those in the first embodiment, 14 is a substrate convex pattern formed in a predetermined region on the substrate 1, 15 is a gate electrode formed on the sidewall of the substrate convex pattern 14, and 16 is a gate insulating film. , 17a, 17b are source / drain regions.

Next, the manufacturing method will be described below with reference to FIG. First, a photoresist film is formed on the entire surface of the substrate 1 and patterned by the photolithography technique. The substrate 1 is etched using this resist pattern as a mask,
After that, the photoresist film is removed to form the substrate convex pattern 14, and then the inter-element isolation insulating film 5 is formed (FIG. 7A). Next, a gate insulating film 16 is formed on the entire surface of the substrate 1 on which the substrate convex pattern 14 is formed,
A doped polysilicon film 15a as a conductive film is formed on the entire surface by CVD (FIG. 7B).

Next, a resist pattern is formed in a region which will be a pad portion of the gate electrode in a later step, and using this as a mask, the doped polysilicon film 15a is anisotropically etched to a predetermined overetch amount. Is etched back using the gate insulating film 16 on the side wall of the convex pattern 14 of the substrate.
A side wall is formed via the gate electrode pad portion and the gate electrode pad portion is left to form a gate electrode 15. After that, the resist pattern is removed. (Fig. 7
(C)). Next, the source / drain regions 17a and 17b are formed by implanting impurity ions from above the substrate 1 by the ion implantation method and diffusing them in the subsequent heat treatment. At this time, one of the source / drain regions 17a is
By properly setting the implantation energy and heat treatment conditions, the gate electrode 15 is formed only on the upper layer portion where the gate electrode 15 is not formed on the side wall of the substrate convex pattern 14 (FIG. 6).
reference). After that, the same processing as that of the first embodiment is applied to the MOS.
Complete the transistor.

In the MOS transistor formed as described above, the gate electrode 15 serves as a sidewall of the convex pattern 14 of the substrate, and has a fine width L ₁ around the sidewall, which is equal to or smaller than the lithography resolution limit value, as in the first embodiment. It is formed. The substrate convex pattern 14 remains when the MOS transistor is completed, and one of the source / drain regions is formed on the upper layer portion thereof.
Since 7a is formed, the gate electrode 15 having the effective gate length L ₂ (L ₁ + height of the gate electrode 15) is formed in the region of the dimension L ₁ , and the direction of the channel connecting the source / drain regions 17a and 17b is The substrate 1 has an L shape in which a vertical direction and a parallel direction are combined. The uniformity of the effective gate length L ₂ at this time depends on the uniformity of the film thickness when the doped polysilicon film 15a is formed and the anisotropic etching when the sidewall is formed. As described above, in the MOS transistor according to the fifth embodiment, the gate electrode 15 having the effective gate length L ₂ has a much smaller dimension L ₁ than the conventional _one.
Can be formed in the region of, and miniaturization and high integration can be promoted.

Example 6. Also in the MOS transistor according to the fifth embodiment, the LDD regions 18a and 18b can be formed to have the LDD structure, which will be described below with reference to FIG.
Similar to the fifth embodiment, the substrate convex pattern 14 is formed on the substrate 1.
After forming the inter-element isolation insulating film, the gate insulating film 16 and the gate electrode 15 are formed, and impurity ions are implanted from above the substrate 1 using oblique rotation ion implantation (see FIG.
(A)), and then TE is deposited on the entire surface of the substrate 1 by the CVD method.
An oxide film 19 is formed as an insulating film using OS (FIG. 8B). Next, the entire surface of the oxide film 19 is etched back by anisotropic etching to form a first sidewall 19a on the side wall of the upper layer portion of the substrate convex pattern 14 on the gate electrode 15.
And the second sidewall 19b on the side wall of the gate electrode 15
To form these first and second sidewalls 1
Impurity ions are implanted again using 9a and 19b as masks, and then diffused to form source / drain regions 17a and 1a.
7b and LDD regions 18a, 18b are formed (FIG. 8).
(C)). In the sixth embodiment, since the first and second sidewalls 19a and 19b are formed, the substrate convex pattern 14 needs to be formed higher than the fifth embodiment in advance.

In the MOS transistor thus formed, when the oblique rotation ion implantation after the gate electrode 15 is formed, the impurity ions implanted from the side wall of the upper layer portion of the substrate convex pattern 14 where the gate electrode 15 is not formed are The LDD region 18a is formed in the deep region. So the source
One of the drain regions 17a and the LDD region 18a are vertically adjacent to each other. On the outer side of the substrate convex pattern 14, the other source / drain region 17b and the LDD region 18b are adjacent to each other in the normal lateral direction. As described above, the MOS transistor according to the sixth embodiment has the same effect as that of the fifth embodiment and the LDD regions 18a and 18b.
Is inserted in series between the source and drain, so it also has the effect of relaxing the electric field near the drain. Moreover, the first and second sidewalls 19a and 19b and the two LDDs
Since the regions 18a and 18b are different from each other in size and shape, using the larger one of the LDD regions 18a and 18b as the drain side has the effect of reducing the resistance on the source side and relaxing the electric field near the drain. is there.

[0037]

As described above, according to the present invention, the gate electrode is formed in a self-aligned manner as the sidewall of the insulating film pattern or the convex pattern of the substrate. A highly accurate gate electrode can be obtained inexpensively and easily. Further, when the gate electrode is arranged in a ring shape, it can be easily formed as a sidewall. Further, since the gate electrode is formed as the side wall of the convex pattern of the substrate that remains at the time of completion, the channel direction can be made L-shaped, and the effective gate length can be secured to promote miniaturization. Further, the gate electrode structure has an LDD
It can be applied to a transistor having a structure and has the same effect, and also suppresses the hot carrier effect by relaxing the electric field near the drain. Moreover, since the LDD regions on the source side and the drain side are formed asymmetrically, if the larger LDD region is used on the drain side, the resistance on the source side can be reduced and the electric field near the drain can be relaxed, which is effective. Is.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a plan view showing the structure of a semiconductor device according to a third embodiment of the invention.

FIG. 5 is a sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor substrate 8 gate electrode 8b doped polysilicon film 9 as a conductive film 9 gate insulating film 10a, 10b source / drain region 11 oxide film pattern 12a, 12b LDD region 13 oxide film 13a as an insulating film 13b Second sidewall made of insulating film 14 Substrate convex pattern 15 Gate electrode 15a Doped polysilicon film 16 as conductive film Gate insulating film 17a, 17b Source / drain region 18a, 18b LDD region 19 Oxide film as insulating film 19a First sidewall 19b Second sidewall

Claims (9)

[Claims] 1. A semiconductor device having a gate electrode formed on a semiconductor substrate via a gate insulating film and a source / drain region, wherein the gate electrode is a sidewall of a pattern formed on the semiconductor substrate. A semiconductor device, characterized in that it is formed as a sidewall in a self-aligned manner. 2. A planar arrangement of gate electrodes is formed in a ring shape, one of the source / drain regions is arranged in a region surrounded by the gate electrode, and the other of the source / drain regions is arranged in a region outside the gate electrode. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 3. A substrate convex pattern provided on a semiconductor substrate, a gate electrode formed on the sidewall of the substrate convex pattern as a sidewall in a self-aligned manner via a gate insulating film, and an upper layer portion of the substrate convex pattern. Formed sauce
A semiconductor device having one of the drain regions and the other of the source / drain regions formed on the semiconductor substrate outside the convex pattern of the substrate with the gate electrode interposed therebetween. 4. A gate electrode formed on a semiconductor substrate via a gate insulating film, sidewalls made of an insulating film formed on sidewalls on both sides of the gate electrode, and formed on both sides below the gate electrode. LDD region and this LDD
In a semiconductor device having a source / drain region formed adjacent to a region, the gate electrode is asymmetric with respect to a gate electrode length direction, and has a tapered shape toward the upper side of the semiconductor substrate, and A semiconductor device, wherein one side wall formed of the insulating film on both sides of the gate electrode is larger than the other side wall. 5. An LDD region formed adjacent to the source / drain region, a first sidewall made of an insulating film formed on the gate electrode and on the sidewall of the substrate convex pattern upper layer portion, and the gate electrode. A second sidewall made of an insulating film formed on a sidewall, and the LDD region is vertically adjacent to one of the source / drain regions formed in the upper layer portion of the substrate convex pattern. 4. The semiconductor device according to claim 3, wherein the other source / drain region is laterally adjacent to and disposed under the second sidewall. 6. A step of forming an insulating film pattern in a predetermined region on a semiconductor substrate, a gate insulating film is formed on the entire surface of the semiconductor substrate so as to cover the insulating film pattern, and a conductive film is formed on the entire surface of the gate insulating film. A step of forming a gate electrode by etching back the conductive film by anisotropic etching to leave a sidewall on the side wall of the insulating film pattern, and then removing the insulating film pattern, and then removing the source. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising: a step of forming a drain region. 7. A step of forming a substrate convex pattern on a semiconductor substrate by etching while leaving a predetermined region of the semiconductor substrate surface, and a gate insulating film covering the entire surface of the semiconductor substrate covering the substrate convex pattern. And forming a conductive film over the entire surface thereof, and a step of etching back the conductive film by anisotropic etching to leave sidewalls on the sidewalls of the convex pattern of the substrate to form a gate electrode. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming source / drain regions. 8. A step of forming an insulating film pattern in a predetermined region on a semiconductor substrate, a gate insulating film is formed on the entire surface of the semiconductor substrate so as to cover the insulating film pattern, and a conductive film is formed on the entire surface of the gate insulating film. A step of forming a gate electrode as a sidewall on the sidewall of the insulating film pattern by etching back the conductive film by anisotropic etching, and removing the insulating film pattern, and then masking the gate electrode. As a step of implanting impurity ions as above, an insulating film is formed on the entire surface of the semiconductor substrate so as to cover the gate electrode, and the insulating film is etched back by anisotropic etching to insulate the side walls on both sides of the gate electrode. A step of forming a side wall made of a film, and a step of forming impurity ions again using the side wall made of this insulating film and the gate electrode as a mask 5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of implanting and then forming a source / drain region and an LDD region adjacent thereto by heat treatment. 9. A step of forming a convex pattern of a substrate on a semiconductor substrate by etching while leaving a predetermined region of the surface of the semiconductor substrate, and a gate insulating film covering the convex pattern of the substrate and covering the entire surface of the semiconductor substrate. And forming a conductive film over the entire surface thereof, and a step of etching back the conductive film by anisotropic etching to leave sidewalls on the sidewalls of the convex pattern of the substrate to form a gate electrode. A step of implanting impurity ions using the gate electrode as a mask, forming an insulating film on the entire surface of the semiconductor substrate covering the convex pattern of the substrate and the gate electrode, and etching the insulating film by anisotropic etching. Back, a first sidewall is formed on the sidewall of the substrate convex pattern upper layer portion and a second sidewall is formed on the gate electrode sidewall. And the first and second
6. The step of implanting impurity ions again using the side wall of the above and the gate electrode as a mask, and then performing a heat treatment to form a source / drain region and an LDD region adjacent thereto. Manufacturing method of semiconductor device.