KR100587593B1 - Method of making selective silicide using cmp - Google Patents

Abstract

The present invention relates to a method of forming a selective silicide using chemical mechanical polishing, and by selectively forming silicide in a source / drain or a gate to obtain an optical characteristic required in an optical device, dark signal characteristics may be improved in a non-silicide region. And a technique capable of lowering the resistance in the silicide region. The selective silicide formation method using the CMP of the present invention for forming a gate and gate spacer on a semiconductor substrate formed with a shallow trench isolation (STI) film; Performing a N + / P + ion implantation process on the structure to form a source / drain region; Forming an oxide film to a predetermined thickness on the structure; Planarizing the oxide layer to expose the upper portion of the gate by a chemical mechanical polishing (CMP) process; Forming a mask pattern to open a first region for forming silicide in the source / drain region and close a second region in the source / drain region that does not form silicide; Etching the oxide layer using the mask pattern as a barrier so that the first region for forming silicide is exposed; Removing the photoresist film used as the mask pattern; And forming a silicide layer on the first region and the gate by performing an annealing process after forming a metal layer for forming the silicide layer on the structure.

Description

Selective silicide formation method using chemical mechanical polishing {METHOD OF MAKING SELECTIVE SILICIDE USING CMP}

1 to 4 are cross-sectional views illustrating a method of forming a selective silicide using chemical mechanical polishing according to the present invention.

(Explanation of symbols for the main parts of the drawing)

1: silicon substrate 2: shallow trench separator

3: gate oxide film 4: gate polysilicon film

5: LDD spacer or gate spacer

6: source / drain area or active area

7: oxide film (SiO ₂ )

8 mask pattern or photoresist film 9 silicide film

The present invention relates to a method of forming a selective silicide using chemical mechanical polishing (CMP), and in particular, between a source / drain or a gate including an image sensor. The present invention relates to a method for forming a selective silicide using CMP which selectively forms silicide.

In the semiconductor manufacturing process, especially in the logic device manufacturing process, silicide is applied to reduce the resistance because the operation speed of the device is a very important factor. This silicide forming process deposits metal and forms metal silicide by thermal process, in which silicide is formed only on the active region made of silicon and polysilicon, which is a gate forming material, but not on the remaining insulating material. Self-aligned silicide process is adopted. In particular, as the gate line width decreases to 0.18 μm or less, cobalt silicide having excellent resistance and stability is being applied.

However, since the silicide-formed region is very low in resistance, it is not applicable in the region where a high resistance is required, and thus the non-salicide which covers the region where the silicide should not be formed with an insulating film and forms silicide in other regions. (Non-Salicide) process is required.

The non-salicide process deposits an insulating film on the entire surface of the wafer before forming the salicide, and protects the insulating film in the non-salicide region using a photo mask, and the insulating film in the silicide forming region Will be removed.

The formation of silicides is simultaneously formed in the source / drain and gate regions and in the prior art the formation of selective silicides was limited to the distinction between active and field and the distinction between source / drain / gate and gate spacers. Formation of such selective silicides was possible by selectively forming SiO ₂ . However, when non-silicide is to be formed in the source / drain only in a portion of the die, as in the case of an optical device, it is difficult to apply a method of forming a selective silicide using SiO ₂ as it is. . In other words, silicide is simultaneously formed in the gate / source / drain region through a silicidation process. Since the source / drain of the optical device must be non-silicide, the source / drain of the optical device is changed to SiO ₂ . While protecting, the silicide must be formed on the upper electrode of the gate.

When silicide is formed in the source / drain region of the optical device, the optical transparency becomes inferior and the dark signal increases, resulting in poor optical characteristics. As an alternative to overcome this disadvantage, SiO ₂ is deposited after the ion implantation process, followed by SOG etchback and photo / etch processes to selectively form silicide. .

However, the difficulty of application is high because of the difficulty and complexity of the additional process.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to form non-silicide by selectively forming silicide in a source / drain or a gate to obtain optical characteristics required in an optical device. The present invention provides a selective silicide formation method using CMP which can improve the dark signal characteristics in the region and lower the resistance in the silicide region.

Selective silicide forming method using CMP according to the present invention for achieving the above object,

Forming a gate and a gate spacer on a semiconductor substrate on which a shallow trench isolation (STI) film is formed;

Performing a N + / P + ion implantation process on the structure to form a source / drain region;

Forming an oxide film to a predetermined thickness on the structure;

Planarizing the oxide layer to expose the upper portion of the gate by a chemical mechanical polishing (CMP) process;

Forming a mask pattern to open a first region for forming silicide in the source / drain region and close a second region in the source / drain region that does not form silicide;

Etching the oxide layer using the mask pattern as a barrier so that the first region for forming silicide is exposed;

Removing the photoresist film used as the mask pattern; And

And forming a silicide film on the first region and the gate by performing an annealing process after forming a metal film for forming the silicide film on the structure.

The oxide film may be formed to be larger than or equal to the thickness of the gate.

The chemical mechanical polishing (CMP) of the oxide film is characterized in that overpolishing is performed within 300 kPa from the uppermost part of the gate.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views illustrating a method of forming a selective silicide using CMP according to the present invention.

First, as shown in FIG. 1, a shallow trench isolation (STI) film 2 for device isolation is formed on a silicon (Si) substrate 1. At this time, the STI film 2 is filled with an insulating film (or an oxide film) and processes a region other than active by a chemical mechanical polishing (CMP) process (planarization).

Then, P wells and N wells are formed in the silicon substrate 1.

Next, after the gate oxide film 3 and the polysilicon film 4 are deposited, a gate electrode is formed through a patterning process. At this time, the polysilicon film 4 is isotropically etched.

Next, NM / PM ions are implanted onto the structure.

Next, ion implantation is performed to form an LDD diffusion layer in the silicon substrate 1.

Next, the LDD spacers 5 are formed on the sidewalls of the gate, and the source / drain regions 6 are formed by performing an N + / P + ion implantation process.

Next, an oxide film (SiO ₂ ) 7 is formed on the upper structure. At this time, the thickness of the oxide film (SiO ₂ ) 7 is greater than the thickness of the polysilicon film 4 serving as a gate so as to be sufficient to remove a step caused by poly in a subsequent CMP process.

Next, as shown in FIG. 2, the oxide film (SiO ₂ ) 7 is planarized so that the top of the polysilicon film 4 is exposed by using a CMP process to remove the step by the gate.

Next, as shown in FIG. 3, the region 6a of the source / drain region to which silicide is to be opened is opened and the region 6b of the source / drain region to which non-silicide is to be formed is closed. The mask pattern 8 is formed so as to close.

Next, as shown in FIG. 4, when the oxide layer (SiO ₂ ) 7 is etched using the mask pattern 8 as a barrier, the source / drain region of the site where silicide is to be formed is exposed.

Then, the photoresist film 8 used as the mask pattern 8 is removed.

Next, a metal film (not shown) for forming a silicide film is formed on the structure, and then an annealing process is performed. As a result, a silicide film 9 is formed on the exposed gate electrode 4 and the source / drain region 6a, and the source / drain region 6b covered with the oxide film (SiO ₂ ) 7 is formed. It remains as a sieve (Non-silicide).

As described above, according to the selective silicide forming method using CMP according to the present invention, the gate electrode (poly) is exposed and the photo and etching process is applied by applying the CMP process before the conventional selective silicide forming process using SiO. By selectively exposing the portion of the source / drain region to be silicide-formed, the gate electrode and the source / drain are silicided in a subsequent silicide formation process, and the source / drain region of the optical element covered with SiO It is possible to obtain an optical device having a high optical transparency and low dark signal due to non-silicide.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Forming a gate and a gate spacer on each of the semiconductor substrates having first and second regions in which a shallow trench isolation (STI) film is formed; Forming a source / drain region by performing an N + / P + ion implantation process on the exposed portion of the semiconductor substrate using the structure as a mask; Forming an oxide film on the semiconductor substrate to cover the gate and the gate spacer; Polishing and oxidizing the oxide layer to expose the upper portion of the gate by a chemical mechanical polishing (CMP) process; Forming a mask pattern with a photoresist film so as to open a first region for forming silicide in the source / drain region and close a second region in which the silicide is not formed in the source / drain region; Etching the oxide layer to expose the source / drain regions in the first region opened using the mask pattern as a barrier; Removing the photoresist film used as the mask pattern; And Depositing a metal film on the structure and then annealing to form a silicide film on the exposed source / drain region and the gate of the first region, using chemical mechanical polishing (CMP). Selective silicide formation method. The method of claim 1, The thickness of the oxide film is formed to be greater than or equal to the thickness of the gate selective silicide forming method using chemical mechanical polishing (CMP). The method of claim 1, Selective silicide forming method using chemical mechanical polishing (CMP) characterized in that when performing the mechanical mechanical polishing (CMP) overpolishing within 300 kPa from the top layer of the gate.

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