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JPS6181229U - - Google Patents

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Publication number
JPS6181229U
JPS6181229U JP16444185U JP16444185U JPS6181229U JP S6181229 U JPS6181229 U JP S6181229U JP 16444185 U JP16444185 U JP 16444185U JP 16444185 U JP16444185 U JP 16444185U JP S6181229 U JPS6181229 U JP S6181229U
Authority
JP
Japan
Prior art keywords
type mos
mos transistor
inverter
type
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16444185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16444185U priority Critical patent/JPS6181229U/ja
Publication of JPS6181229U publication Critical patent/JPS6181229U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案による実施例を示す回路図、第
２図は同実施例の動作を説明するための信号波形
図、第３図は従来の回路図、第４図は同従来回路
を説明するための信号波形図である。 Ｑ１，Ｑ２，Ｑ３，Ｑ４：Ｅ型ＭＯＳトランジ
スタ、Ｑ０：Ｄ型ＭＯＳトランジスタ、ＣＢ：帰
還容量、ＣＧ：ゲート容量、ＣＬ：負荷容量。 Fig. 1 is a circuit diagram showing an embodiment according to the present invention, Fig. 2 is a signal waveform diagram for explaining the operation of the embodiment, Fig. 3 is a conventional circuit diagram, and Fig. 4 is an explanation of the conventional circuit. FIG. 3 is a signal waveform diagram for Q 1 , Q 2 , Q 3 , Q 4 : E-type MOS transistor, Q 0 : D-type MOS transistor, CB: Feedback capacitance, CG: Gate capacitance, CL: Load capacitance.

Claims (1)

【実用新案登録請求の範囲】 入力信号がゲートに与えられたＥ型ＭＯＳトラ
ンジスタと、ゲートがソースに接続されたＤ型Ｍ
ＯＳトランジスタからなるインバータと、 上記インバータのＤ型ＭＯＳトランジスタのド
レイン側と電源に挿入された、ゲートがドレイン
に接続されたＥ型ＭＯＳトランジスタと、 上記インバータの出力に一方のＥ型ＭＯＳトラ
ンジスタのゲートが接続され、他方のＥ型ＭＯＳ
トランジスタのゲートが入力端子に接続されたＥ
／Ｅ型プツシユプルバツフアを設け、 該プツシユプルバツフアの両ＭＯＳトランジス
タ接続点と、上記インバータのＤ型ＭＯＳトラン
ジスタと付加されたＥ型ＭＯＳトランジスタとの
接続点間に帰還容量ＣＢを接続してなるブートス
トラツパバツフア回路。[Claims for Utility Model Registration] An E-type MOS transistor whose gate is given an input signal, and a D-type M whose gate is connected to its source.
an inverter consisting of an OS transistor; an E-type MOS transistor whose gate is connected to the drain and inserted into the drain side of the D-type MOS transistor of the inverter and the power supply; and the gate of one E-type MOS transistor connected to the output of the inverter. is connected, and the other E type MOS
E with the gate of the transistor connected to the input terminal
/E-type push-pull buffer is provided, and a feedback capacitor CB is provided between the connection point of both MOS transistors of the push-pull buffer and the connection point of the D-type MOS transistor of the inverter and the added E-type MOS transistor. A bootstrapper buffer circuit is connected.
JP16444185U 1985-10-23 1985-10-23 Pending JPS6181229U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16444185U JPS6181229U (en) 1985-10-23 1985-10-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16444185U JPS6181229U (en) 1985-10-23 1985-10-23

Publications (1)

Publication Number Publication Date
JPS6181229U true JPS6181229U (en) 1986-05-29

Family

ID=30722304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16444185U Pending JPS6181229U (en) 1985-10-23 1985-10-23

Country Status (1)

Country Link
JP (1) JPS6181229U (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012095293A (en) * 2011-10-14 2012-05-17 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013229902A (en) * 2013-06-14 2013-11-07 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013229888A (en) * 2010-02-23 2013-11-07 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
US8586991B2 (en) 2001-08-10 2013-11-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2014222892A (en) * 2014-06-18 2014-11-27 株式会社半導体エネルギー研究所 Semiconductor device, display device, and electronic apparatus
JP2015144459A (en) * 2015-03-04 2015-08-06 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2016177297A (en) * 2016-04-28 2016-10-06 株式会社半導体エネルギー研究所 Semiconductor layer, display device, display module and electronic apparatus
JP2017142529A (en) * 2017-04-20 2017-08-17 株式会社半導体エネルギー研究所 Semiconductor device, display device, display module, and electronic apparatus
JP2018170780A (en) * 2018-06-15 2018-11-01 株式会社半導体エネルギー研究所 Electronic apparatus

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8586991B2 (en) 2001-08-10 2013-11-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8841680B2 (en) 2001-08-10 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2013229888A (en) * 2010-02-23 2013-11-07 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
JP2012095293A (en) * 2011-10-14 2012-05-17 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013229902A (en) * 2013-06-14 2013-11-07 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2014222892A (en) * 2014-06-18 2014-11-27 株式会社半導体エネルギー研究所 Semiconductor device, display device, and electronic apparatus
JP2015144459A (en) * 2015-03-04 2015-08-06 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP2016177297A (en) * 2016-04-28 2016-10-06 株式会社半導体エネルギー研究所 Semiconductor layer, display device, display module and electronic apparatus
JP2017142529A (en) * 2017-04-20 2017-08-17 株式会社半導体エネルギー研究所 Semiconductor device, display device, display module, and electronic apparatus
JP2018170780A (en) * 2018-06-15 2018-11-01 株式会社半導体エネルギー研究所 Electronic apparatus

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