JPS62117841U - - Google Patents
Info
- Publication number
- JPS62117841U JPS62117841U JP532686U JP532686U JPS62117841U JP S62117841 U JPS62117841 U JP S62117841U JP 532686 U JP532686 U JP 532686U JP 532686 U JP532686 U JP 532686U JP S62117841 U JPS62117841 U JP S62117841U
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- gate
- connection point
- input
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図及び第２図は本考案の実施例を示す回路
図、第３図及び第４図は第１図及び第２図に示さ
れた実施例の動作を示す波形図、第５図及び第６
図は従来例を示す回路図である。
１３，１８…第１のＭＯＳＦＥＴ、１４，１９
…第２のＭＯＳＦＥＴ、１５，２２…インバータ
、１６，２０…Ｐチヤンネル型ＭＯＳＦＥＴ、１
７，２１…Ｎチヤンネル型ＭＯＳＦＥＴ。
1 and 2 are circuit diagrams showing an embodiment of the present invention, FIGS. 3 and 4 are waveform diagrams showing the operation of the embodiment shown in FIGS. 1 and 2, and FIGS. 6th
The figure is a circuit diagram showing a conventional example. 13, 18...first MOSFET, 14, 19
...Second MOSFET, 15,22...Inverter, 16,20...P channel type MOSFET, 1
7, 21...N channel type MOSFET.
Claims (1)
のＭＯＳＦＥＴ及び第２のＭＯＳＦＥＴと、他方
の接続点が入力に接続されたインバータと、該イ
ンバータの入力と電源間に接続され前記インバー
タの出力がゲートに印加されたＰチヤンネルＭＯ
ＳＦＥＴと、前記インバータの入力と接地間に接
続され前記インバータの出力がゲートに印加され
たＮチヤンネルＭＯＳＦＥＴとを備え、前記第１
のＭＯＳＦＥＴのゲートが一方の接続点に接続さ
れ前記第２のＭＯＳＦＥＴのゲートが他方の接続
点に接続されて成るシユミツト回路。 The first one is connected in parallel and has one connection point as the input end.
and a second MOSFET, an inverter whose other connection point is connected to the input, and a P-channel MOSFET connected between the input of the inverter and a power supply and whose gate is applied with the output of the inverter.
SFET, and an N-channel MOSFET connected between the input of the inverter and ground and having the output of the inverter applied to the gate, the first
A Schmitt circuit comprising a gate of a second MOSFET connected to one connection point and a gate of the second MOSFET connected to another connection point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP532686U JPS62117841U (en) | 1986-01-17 | 1986-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP532686U JPS62117841U (en) | 1986-01-17 | 1986-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62117841U true JPS62117841U (en) | 1987-07-27 |
Family
ID=30786806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP532686U Pending JPS62117841U (en) | 1986-01-17 | 1986-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62117841U (en) |
-
1986
- 1986-01-17 JP JP532686U patent/JPS62117841U/ja active Pending