JPS6157631U - - Google Patents
Info
- Publication number
- JPS6157631U JPS6157631U JP14023384U JP14023384U JPS6157631U JP S6157631 U JPS6157631 U JP S6157631U JP 14023384 U JP14023384 U JP 14023384U JP 14023384 U JP14023384 U JP 14023384U JP S6157631 U JPS6157631 U JP S6157631U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- connection point
- mos transistor
- inverter
- connection diagram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 10
Landscapes
- Logic Circuits (AREA)
Description
第１図はこの考案の一実施例の接続図、第２図
はこの考案の他の実施例の接続図、第３図はこの
考案の更に他の実施例の接続図、第４図はこの考
案の更に他の実施例の説明に用いる各部波形図、
第５図は従来のＭＯＳインバータの一例の接続図
、第６図は従来のＭＯＳインバータの他の例の接
続図、第７図は従来のＭＯＳインバータを２段接
続した構成の接続図、第８図は第７図の構成の説
明に用いる各部波形図である。
１，２，１１，１２：ＭＯＳトランジスタ、３
，１３：入力端子、５，１５：電圧リミツト用の
ＭＯＳトランジスタ、６，１６：出力端子。
Fig. 1 is a connection diagram of one embodiment of this invention, Fig. 2 is a connection diagram of another embodiment of this invention, Fig. 3 is a connection diagram of yet another embodiment of this invention, and Fig. 4 is a connection diagram of another embodiment of this invention. Waveform diagrams of various parts used to explain still other embodiments of the invention,
Fig. 5 is a connection diagram of an example of a conventional MOS inverter, Fig. 6 is a connection diagram of another example of a conventional MOS inverter, Fig. 7 is a connection diagram of a configuration in which two stages of conventional MOS inverters are connected, and Fig. 8 is a connection diagram of an example of a conventional MOS inverter. The figure is a waveform diagram of each part used to explain the configuration of FIG. 7. 1, 2, 11, 12: MOS transistor, 3
, 13: input terminal, 5, 15: MOS transistor for voltage limit, 6, 16: output terminal.
Claims (1)
ンジスタとが接続され、この接続点から出力を取
り出すようにしたＭＯＳインバータにおいて、 上記接続点及び基準電位間に電圧リミツト用の
ダイオード接続のＭＯＳトランジスタを接続する
ようにしたことを特徴とするＭＯＳインバータ。[Claims for Utility Model Registration] In a MOS inverter in which a drive MOS transistor and a load MOS transistor are connected and the output is taken out from this connection point, a diode-connected MOS for voltage limiting is connected between the connection point and the reference potential. A MOS inverter characterized by connecting transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14023384U JPS6157631U (en) | 1984-09-14 | 1984-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14023384U JPS6157631U (en) | 1984-09-14 | 1984-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157631U true JPS6157631U (en) | 1986-04-18 |
Family
ID=30698588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14023384U Pending JPS6157631U (en) | 1984-09-14 | 1984-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157631U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022115875A (en) * | 2006-09-29 | 2022-08-09 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132242A (en) * | 1983-01-18 | 1984-07-30 | Nec Corp | Output circuit |
-
1984
- 1984-09-14 JP JP14023384U patent/JPS6157631U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132242A (en) * | 1983-01-18 | 1984-07-30 | Nec Corp | Output circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022115875A (en) * | 2006-09-29 | 2022-08-09 | 株式会社半導体エネルギー研究所 | Semiconductor device |