JPS6180842A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6180842A JPS6180842A JP20174784A JP20174784A JPS6180842A JP S6180842 A JPS6180842 A JP S6180842A JP 20174784 A JP20174784 A JP 20174784A JP 20174784 A JP20174784 A JP 20174784A JP S6180842 A JPS6180842 A JP S6180842A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- external connection
- length
- radiating sheet
- longer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に良好な放熱効果が要求
される大出力電力用トランジスタ、半導体集植回路に用
いて好適なものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and is particularly suitable for use in high-output power transistors and semiconductor integrated circuits that require good heat dissipation effects.
大出力電力用トランジスタを例に述べると、放熱効果が
良好であるか否かによって出力電力が決定される、と言
っても過言ではない。従って、半導体装置の放熱板につ
いては種々の提案がなされているのであるが、本発明者
等は、出力電力が例えばＩＷ以上にもなる出力用トラン
ジスタの放熱を念頭におき、種々の技術的検討を行ない
、本発明をなすに至った。Taking a high output power transistor as an example, it is no exaggeration to say that the output power is determined by whether the heat dissipation effect is good or not. Therefore, various proposals have been made regarding heat sinks for semiconductor devices, and the present inventors have carried out various technical studies, keeping in mind the heat dissipation of output transistors whose output power is, for example, greater than IW. As a result, the present invention has been completed.
なお、特開昭５７−１７７５４８号公報には、上記放熱
板に関する提案がなされている。Incidentally, Japanese Patent Application Laid-Open No. 57-177548 proposes the above-mentioned heat sink.
本発明の目的は、外部接続端子を利用して放熱効果を良
好に行ない得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can effectively dissipate heat by using external connection terminals.
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明の概要を簡単に述べれば、
下記のとおシである。A brief summary of the invention disclosed in this application is as follows:
It is as follows.
すなわち、トランジスタについて述べるとコレクタに接
続される外部接続端子に２個の外部接続端子間の長さ以
上の大赦熱板全形成し、放熱効果を良好にする、という
本発明の目的ヲ迂成するものである。In other words, regarding a transistor, the object of the present invention is to form a heat plate on the external connection terminal connected to the collector, the length of which is longer than the length between two external connection terminals, to improve the heat dissipation effect. It is something.
〔実施例−１〕
次に、第１図〜第３図を参照して本発明をスΔ用した半
導体装置の第１実施例を述べる。なお、本実施例では、
大出力電力トランジスタへの適用例全述べる。[Embodiment 1] Next, a first embodiment of a semiconductor device using the present invention will be described with reference to FIGS. 1 to 3. In addition, in this example,
All examples of application to high output power transistors will be described.
先ス、第１図についてフレームの構造から述べると、１
はタブであり、その上面に点線で示すような半導体チッ
プ２が設けられる。なお、半導体チップ２は大出力電力
用の場合に点線で示すように大型になるが、小出力電力
用の場合はその形状が小型になる。タブ１はコレクタ端
子３となる外部接続端子と一体であり、２個のコレクタ
端子３には放熱４が一体に形成されている。First, to describe Figure 1 from the frame structure, 1.
is a tab, and a semiconductor chip 2 as shown by a dotted line is provided on the top surface of the tab. Note that the semiconductor chip 2 becomes large in size as shown by the dotted line when used for high output power, but becomes small in size when used for low output power. The tab 1 is integral with an external connection terminal serving as a collector terminal 3, and a heat radiation 4 is integrally formed on the two collector terminals 3.
ここで注目すべきは、上記放熱板４の大きさであるＯ
すなわち、放熱板４の両側部はコレクタ端子３よりも幅
Ｗだけ大であり、従って２個の端子間の長さ！よりも大
となる。そして、放熱板４が大きくなった分につき、そ
の表面積が大になり、放熱効果が良好になる。What should be noted here is the size O of the heat sink 4. That is, both sides of the heat sink 4 are larger than the collector terminal 3 by the width W, and therefore the length between the two terminals! becomes larger than As the heat dissipation plate 4 becomes larger, its surface area becomes larger and the heat dissipation effect becomes better.
なお、５はエミッタ端子となる外部接続端子であり、６
はペースとなる外部接続端子である。Note that 5 is an external connection terminal that serves as an emitter terminal, and 6
is an external connection terminal that serves as a pace.
そして、上記外部接続端子３．４．５において、後述す
るパッケージ２１に係合する部分には溝部７．８．９が
形成され、さらにリードフレームには空間部１０が設け
られていることよ）パッケージとなる、レジンの上下の
食いつきを良くし水分の浸入全低減して防湿効果を向上
するようになされている。また、外部接続端子５．６に
形成された切り込み部１１．１２は、外部接続端子５．
６の抜は止め用でちり、半導体チップ２に形成されたポ
ンディングパッド（図示せず）と上記外部接続端子５．
６とは、第２図に示すようにワイヤポンディング１３．
１４によって接続される。In the external connection terminal 3.4.5, a groove portion 7.8.9 is formed in the portion that engages with a package 21, which will be described later, and a space portion 10 is further provided in the lead frame.) It is designed to improve the grip between the top and bottom of the resin, which becomes the package, to completely reduce moisture infiltration and improve the moisture-proofing effect. Further, the notch portion 11.12 formed in the external connection terminal 5.6 is formed in the external connection terminal 5.6.
6 is used to prevent removal, and the bonding pad (not shown) formed on the semiconductor chip 2 and the external connection terminal 5.
6 is wire bonding 13. as shown in FIG.
14.
そして、Ｍ２図に示す状態からレジン等によってモール
ドされ、第３図に示す如きパッケージ１１の形状になさ
れる。Then, from the state shown in FIG. M2, it is molded with resin or the like to form the shape of the package 11 as shown in FIG.
上記構造のトランジスタによれば、放熱効果が極めて良
好になり、ＩＷ以上の出力電力が要求される電子回路に
おいても充分使用−することができ する。According to the transistor having the above structure, the heat dissipation effect is extremely good, and it can be used satisfactorily even in electronic circuits that require output power greater than IW.
また、上記溝部７，８．９を設けることにより、外部接
続端子３．５．６を伝わってパッケージ２１内に浸入し
ようとする水分の浸入経路が犬となり、耐湿性を向上さ
せることもできる。Further, by providing the grooves 7, 8.9, there is a path for moisture to enter the package 21 through the external connection terminals 3.5.6, thereby improving moisture resistance.
〔実施例−２〕
次に、第４図ａを参照して本発明の第２実施例を述べる
。なお、上記第１実施例と同一部分には同一の符号を付
し、説明の重ｔ５ｔさけるものとするＯ
第４ａ図に示すように、２個の外部接続端子３には個別
に放熱板４ ａ ｒ ４ ｂが設けられ、これらはそれ
ぞれ外側方向に折り曲げられている。放熱板４ａ、４ｂ
は第１図に魚粕Ａの位置で切断され、しかる後に折り曲
げられたものであり、面積の和は上記放熱板４に等しい
。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG. 4a. Note that the same parts as in the first embodiment are given the same reference numerals to avoid redundant explanation.As shown in FIG. a r 4 b are provided, each of which is bent in an outward direction. Heat sinks 4a, 4b
is cut at the position of fish meal A in FIG. 1 and then bent, and the sum of the areas is equal to the heat sink plate 4.
第４ｂ図、第４Ｃ図は、第１図に示す放熱板より大きな
放熱板を有する実施例の図を示す。4b and 4c show views of an embodiment having a larger heat sink than the heat sink shown in FIG.
そして、放熱板４ａ、４ｂｅ折り曲げ構造にすることに
より、同一６Ｇ造のトランジスタを隣接して実装する易
合に、放熱板と放熱板の接触、言い換えればコレクタと
コレクタとの不測の接触を防止することができる。By bending the heat sinks 4a and 4be, when transistors of the same 6G structure are mounted adjacently, contact between the heat sinks, or in other words, accidental contact between the collectors is prevented. be able to.
〔実施例−３〕 次に、本発明の第３実施例を第５図を参照して述べる。[Example-3] Next, a third embodiment of the present invention will be described with reference to FIG.
なお、本実施例は、本発明をデュアルインライン型のＩ
ＣＫ適用したものである。In this example, the present invention is applied to a dual in-line type I
CK is applied.
第５図に示すように、２個の外部接続端子３１について
放熱板３２が形成されている。放熱板３２は、例えばタ
ブ（図示せず）に接続された端子に設けてもよく、或い
は出力回路の如く大電流の流れる端子に設けてもよい。As shown in FIG. 5, heat sinks 32 are formed for the two external connection terminals 31. As shown in FIG. The heat sink 32 may be provided, for example, at a terminal connected to a tab (not shown), or may be provided at a terminal through which a large current flows, such as an output circuit.
また、図示の位置に限定されるものではなく、他の位置
に設けてよい。すなわち、大形状の放熱板３２を設ける
ことにより、半導体チップ（図示せず）から発生した熱
を効率よく放熱させることができる。Moreover, it is not limited to the illustrated position, and may be provided at other positions. That is, by providing the large heat sink 32, heat generated from a semiconductor chip (not shown) can be efficiently dissipated.
〔効果〕
（１１半導体装置の外部接続端子を利用して大形状の放
熱板を設けることにより、半導体チップの放熱が効率的
に行われるので、大出力電力で半導体装置を駆動するこ
とができる。[Effects] (11) By providing a large-sized heat sink using the external connection terminals of the semiconductor device, heat is efficiently radiated from the semiconductor chip, so the semiconductor device can be driven with high output power.
（２）外部接続端子に放熱板金設けることによシ、外部
接続端子の機械的強度が増し、外部接続端子の不所望の
変形が低減され、実装時の作業効率が向上する。(2) By providing the external connection terminal with a heat dissipation plate, the mechanical strength of the external connection terminal is increased, undesired deformation of the external connection terminal is reduced, and work efficiency during mounting is improved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
例えば、第２実施例に示す如き放熱板４ ａ ＊ ４ｂ
をペース、エミッタ用の外部接続端子に設けてもよい。For example, heat sinks 4a*4b as shown in the second embodiment
may be provided on the external connection terminal for the pace and emitter.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野であるトランジスタ、Ｉ
Ｃについて説明したが、それに限定されるものではない
。In the above explanation, the invention made by the present inventor will be mainly described in the field of application of the transistor, I.
Although the description has been made for C, the present invention is not limited thereto.
例えば、ハイブリッドＩＣに利用することができる。For example, it can be used in a hybrid IC.
第１図は本発明の第１実施例を示すトランジスタのフレ
ームの平面図を示し、
第２図は上記フレームと半導体チップとの関係を示す斜
視図を示し、
第３図は上記トランジスタの外観図を示し、第４ａ図、
第４ｂ図、第４ｃｉｋは本発明の第２実施例を示すトラ
ンジスタの外観図を示し、第５図は本発明の第３実施例
を示すデュアルインライン型ＩＣの外観図を示す。
１・・・タブ、２・・・半導体チップ、３，５，６．３
１・・・外部接続端子、４．４ａ＋ ４ｂ＋ ３２・・
・放熱板、第 ２ 図
第 １ 図
甲
第 ３ 図
第 ４４ 図 第 ４ Ｌ 図
第 ４ｃ 図第 Ｄ 図FIG. 1 shows a plan view of a frame of a transistor showing a first embodiment of the present invention, FIG. 2 shows a perspective view showing the relationship between the frame and a semiconductor chip, and FIG. 3 shows an external view of the transistor. 4a,
4b and 4cik show an external view of a transistor showing a second embodiment of the present invention, and FIG. 5 shows an external view of a dual in-line type IC showing a third embodiment of the present invention. 1...Tab, 2...Semiconductor chip, 3, 5, 6.3
1...External connection terminal, 4.4a+ 4b+ 32...
・Heat sink, Figure 2, Figure 1, Figure A, Figure 3, Figure 44, Figure 4, L
Figure 4c Figure D
Claims (1)
長さ以上の放熱板を形成したことを特徴とする半導体装
置。1. A semiconductor device characterized in that an external connection terminal is provided with a heat sink having a length longer than at least two external connection terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201747A JPH073848B2 (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201747A JPH073848B2 (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6180842A true JPS6180842A (en) | 1986-04-24 |
| JPH073848B2 JPH073848B2 (en) | 1995-01-18 |
Family
ID=16446268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59201747A Expired - Lifetime JPH073848B2 (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073848B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225268A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor device |
| US5518684A (en) * | 1994-03-09 | 1996-05-21 | National Semiconductor Corporation | Method of making a molded lead frame |
| US6297074B1 (en) * | 1990-07-11 | 2001-10-02 | Hitachi, Ltd. | Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof |
| JP2009259961A (en) * | 2008-04-15 | 2009-11-05 | Mitsubishi Electric Corp | Semiconductor device |
| JP2011139108A (en) * | 2011-04-14 | 2011-07-14 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2020120131A (en) * | 2016-07-26 | 2020-08-06 | 株式会社三社電機製作所 | Semiconductor element fitting substrate |
| CN111668107A (en) * | 2012-12-06 | 2020-09-15 | 美格纳半导体有限公司 | Multi-chip package and method of manufacturing the same |
| CN113451243A (en) * | 2020-03-27 | 2021-09-28 | 三菱电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4816756U (en) * | 1971-07-06 | 1973-02-24 | ||
| JPS57177548A (en) * | 1981-04-06 | 1982-11-01 | Int Rectifier Corp | Module for semiconductor device |
| JPS58140647U (en) * | 1982-03-17 | 1983-09-21 | ニチデン機械株式会社 | lead frame |
-
1984
- 1984-09-28 JP JP59201747A patent/JPH073848B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4816756U (en) * | 1971-07-06 | 1973-02-24 | ||
| JPS57177548A (en) * | 1981-04-06 | 1982-11-01 | Int Rectifier Corp | Module for semiconductor device |
| JPS58140647U (en) * | 1982-03-17 | 1983-09-21 | ニチデン機械株式会社 | lead frame |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6297074B1 (en) * | 1990-07-11 | 2001-10-02 | Hitachi, Ltd. | Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof |
| JPH04225268A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor device |
| US5518684A (en) * | 1994-03-09 | 1996-05-21 | National Semiconductor Corporation | Method of making a molded lead frame |
| JP2009259961A (en) * | 2008-04-15 | 2009-11-05 | Mitsubishi Electric Corp | Semiconductor device |
| JP2011139108A (en) * | 2011-04-14 | 2011-07-14 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN111668107A (en) * | 2012-12-06 | 2020-09-15 | 美格纳半导体有限公司 | Multi-chip package and method of manufacturing the same |
| US12057377B2 (en) | 2012-12-06 | 2024-08-06 | Magnachip Semiconductor, Ltd. | Multichip packaged semiconductor device |
| JP2020120131A (en) * | 2016-07-26 | 2020-08-06 | 株式会社三社電機製作所 | Semiconductor element fitting substrate |
| CN113451243A (en) * | 2020-03-27 | 2021-09-28 | 三菱电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP2021158229A (en) * | 2020-03-27 | 2021-10-07 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH073848B2 (en) | 1995-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6479327B2 (en) | Semiconductor device and method for manufacturing the same | |
| JP4698225B2 (en) | Semiconductor die package with drain clip | |
| JP3243116B2 (en) | Semiconductor device | |
| US6650004B1 (en) | Semiconductor device | |
| JP6653199B2 (en) | Semiconductor device | |
| US5299091A (en) | Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same | |
| JPH0758277A (en) | Semiconductor device | |
| JPS6180842A (en) | Semiconductor device | |
| JPS6150387B2 (en) | ||
| JP2010003858A (en) | Semiconductor device | |
| JPH0637217A (en) | Semiconductor device | |
| JPS6378558A (en) | Electronic device | |
| JP3644161B2 (en) | Power semiconductor module | |
| JP5362658B2 (en) | Semiconductor device | |
| CN217719587U (en) | Packaging structure of intelligent power module | |
| JPH0395959A (en) | Lead frame | |
| JP2561470Y2 (en) | Insulation-sealed electronic components | |
| JPS62224049A (en) | Electronic device | |
| JP2005158871A (en) | Packaged semiconductor device | |
| KR200161904Y1 (en) | Heat plate semiconductor package | |
| JPH07130932A (en) | Semiconductor device and its manufacture | |
| JPS58223353A (en) | Semiconductor device | |
| JPH07193173A (en) | Power semiconductor device | |
| JP2002134560A (en) | Semiconductor device | |
| JPS6050355B2 (en) | Lead frame and its manufacturing method |