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JP2010003858A - Semiconductor device - Google Patents

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Publication number
JP2010003858A
JP2010003858A JP2008161144A JP2008161144A JP2010003858A JP 2010003858 A JP2010003858 A JP 2010003858A JP 2008161144 A JP2008161144 A JP 2008161144A JP 2008161144 A JP2008161144 A JP 2008161144A JP 2010003858 A JP2010003858 A JP 2010003858A
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lead
insulating substrate
semiconductor device
patterned insulating
semiconductor chip
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JP4614107B2 (en
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Jiro Shinkai
次郎 新開
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an excellent heat dissipating property and a superior efficiency on a manufacture, also having neither deterioration of a reliability nor generation of a voltage potential in a heat sink because a heating and a partial high temperature are not generated in a junction among a circuit pattern and an electrode and a lead for a semiconductor. <P>SOLUTION: The semiconductor device 1 generating neither heating nor partial heat generation, and deteriorating no reliability is manufactured by using an ultrasonic junction for junctions among an insulating substrate 10 with a pattern and a semiconductor chip 20 and the lead 40. The potential is not generated in the heat sink 30 by preventing a contact with the heat sink 30 of the lead 40, and the semiconductor device 1 having the excellent heat dissipating property is manufactured. The semiconductor device 1 easily joining the insulating substrate 10 with the pattern, the semiconductor chip 20 and the lead 40, and improving the efficiency on the manufacture is manufactured by pinching a part of the lead 40 to projecting sections 10a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、電力用の半導体チップを搭載した半導体装置に関する。   The present invention relates to a semiconductor device on which a power semiconductor chip is mounted.

電力用半導体デバイスが形成された半導体チップを搭載した半導体装置は、樹脂モールドされ、樹脂封止型の半導体装置として各種電子機器に内蔵されている。
電力用半導体デバイスは、大電力を消費することから、半導体装置の製造時及び使用時に発生する熱応力や放熱性に対する対策が重要な課題となる。
従来、樹脂封止型の半導体装置として、半導体の電極とリードフレームとの接合にアルミワイヤーを用いず、リードフレームを直接固着させるものがあった。そのようなものとして、下記特許文献１がある。
下記特許文献１は、電力用半導体装置に関する発明で、半導体の電極にリードフレームを直接固着させ、リードフレームと、半導体素子を載置する基板としての金属ブロックと、半導体素子とをモールド樹脂で一体成形する技術が開示されている。
特開２００３−２６４２６５号公報 A semiconductor device mounted with a semiconductor chip on which a power semiconductor device is formed is resin-molded and incorporated in various electronic devices as a resin-encapsulated semiconductor device.
Since power semiconductor devices consume a large amount of power, measures against thermal stress and heat dissipation generated during the manufacture and use of semiconductor devices are important issues.
Conventionally, as a resin-encapsulated semiconductor device, there is one in which a lead frame is directly fixed without using an aluminum wire for joining a semiconductor electrode and a lead frame. There exists the following patent document 1 as such.
The following Patent Document 1 is an invention related to a power semiconductor device, in which a lead frame is directly fixed to a semiconductor electrode, and the lead frame, a metal block as a substrate on which the semiconductor element is placed, and the semiconductor element are integrated with a mold resin. Techniques for molding are disclosed.
JP 2003-264265 A

上記特許文献１に示す発明では、リードフレームの接合部での疲労破壊が生じにくいというメリットがある。
しかし、半導体の電極とリードフレームとの接合にハンダ若しくは溶接を用いる構成としてある。よってハンダを用いる場合には、加熱工程を繰り返すことにより半導体チップの熱履歴が多くなり、半導体チップに悪影響を与え、半導体装置の信頼性を劣化させるという問題があった。また溶接を用いる場合には、固着箇所に局所的な高温を加えることにより半導体チップに熱応力が発生し、半導体チップに悪影響を与え、半導体装置の信頼性を劣化させるという問題があった。
また金属ブロックを筐体から露出させる場合には、ヒートシンクに電位が生じないようにヒートシンク裏面に絶縁性樹脂シートを敷くため、熱伝導率が悪く、放熱性が悪いという問題があった。 The invention disclosed in Patent Document 1 has an advantage that fatigue failure is less likely to occur at the joint portion of the lead frame.
However, solder or welding is used for joining the semiconductor electrode and the lead frame. Therefore, when solder is used, there is a problem in that the heat history of the semiconductor chip increases by repeating the heating process, which adversely affects the semiconductor chip and degrades the reliability of the semiconductor device. Further, when welding is used, there is a problem that thermal stress is generated in the semiconductor chip by applying a local high temperature to the fixing portion, which adversely affects the semiconductor chip and deteriorates the reliability of the semiconductor device.
Further, when the metal block is exposed from the casing, an insulating resin sheet is laid on the back surface of the heat sink so that no potential is generated in the heat sink, so that there is a problem that heat conductivity is poor and heat dissipation is poor.

そこで本発明は上記従来における問題点を解決し、回路パターン及び半導体の電極とリードとの接合に加熱や局所的な高温を発生させることがないことで、信頼性を劣化させることがなく、また放熱板に電位を生じさせることがないことで放熱性が良く、更に製造効率の良い半導体装置の提供を課題とする。   Therefore, the present invention solves the above-described conventional problems, and does not cause heating or local high temperature at the junction between the circuit pattern and the semiconductor electrode and the lead, so that reliability is not deteriorated. It is an object of the present invention to provide a semiconductor device with good heat dissipation and high manufacturing efficiency because no potential is generated in the heat sink.

本発明の半導体装置は、回路パターンを備えたパターン付絶縁基板と、該パターン付絶縁基板に搭載される半導体チップと、前記パターン付絶縁基板の下面に取り付けられる放熱板と、前記パターン付絶縁基板及び前記半導体チップに接合されるリードとを備えた半導体装置であって、前記パターン付絶縁基板の一部を回路パターンを設けることなく且つ前記放熱板より突出させてなる突出部とすると共に、該突出部に対して前記リードの一部を挟みつけることで該リードを保持してあることを第１の特徴としている。   The semiconductor device of the present invention includes a patterned insulating substrate having a circuit pattern, a semiconductor chip mounted on the patterned insulating substrate, a heat sink attached to the lower surface of the patterned insulating substrate, and the patterned insulating substrate. And a lead that is bonded to the semiconductor chip, wherein a part of the patterned insulating substrate is formed as a protruding portion that protrudes from the heat sink without providing a circuit pattern, The first feature is that the lead is held by sandwiching a part of the lead with respect to the protruding portion.

上記本発明の第１の特徴によれば、回路パターンを備えたパターン付絶縁基板と、該パターン付絶縁基板に搭載される半導体チップと、前記パターン付絶縁基板の下面に取り付けられる放熱板と、前記パターン付絶縁基板及び前記半導体チップに接合されるリードとを備えた半導体装置であって、前記パターン付絶縁基板の一部を回路パターンを設けることなく且つ前記放熱板より突出させてなる突出部とすると共に、該突出部に対して前記リードの一部を挟みつけることで該リードを保持してある構成としてあることから、パターン付絶縁基板にリードを仮止め固定することができる。よって特に製造時において、リードのぐらつきを防止でき、パターン付絶縁基板及び半導体チップに対するリードの接合位置を位置決め容易なものとすることができる。従ってパターン付絶縁基板及び半導体チップとリードとの接合を容易化でき、製造効率を向上させることができる。また半導体装置の強度を向上させることができる。
また回路パターンを設けることなく且つ放熱板より突出させてなる突出部に対してリードの一部を挟みつけることで、リードが放熱板に接触することがない。よって放熱板に電位を生じさせることがない。従って放熱板裏面に絶縁性樹脂シートを敷く必要がなく、放熱性の良い半導体装置とすることができると共に、コスト面に配慮した半導体装置とすることができる。 According to the first aspect of the present invention, a patterned insulating substrate having a circuit pattern, a semiconductor chip mounted on the patterned insulating substrate, a heat sink attached to the lower surface of the patterned insulating substrate, A semiconductor device including the patterned insulating substrate and a lead bonded to the semiconductor chip, wherein a protruding portion is formed by protruding a part of the patterned insulating substrate from the heat sink without providing a circuit pattern. In addition, since the lead is held by sandwiching a part of the lead with respect to the protruding portion, the lead can be temporarily fixed to the insulating substrate with pattern. Therefore, the wobbling of the lead can be prevented especially during manufacturing, and the bonding position of the lead to the patterned insulating substrate and the semiconductor chip can be easily positioned. Therefore, the bonding of the patterned insulating substrate and the semiconductor chip and the leads can be facilitated, and the manufacturing efficiency can be improved. In addition, the strength of the semiconductor device can be improved.
Further, the lead does not come into contact with the heat radiating plate by sandwiching a part of the lead without protruding the circuit pattern and projecting from the heat radiating plate. Therefore, no potential is generated in the heat sink. Therefore, it is not necessary to lay an insulating resin sheet on the back surface of the heat sink, so that a semiconductor device with good heat dissipation can be obtained and a semiconductor device in consideration of cost can be obtained.

また本発明の半導体装置は、上記本発明の第１の特徴に加えて、リードは複数本からなり、該複数本のリードのうちの少なくとも１本について、そのリードの一部をパターン付絶縁基板の突出部に挟みつけてあることを第２の特徴としている。   In addition to the first feature of the present invention, the semiconductor device of the present invention comprises a plurality of leads, and at least one of the plurality of leads is partially patterned with an insulating substrate with a pattern. The second feature is that it is sandwiched between the protrusions.

上記本発明の第２の特徴によれば、上記本発明の第１の特徴による作用効果に加えて、リードは複数本からなり、該複数本のリードのうちの少なくとも１本について、そのリードの一部をパターン付絶縁基板の突出部に挟みつけてある構成としてあることから、半導体装置の製造時において複数本からなるリードは相互に連結されて一体化されているところ、リードのうちの少なくとも１本を突出部に挟みつけることで、パターン付絶縁基板に複数本からなるリードを仮止め固定することができる。よって特に製造時において、複数本からなるリードのぐらつきを防止でき、パターン付絶縁基板及び半導体チップに対する複数本からなるリードの接合位置を位置決め容易なものとすることができる。従ってパターン付絶縁基板及び半導体チップと複数本からなるリードとの接合を容易化でき、製造効率を向上させることができる。   According to the second feature of the present invention, in addition to the function and effect of the first feature of the present invention, the lead comprises a plurality of leads, and at least one of the plurality of leads Since a part is sandwiched between the protruding portions of the patterned insulating substrate, a plurality of leads are interconnected and integrated at the time of manufacturing a semiconductor device. By sandwiching one piece between the protrusions, a plurality of leads can be temporarily fixed to the patterned insulating substrate. Therefore, the wobbling of the plurality of leads can be prevented particularly during manufacturing, and the bonding position of the plurality of leads to the patterned insulating substrate and the semiconductor chip can be easily positioned. Therefore, it is possible to facilitate the bonding of the patterned insulating substrate and the semiconductor chip to the plurality of leads, and to improve the manufacturing efficiency.

また本発明の半導体装置は、上記本発明の第１又は第２の特徴に加えて、リードは３本からなり、第１のリードはパターン付絶縁基板の回路パターンに接合され、第２及び第３のリードは半導体チップの電極面に接合されており、且つパターン付絶縁基板の突出部に対してそれぞれのリードの一部を挟みつけてあることを第３の特徴としている。   In addition to the first or second feature of the present invention, the semiconductor device of the present invention includes three leads, the first lead being bonded to the circuit pattern of the patterned insulating substrate, and the second and second features. The third feature is that the leads 3 are bonded to the electrode surface of the semiconductor chip and a part of each lead is sandwiched between the protruding portions of the patterned insulating substrate.

上記本発明の第３の特徴によれば、上記本発明の第１又は第２の特徴による作用効果に加えて、リードは３本からなり、第１のリードはパターン付絶縁基板の回路パターンに接合され、第２及び第３のリードは半導体チップの電極面に接合されており、且つパターン付絶縁基板の突出部に対してそれぞれのリードの一部を挟みつけてある構成としてあることから、リードを３本とすることで、３極の端子を構成することができる。よってサイリスタ等の大電力パワーデバイスとして有用な半導体装置とすることができる。また３本のそれぞれのリードの一部を突出部に対して挟みつけることで、パターン付絶縁基板に３本全てのリードを仮止め固定することができる。よって特に製造時において、リードのぐらつきを一段と防止でき、パターン付絶縁基板及び半導体チップに対するリードの接合位置を一段と位置決め容易なものとすることができる。従ってパターン付絶縁基板及び半導体チップとリードとの接合を一段と容易化でき、製造効率を向上させることができる。また半導体装置の強度を一段と向上させることができる。   According to the third feature of the present invention, in addition to the function and effect of the first or second feature of the present invention, there are three leads, and the first lead is a circuit pattern of the patterned insulating substrate. Since the second and third leads are joined to the electrode surface of the semiconductor chip, and a part of each lead is sandwiched with the protruding portion of the patterned insulating substrate, By using three leads, a three-pole terminal can be configured. Therefore, a semiconductor device useful as a high-power power device such as a thyristor can be obtained. Further, by sandwiching a part of each of the three leads with the protruding portion, all the three leads can be temporarily fixed to the patterned insulating substrate. Therefore, the wobbling of the leads can be prevented more particularly during the manufacturing, and the positions where the leads are bonded to the patterned insulating substrate and the semiconductor chip can be more easily positioned. Therefore, the bonding between the patterned insulating substrate and the semiconductor chip and the leads can be further facilitated, and the manufacturing efficiency can be improved. Further, the strength of the semiconductor device can be further improved.

また本発明の半導体装置は、上記本発明の第１〜第３の特徴に加えて、パターン付絶縁基板及び半導体チップに対するリードの接合部分は、通常の０．３ｍｍ〜０．６ｍｍリードフレーム厚に対して薄肉に形成してあることを第４の特徴としている。   In addition to the first to third features of the present invention described above, the semiconductor device of the present invention has a normal lead frame thickness of 0.3 mm to 0.6 mm for the lead joint portion to the patterned insulating substrate and the semiconductor chip. On the other hand, the fourth feature is that it is formed thin.

上記本発明の第４の特徴によれば、上記本発明の第１〜第３の特徴による作用効果に加えて、パターン付絶縁基板及び半導体チップに対するリードの接合部分は、通常の０．３ｍｍ〜０．６ｍｍリードフレーム厚に対して薄肉に形成してある構成としてあることから、パターン付絶縁基板及び半導体チップとリードとの接合を容易化することができる。   According to the fourth feature of the present invention, in addition to the operational effects of the first to third features of the present invention, the joint portion of the lead to the patterned insulating substrate and the semiconductor chip is 0.3 mm Since the structure is formed so as to be thin with respect to the thickness of the lead frame of 0.6 mm, the bonding between the patterned insulating substrate and the semiconductor chip and the leads can be facilitated.

また本発明の半導体装置は、上記本発明の第１〜第４の特徴に加えて、パターン付絶縁基板及び半導体チップとリードとの接合は、超音波接合によりなされていることを第５の特徴としている。   In addition to the first to fourth features of the present invention, the semiconductor device of the present invention is characterized in that the patterned insulating substrate and the semiconductor chip and the leads are joined by ultrasonic joining. It is said.

上記本発明の第５の特徴によれば、上記本発明の第１〜第４の特徴による作用効果に加えて、パターン付絶縁基板及び半導体チップとリードとの接合は、超音波接合によりなされている構成としてあることから、パターン付絶縁基板及び半導体チップとリードとの接合に加熱や局所的発熱を発生させることがない。よってパターン付絶縁基板及び半導体チップに熱履歴や熱応力を生じさせることがない。従って熱履歴や熱応力に伴う半導体装置の信頼性劣化を確実に防止することができる。   According to the fifth feature of the present invention, in addition to the effects of the first to fourth features of the present invention, the patterned insulating substrate and the semiconductor chip and the lead are joined by ultrasonic joining. Therefore, heating and local heat generation are not generated in the bonding between the patterned insulating substrate and the semiconductor chip and the leads. Therefore, thermal history and thermal stress are not generated in the patterned insulating substrate and the semiconductor chip. Therefore, it is possible to reliably prevent deterioration of the reliability of the semiconductor device due to thermal history and thermal stress.

また本発明の半導体装置は、上記本発明の第１〜第５の特徴に加えて、同種又は異種のものからなる複数個の半導体チップが１つのパターン付絶縁基板上に搭載されていることを第６の特徴としている。   In addition to the first to fifth features of the present invention, the semiconductor device of the present invention includes a plurality of semiconductor chips of the same type or different types mounted on one patterned insulating substrate. This is the sixth feature.

上記本発明の第６の特徴によれば、上記本発明の第１〜第５の特徴による作用効果に加えて、同種又は異種のものからなる複数個の半導体チップが１つのパターン付絶縁基板上に搭載されている構成としてあることから、複数個の半導体チップを１つのモジュールとする、いわゆるマルチチップモジュールを構成することができる。よって半導体装置の高性能化を図ることができる。   According to the sixth aspect of the present invention, in addition to the functions and effects of the first to fifth aspects of the present invention, a plurality of semiconductor chips of the same or different types are provided on one patterned insulating substrate. Therefore, a so-called multi-chip module in which a plurality of semiconductor chips are used as one module can be configured. Therefore, high performance of the semiconductor device can be achieved.

また本発明の半導体装置は、上記本発明の第１〜第６の特徴に加えて、パターン付絶縁基板と、半導体チップと、放熱板と、リードとが樹脂によりモールドされていることを第７の特徴としている。   In addition to the first to sixth features of the present invention, the semiconductor device of the present invention is characterized in that a patterned insulating substrate, a semiconductor chip, a heat sink, and leads are molded by a resin. It has the characteristics of

上記本発明の第７の特徴によれば、上記本発明の第１〜第６の特徴による作用効果に加えて、パターン付絶縁基板と、半導体チップと、放熱板と、リードとが樹脂によりモールドされている構成としてあることから、半導体装置を構成する各部品を光、水、ほこり等の外界の影響から遮断し、保護できる樹脂封止型の半導体装置とすることができる。   According to the seventh feature of the present invention, in addition to the functions and effects of the first to sixth features of the present invention, the patterned insulating substrate, the semiconductor chip, the heat sink, and the leads are molded with resin. Therefore, each component constituting the semiconductor device can be shielded from the influence of the outside such as light, water, dust, and the like, and a resin-encapsulated semiconductor device that can be protected can be obtained.

本発明の半導体装置によれば、回路パターン及び半導体の電極とリードとの接合に加熱や局所的な高温を発生させることがないことで、信頼性を劣化させることがない半導体装置とすることができる。また放熱板に電位を生じさせることがないので、放熱性の良い半導体装置とすることができる。更にパターン付絶縁基板及び半導体チップとリードとの接合を容易化できることで、製造効率の良い半導体装置とすることができる。   According to the semiconductor device of the present invention, it is possible to obtain a semiconductor device in which reliability is not deteriorated because heating or local high temperature is not generated at the junction between the circuit pattern and the semiconductor electrode and the lead. it can. Further, since no potential is generated in the heat sink, a semiconductor device with good heat dissipation can be obtained. Further, since the bonding between the patterned insulating substrate and the semiconductor chip and the leads can be facilitated, a semiconductor device with high manufacturing efficiency can be obtained.

以下の図面を参照して、本発明の実施の形態に係る半導体装置を説明し、本発明の理解に供する。しかし以下の説明は本発明の実施形態であって、特許請求の範囲に記載の内容を限定するものではない。   A semiconductor device according to an embodiment of the present invention will be described with reference to the following drawings for understanding of the present invention. However, the following description is an embodiment of the present invention, and does not limit the contents described in the claims.

図１は本発明の第１の実施形態に係る半導体装置の平面図である。図２は図１の断面図で、（ａ）はＡ−Ａ線における拡大断面図、（ｂ）はＢ−Ｂ線における拡大断面図である。図３は本発明の第１の実施形態に係る半導体装置の製造工程を説明する図で、パターン付絶縁基板と半導体チップと放熱板とを一体化させた状態でリードをパターン付絶縁基板に挟みつけた状態を示す平面図である。図４は本発明の第２の実施形態に係る半導体装置の平面図である。   FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention. 2A and 2B are cross-sectional views of FIG. 1, in which FIG. 2A is an enlarged cross-sectional view taken along line AA, and FIG. 2B is an enlarged cross-sectional view taken along line BB. FIG. 3 is a diagram for explaining the manufacturing process of the semiconductor device according to the first embodiment of the present invention, in which the leads are sandwiched between the patterned insulating substrate in a state where the patterned insulating substrate, the semiconductor chip, and the heat sink are integrated. It is a top view which shows the state attached. FIG. 4 is a plan view of a semiconductor device according to the second embodiment of the present invention.

まず図１〜図３を参照して、第１の実施形態に係る半導体装置１を説明する。   First, the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

前記半導体装置１は、電力用の半導体チップを搭載した樹脂封止型の半導体装置である。
この半導体装置１は、図１に示すように、パターン付絶縁基板１０と、半導体チップ２０と、放熱板３０と、リード４０と、樹脂５０とで構成される。 The semiconductor device 1 is a resin-encapsulated semiconductor device on which a power semiconductor chip is mounted.
As shown in FIG. 1, the semiconductor device 1 includes a patterned insulating substrate 10, a semiconductor chip 20, a heat sink 30, leads 40, and a resin 50.

前記パターン付絶縁基板１０は、図２に示すように、基板の上面に上面回路パターン１１を備え、基板の下面に下面回路パターン１２を備える絶縁基板である。
また図１、図２（ａ）に示すように、パターン付絶縁基板１０の一部を、回路パターンを設けることなく且つ放熱板３０より突出させてなる突出部１０ａとしてある。 As shown in FIG. 2, the patterned insulating substrate 10 is an insulating substrate having an upper circuit pattern 11 on the upper surface of the substrate and a lower circuit pattern 12 on the lower surface of the substrate.
As shown in FIGS. 1 and 2A, a part of the patterned insulating substrate 10 is a protruding portion 10a that protrudes from the radiator plate 30 without providing a circuit pattern.

なおパターン付絶縁基板１０は、ＡｌＮ、ＳｉＣ、Ｃ−ＢＮ等の高熱伝導率セラミックスによって形成されている。
なおパターン付絶縁基板１０の寸法は、厚みが０．３ｍｍ〜１．０ｍｍ程度、横が５．０ｍｍ〜１０．０ｍｍ程度、縦が４．０ｍｍ〜８．０ｍｍ程度である。 The patterned insulating substrate 10 is made of high thermal conductivity ceramics such as AlN, SiC, C-BN.
The dimension of the patterned insulating substrate 10 is about 0.3 mm to 1.0 mm in thickness, about 5.0 mm to 10.0 mm in width, and about 4.0 mm to 8.0 mm in length.

また上面回路パターン１１及び下面回路パターン１２は、Ｃｕ等の導体材料で形成されている。
なお上面回路パターン１１及び下面回路パターン１２の寸法は、厚みが０．２ｍｍ〜０．４ｍｍ程度、横が４．０ｍｍ〜９．０ｍｍ程度、縦が２．０ｍｍ〜７．０ｍｍ程度である。 The upper circuit pattern 11 and the lower circuit pattern 12 are formed of a conductor material such as Cu.
The upper circuit pattern 11 and the lower circuit pattern 12 have a thickness of about 0.2 mm to 0.4 mm, a width of about 4.0 mm to 9.0 mm, and a length of about 2.0 mm to 7.0 mm.

なお本実施例においては、図１に示すように、パターン付絶縁基板１０の平面視下部を突出部１０ａとする構成であるが、必ずしも平面視下部に限る必要はなく、パターン付絶縁基板１０の一部を回路パターンを設けることなく且つ放熱板３０より突出させてなるものであれば、パターン付絶縁基板１０における突出部１０ａの位置は適宜変更可能である。   In the present embodiment, as shown in FIG. 1, the lower part in the plan view of the patterned insulating substrate 10 is the projecting portion 10 a, but it is not necessarily limited to the lower part in the plan view. The position of the protruding portion 10a in the patterned insulating substrate 10 can be appropriately changed as long as a part of the insulating substrate 10 is provided with no circuit pattern and protruded from the heat sink 30.

前記半導体チップ２０は、ＳｉＣ、ＧａＮ等の基板を用いたＩＧＢＴ等の縦型半導体デバイスである。また図示していないが、半導体チップ２０の上面に電極を備えている。
半導体チップ２０は、金属ハンダ若しくは導電性樹脂を用いて上面回路パターン１１に接合されることでパターン付絶縁基板１０に搭載される。
導電性樹脂としては、エポキシ系、ウレタン系、水性エポキシ系、水性アクリル系等、導電性樹脂として通常用いられるものであれば如何なるものであってもよい。
なお半導体チップ２０の寸法は、厚みが０．１ｍｍ〜０．５ｍｍ程度、横が３．０ｍｍ〜５．０ｍｍ程度、縦が３．０ｍｍ〜５．０ｍｍ程度である。 The semiconductor chip 20 is a vertical semiconductor device such as an IGBT using a substrate such as SiC or GaN. Although not shown, an electrode is provided on the upper surface of the semiconductor chip 20.
The semiconductor chip 20 is mounted on the patterned insulating substrate 10 by being bonded to the upper circuit pattern 11 using metal solder or conductive resin.
The conductive resin may be any epoxy resin, urethane resin, aqueous epoxy resin, aqueous acrylic resin, or the like as long as it is normally used as a conductive resin.
The semiconductor chip 20 has a thickness of about 0.1 mm to 0.5 mm, a width of about 3.0 mm to 5.0 mm, and a length of about 3.0 mm to 5.0 mm.

前記放熱板３０は、Ｎｉめっき、Ａｕめっき等のめっき付Ｃｕ板によって形成された放熱板であり、その一部に樹脂５０による把持力を増強するための開口部３１を有する。
放熱板３０は、金属ハンダ若しくは導電性樹脂を用いて下面回路パターン１２に接合されることでパターン付絶縁基板１０に取り付けられる。
導電性樹脂としては、エポキシ系、ウレタン系、水性エポキシ系、水性アクリル系等、導電性樹脂として通常用いられるものであれば如何なるものであってもよい。
なお放熱板３０の寸法は、厚みが１．０ｍｍ〜２．０ｍｍ程度、横が７．０ｍｍ〜１２．０ｍｍ程度、縦が１２．０ｍｍ〜１６．０ｍｍ程度である。 The heat radiating plate 30 is a heat radiating plate formed of a plated Cu plate such as Ni plating or Au plating, and has an opening 31 for enhancing the gripping force by the resin 50 in a part thereof.
The heat sink 30 is attached to the patterned insulating substrate 10 by being bonded to the lower surface circuit pattern 12 using metal solder or conductive resin.
The conductive resin may be any epoxy resin, urethane resin, aqueous epoxy resin, aqueous acrylic resin, or the like as long as it is normally used as a conductive resin.
The dimensions of the heat sink 30 are about 1.0 mm to 2.0 mm in thickness, about 7.0 mm to 12.0 mm in width, and about 12.0 mm to 16.0 mm in length.

前記リード４０は、外部配線を介して半導体装置１への電源供給を行うためのものである。
このリード４０は、図１に示すように、第１リード４１と、第２リード４２と、第３リード４３の３本のリードで構成され、順にドレイン端子、ゲート端子、ソース端子の３極を構成している。このように３極を有する構成とすることで、半導体装置１をサイリスタ等の大電力パワーデバイスとして有用なものとすることができる。 The lead 40 is for supplying power to the semiconductor device 1 through an external wiring.
As shown in FIG. 1, the lead 40 is composed of three leads, a first lead 41, a second lead 42, and a third lead 43. The lead 40 has a drain terminal, a gate terminal, and a source terminal in order. It is composed. Thus, by setting it as the structure which has 3 poles, the semiconductor device 1 can be made useful as high power power devices, such as a thyristor.

更に図１に示すように、第１リード４１〜第３リード４３は、それぞれ上面リードと下面リードとを有している。
ここで「上面リード」とは、リード４０におけるパターン付絶縁基板１０と接する部分のうちパターン付絶縁基板１０よりも上面に位置するリードを指し、「下面リード」とは、パターン付絶縁基板１０よりも下面に位置するリードを指すものとする。
具体的には、図１に示すように、第１リード４１は、第１上面リード４１ａと第１下面リード４１ｂとを有し、第２リード４２は、第２上面リード４２ａと第２下面リード４２ｂとを有し、第３リード４３は、第３上面リード４３ａと第３下面リード４３ｂとを有している。 Further, as shown in FIG. 1, each of the first lead 41 to the third lead 43 has an upper surface lead and a lower surface lead.
Here, the “upper surface lead” refers to a lead located on the upper surface of the patterned insulating substrate 10 in the portion of the lead 40 in contact with the patterned insulating substrate 10, and the “lower surface lead” refers to the patterned insulating substrate 10. Is also a lead located on the lower surface.
Specifically, as shown in FIG. 1, the first lead 41 includes a first upper surface lead 41a and a first lower surface lead 41b, and the second lead 42 includes a second upper surface lead 42a and a second lower surface lead. 42b, and the third lead 43 has a third upper surface lead 43a and a third lower surface lead 43b.

なお、リード４０はＣｕ板を用いて形成され、表面にはＮｉめっき、Ａｕめっき等が施されている。また詳しく図示していないが、第１リード４１〜第３リード４３は、同一幅且つ同一厚である。また全ての上面リード及び下面リードは、同一幅且つ同一厚であり、更に下面リードについては全て同一長である。   The lead 40 is formed using a Cu plate, and the surface thereof is subjected to Ni plating, Au plating, or the like. Although not shown in detail, the first lead 41 to the third lead 43 have the same width and the same thickness. All the upper surface leads and the lower surface leads have the same width and the same thickness, and the lower surface leads all have the same length.

前記第１リード４１は、ドレイン端子を構成するリードである。
この第１リード４１は、図１、図２（ａ）に示すように、第１上面リード４１ａと、第１下面リード４１ｂとを有している。また図２（ａ）に示すように、第１上面リード４１ａの先端は、その下面を上面回路パターン１１の上面と面接合させてある。これにより、第１上面リード４１ａを通じて上面回路パターン１１へ電源供給を行うことができる。 The first lead 41 is a lead constituting a drain terminal.
As shown in FIGS. 1 and 2A, the first lead 41 includes a first upper surface lead 41a and a first lower surface lead 41b. Further, as shown in FIG. 2A, the front end of the first upper surface lead 41 a has its lower surface joined to the upper surface of the upper circuit pattern 11. As a result, power can be supplied to the upper circuit pattern 11 through the first upper surface lead 41a.

更に図２（ａ）に示すように、第１上面リード４１ａの先端は、その厚みを薄肉なものとする薄肉部Ｌとし、その長さを第１上面リード４１ａと上面回路パターン１１との接合部分よりも長いものとしてある。
ここで「薄肉」とは、薄肉部Ｌの厚みが該薄肉部Ｌを除く第１上面リード４１ａの厚みよりも薄いものであることを示す。
このような構成とすることで、端面１１ａに第１上面リード４１ａが接触することがない。よって上面回路パターン１１において、第１上面リード４１ａが接合部分以外に電位を生じさせることがない。従って放熱性の良い半導体装置１とすることができる。 Further, as shown in FIG. 2 (a), the tip of the first upper surface lead 41a is a thin portion L having a thin thickness, and the length thereof is a junction between the first upper surface lead 41a and the upper circuit pattern 11. It is supposed to be longer than the part.
Here, “thin wall” indicates that the thickness of the thin wall portion L is thinner than the thickness of the first upper surface lead 41a excluding the thin wall portion L.
With this configuration, the first upper surface lead 41a does not come into contact with the end surface 11a. Therefore, in the upper surface circuit pattern 11, the first upper surface lead 41 a does not generate a potential other than the joint portion. Therefore, the semiconductor device 1 with good heat dissipation can be obtained.

前記第２リード４２は、ゲート端子を構成するリードである。
この第２リード４２は、図１に示すように、第２上面リード４２ａと、第２下面リード４２ｂとを有している。また図２（ａ）に示すように、第２上面リード４２ａの先端は、その下面を半導体チップ２０の上面にある図示していない電極と面接合させてある。これにより第２上面リード４２ａを通じて半導体チップ２０へ電源供給を行うことができる。 The second lead 42 is a lead constituting a gate terminal.
As shown in FIG. 1, the second lead 42 has a second upper surface lead 42a and a second lower surface lead 42b. Further, as shown in FIG. 2A, the tip of the second upper surface lead 42 a is surface-bonded to an electrode (not shown) on the upper surface of the semiconductor chip 20. As a result, power can be supplied to the semiconductor chip 20 through the second upper surface lead 42a.

更に図２（ａ）に示すように、第２上面リード４２ａの先端は、その厚みを薄肉なものとする薄肉部Ｍとし、その長さを半導体チップ２０との接合部分よりも長いものとしてある。
ここで「薄肉」とは、薄肉部Ｍの厚みが該薄肉部Ｍを除く第２上面リード４２ａの厚みよりも薄いものであることを示す。
このような構成とすることで、端面２０ａに第２上面リード４２ａが接触することがない。よって半導体チップ２０において、第２上面リード４２ａが接合部分以外に電位を生じさせることがない。よって放熱性の良い半導体装置１とすることができる。 Further, as shown in FIG. 2 (a), the tip of the second upper surface lead 42a is a thin portion M whose thickness is thin, and its length is longer than the joint portion with the semiconductor chip 20. .
Here, “thin wall” indicates that the thickness of the thin wall portion M is thinner than the thickness of the second upper surface lead 42a excluding the thin wall portion M.
With this configuration, the second upper surface lead 42a does not contact the end surface 20a. Therefore, in the semiconductor chip 20, the second upper surface lead 42a does not generate a potential other than the joined portion. Therefore, the semiconductor device 1 with good heat dissipation can be obtained.

前記第３リード４３は、ソース端子を構成するリードである。
この第３リード４３は、図１に示すように、第３上面リード４３ａと、第３下面リード４３ｂとを有している。また図２（ｂ）に示すように、第３上面リード４３ａの先端は、その下面を半導体チップ２０の上面にある図示していない電極と面接合させてある。これにより第３上面リード４３ａを通じて半導体チップ２０へ電源供給を行うことができる。 The third lead 43 is a lead constituting a source terminal.
As shown in FIG. 1, the third lead 43 has a third upper surface lead 43a and a third lower surface lead 43b. As shown in FIG. 2B, the tip of the third upper surface lead 43 a is surface-bonded to an electrode (not shown) on the upper surface of the semiconductor chip 20. As a result, power can be supplied to the semiconductor chip 20 through the third upper surface lead 43a.

更に図２（ｂ）に示すように、第３上面リード４３ａの先端は、その厚みを薄肉なものとする薄肉部Ｎとし、その長さを半導体チップ２０との接合部分よりも長いものとしてある。
ここで「薄肉」とは、薄肉部Ｎの厚みが該薄肉部Ｎを除く第３上面リード４３ａの厚みよりも薄いものであることを示す。
このような構成とすることで、端面２０ｂに第３上面リード４３ａが接触することがない。よって半導体チップ２０において、第３上面リード４３ａが接合部分以外に電位を生じさせることがない。よって放熱性の良い半導体装置１とすることができる。 Further, as shown in FIG. 2B, the tip of the third upper surface lead 43a is a thin portion N whose thickness is thin, and its length is longer than the joint portion with the semiconductor chip 20. .
Here, “thin wall” indicates that the thickness of the thin wall portion N is thinner than the thickness of the third upper surface lead 43a excluding the thin wall portion N.
With such a configuration, the third upper surface lead 43a does not contact the end surface 20b. Therefore, in the semiconductor chip 20, the third upper surface lead 43 a does not generate a potential other than the joint portion. Therefore, the semiconductor device 1 with good heat dissipation can be obtained.

なお本実施例においては、薄肉部Ｌ、Ｍ、Ｎは、その幅、厚み、長さ、形状を同一のものとしてある。   In the present embodiment, the thin portions L, M, and N have the same width, thickness, length, and shape.

また図１、図２（ａ）に示すように、第１リード４１〜第３リード４３の全てにおいて、突出部１０ａに対して上面リードと下面リードとでリードを挟みつけてある。
なおここで及び下記の説明において、図２（ａ）は、図１のＡ−Ａ線の拡大断面図であり、且つ全ての下面リードは同一厚、同一長であることから、第１上面リード４１ａと第１下面リード４１ｂとでリードを突出部１０ａに挟みつけてある状態のみが示されている。しかし本実施例において、第２リード４２及び第３リード４３をパターン付絶縁基板１０に挟みつけてある状態をＡ−Ａ線拡大断面図と同方向の断面の拡大図で表す場合、第１リード４１と同様の形状で示される。よって図２（ａ）において、突出部１０ａに挟みつけてある第１上面リード４１ａ、第１下面リード４１ｂに括弧を付して第２、第３上面リード４２ａ、４３ａと第２、第３下面リード４２ｂ、４３ｂとを示すものとする。 As shown in FIGS. 1 and 2A, in all of the first lead 41 to the third lead 43, the upper surface lead and the lower surface lead are sandwiched between the protrusion 10a.
2A is an enlarged cross-sectional view taken along the line AA of FIG. 1, and all the lower surface leads have the same thickness and the same length. Only a state in which the lead 41a and the first lower surface lead 41b are sandwiched between the protrusions 10a is shown. However, in this embodiment, when the state in which the second lead 42 and the third lead 43 are sandwiched between the patterned insulating substrates 10 is represented by an enlarged view of a cross section in the same direction as the AA line enlarged cross sectional view, the first lead It is shown in the same shape as 41. Therefore, in FIG. 2A, the first upper surface lead 41a and the first lower surface lead 41b sandwiched between the projecting portions 10a are parenthesized, and the second and third upper surface leads 42a and 43a and the second and third lower surface leads. Leads 42b and 43b are shown.

このように突出部１０ａに対して上面リードと下面リードとでパターン付絶縁基板１０を挟みつけてある構成とすることで、第１リード４１〜第３リード４３をパターン付絶縁基板１０に仮止め固定することができる。よって特に製造時において、第１リード４１〜第３リード４３のぐらつきを防止できる。よって上面回路パターン１１と第１上面リード４１ａとの接合位置及び半導体チップ２０の電極と第２、第３上面リード４２ａ、４３ａとの接合位置を位置決め容易なものとすることができる。従って上面回路パターン１１と第１上面リード４１ａとの接合及び半導体チップ２０の電極と第２、第３上面リード４２ａ、４３ａとの接合を容易化でき、製造効率を向上させることができる。また半導体装置１の強度を向上させることができる。   As described above, the first insulating layer 10 is temporarily fixed to the patterned insulating substrate 10 by arranging the patterned insulating substrate 10 between the upper surface lead and the lower surface lead with respect to the protruding portion 10a. Can be fixed. Therefore, the wobbling of the first lead 41 to the third lead 43 can be prevented particularly during manufacturing. Therefore, the bonding position between the upper surface circuit pattern 11 and the first upper surface lead 41a and the bonding position between the electrode of the semiconductor chip 20 and the second and third upper surface leads 42a and 43a can be easily positioned. Therefore, the bonding between the upper surface circuit pattern 11 and the first upper surface lead 41a and the bonding between the electrode of the semiconductor chip 20 and the second and third upper surface leads 42a and 43a can be facilitated, and the manufacturing efficiency can be improved. In addition, the strength of the semiconductor device 1 can be improved.

更に図１、図２（ａ）に示すように、下面リード４１ｂ〜４３ｂの長さは、パターン付絶縁基板１０に下面リードを挟みつけた状態で、下面回路パターン１２及び放熱板３０と下面リードとの間に隙間Ｐが空く長さとしてある。このような構成とすることで、下面リード４１ｂ〜４３ｂが下面回路パターン１２及び放熱板３０と接触することがない。よって放熱板３０に電位を生じさせることがない。従って放熱性が良い半導体装置１とすることができる。   Further, as shown in FIGS. 1 and 2A, the lengths of the lower surface leads 41b to 43b are such that the lower surface circuit pattern 12 and the heat sink 30 and the lower surface leads are sandwiched between the patterned insulating substrate 10 and the lower surface leads. The gap P is long enough. With such a configuration, the lower surface leads 41 b to 43 b do not come into contact with the lower surface circuit pattern 12 and the heat sink 30. Therefore, no potential is generated in the heat sink 30. Therefore, the semiconductor device 1 with good heat dissipation can be obtained.

なお本実施例においては、図２（ａ）に示すように、放熱板３０の端面３０ａを下面回路パターン１２の端面１２ａと面一に取り付ける構成としてあるが、そのような構成としない場合には、端面３０ａと端面１２ａとの何れかのうちで下面リードに近い側との間に隙間Ｐが空くようにすることが必要である。
なお隙間Ｐの長さは、１．０ｍｍ〜１．５ｍｍ程度とすることが望ましい。 In this embodiment, as shown in FIG. 2 (a), the end face 30a of the heat sink 30 is configured to be flush with the end face 12a of the lower surface circuit pattern 12. However, when such a configuration is not used, It is necessary to make a gap P between any one of the end face 30a and the end face 12a and the side close to the lower surface lead.
The length of the gap P is preferably about 1.0 mm to 1.5 mm.

なお上面回路パターン１１と第１上面リード４１ａとの接合及び半導体チップ２０の電極と第２、第３上面リード４２ａ、４３ａとの接合は、超音波接合により行う。超音波接合は微細な超音波振動と加圧力により接合を行うものであることから、このような構成とすることで、接合時に加熱や局所的発熱を発生させることがない。よってパターン付絶縁基板１０及び半導体チップ２０に熱履歴や熱応力を生じさせることがない。従ってハンダや溶接を用いて接合を行う場合に発生する、熱履歴や熱応力に伴う半導体装置１の信頼性の劣化を生じさせることがない。   The bonding between the upper surface circuit pattern 11 and the first upper surface lead 41a and the bonding between the electrode of the semiconductor chip 20 and the second and third upper surface leads 42a and 43a are performed by ultrasonic bonding. Since ultrasonic bonding is performed by fine ultrasonic vibration and pressure, such a configuration prevents heating or local heat generation during bonding. Therefore, thermal history and thermal stress are not generated in the patterned insulating substrate 10 and the semiconductor chip 20. Therefore, the reliability of the semiconductor device 1 is not deteriorated due to thermal history or thermal stress, which occurs when joining is performed using solder or welding.

更に第１〜第３上面リード４１ａ〜４３ａの先端は薄肉部Ｌ、Ｍ、Ｎとしてあることから、接合面に超音波振動を一段と印加させ易くでき、接合を容易化することができる。また接合時間の短縮化を図ることができ、半導体装置１の製造サイクルを効率化できる。また消費電力を抑えることができ、省エネ化を図ることができると共に、コスト面に配慮した半導体装置１とすることができる。   Furthermore, since the tips of the first to third upper surface leads 41a to 43a are thin portions L, M, and N, ultrasonic vibration can be more easily applied to the bonding surfaces, and bonding can be facilitated. Further, the bonding time can be shortened, and the manufacturing cycle of the semiconductor device 1 can be made efficient. In addition, power consumption can be suppressed, energy saving can be achieved, and the semiconductor device 1 can be obtained in consideration of cost.

なお第１リード４１〜第３リード４３の寸法は、幅が０．５ｍｍ〜０．８ｍｍ程度、厚みが０．３ｍｍ〜０．６ｍｍ程度である。
また第１上面リード４１ａ〜第３上面リード４３ａ及び第１下面リード４１ｂ〜第３下面リード４３ｂの寸法は、幅が０．５ｍｍ〜２．０ｍｍ程度、厚みが０．１ｍｍ〜０．５ｍｍ程度である。
また第１下面リード４１ｂ〜第３下面リード４３ｂの長さは、１．０ｍｍ〜１．５ｍｍ程度である。
また薄肉部Ｌ、Ｍ、Ｎの寸法は、幅が０．５ｍｍ〜２．０ｍｍ程度、厚みが、０．１ｍｍ未満、長さが１ｍｍ以上である。 The first lead 41 to the third lead 43 have a width of about 0.5 mm to 0.8 mm and a thickness of about 0.3 mm to 0.6 mm.
The first upper surface lead 41a to the third upper surface lead 43a and the first lower surface lead 41b to the third lower surface lead 43b have a width of about 0.5 mm to 2.0 mm and a thickness of about 0.1 mm to 0.5 mm. is there.
The length of the first lower surface lead 41b to the third lower surface lead 43b is about 1.0 mm to 1.5 mm.
The thin portions L, M, and N have a width of about 0.5 mm to 2.0 mm, a thickness of less than 0.1 mm, and a length of 1 mm or more.

なお本実施例においては、第１リード４１〜第３リード４３は、同一幅且つ同一厚としてある。また全ての上面リード及び下面リードは、同一幅且つ同一厚とし、更に下面リードについては全て同一長としてある。また薄肉部Ｌ、Ｍ、Ｎは、その幅、厚み、長さを同一のものとしてある。しかし勿論、このような構成に限る必要はなく、何れか若しくは何れもが異なるものであってもよい。
またリード４０の本数、形状も必ずしも本実施例のものに限る必要はなく、適宜変更可能である。
例えば薄肉部Ｌ、Ｍ、Ｎの形状を該薄肉部の下面が、薄肉部Ｌ、Ｍ、Ｎを除く上面リード４１ａ〜４３ａの下面と面一となるような構成とすることができる。このような構成とすることで、薄肉部の長さに関係なく、上面リード４１ａ〜４３ａが上面回路パターン１１及び半導体チップ２０の電極との接合部分以外に電位を生じさせることがないものとすることができる。 In the present embodiment, the first lead 41 to the third lead 43 have the same width and the same thickness. All the upper surface leads and lower surface leads have the same width and the same thickness, and the lower surface leads all have the same length. The thin portions L, M and N have the same width, thickness and length. However, of course, it is not necessary to limit to such a configuration, and either one or both may be different.
Further, the number and shape of the leads 40 are not necessarily limited to those of the present embodiment, and can be appropriately changed.
For example, the shape of the thin portions L, M, and N can be configured such that the lower surface of the thin portion is flush with the lower surfaces of the upper surface leads 41a to 43a excluding the thin portions L, M, and N. By adopting such a configuration, the upper surface leads 41a to 43a do not generate a potential other than the junction between the upper surface circuit pattern 11 and the electrode of the semiconductor chip 20 regardless of the length of the thin portion. be able to.

前記樹脂５０は、パターン付絶縁基板１０と、半導体チップ２０と、放熱板３０と、リード４０とをモールドするための樹脂である。
樹脂５０としては、エポキシ樹脂等の熱硬化性樹脂や、ポリエチレン等の熱可塑性樹脂を用い、トランスファー成形によりモールドを行う。このようにトランスファー成形によりモールドを行うことで、モールド作業を簡潔化でき、製造効率を向上させることができる。
なお本実施例においては、図１、図２に示すように、パターン付絶縁基板１０と、半導体チップ２０と、放熱板３０と、端子部分を除くリード４０との全てを樹脂５０でモールドする構成としてあるが、必ずしもこのような構成に限る必要はなく、適宜変更可能である。
例えば、放熱板３０の下面を含む下部を樹脂５０でモールドすることなく露出させるものとすることができる。このような構成とすることで、放熱板３０の下面に更に外部放熱器を取り付ける場合に外部放熱器を確実に放熱板３０に接触させることができる。 The resin 50 is a resin for molding the patterned insulating substrate 10, the semiconductor chip 20, the heat sink 30, and the leads 40.
As the resin 50, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyethylene is used, and molding is performed by transfer molding. By performing the molding by transfer molding in this way, the molding operation can be simplified and the manufacturing efficiency can be improved.
In this embodiment, as shown in FIGS. 1 and 2, the insulating substrate with pattern 10, the semiconductor chip 20, the heat sink 30, and the leads 40 except for the terminal portions are all molded with a resin 50. However, it is not necessarily limited to such a configuration, and can be changed as appropriate.
For example, the lower part including the lower surface of the heat sink 30 can be exposed without being molded with the resin 50. With such a configuration, when an external radiator is further attached to the lower surface of the radiator plate 30, the external radiator can be reliably brought into contact with the radiator plate 30.

次に図３を参照して、半導体装置１の製造工程を説明する。
まずパターン付絶縁基板１０の上面回路パターン１１に半導体チップ２０を金属ハンダ若しくは導電性樹脂で接合する。そしてパターン付絶縁基板１０の下面回路パターン１２に放熱板３０を金属ハンダ若しくは導電性樹脂で接合する。この際、突出部１０ａが生じるように放熱板３０を取り付ける。これによりパターン付絶縁基板１０と、半導体チップ２０と、放熱板３０とが一体化される。そしてリードフレーム６０の第１リード４１〜第３リード４３を突出部１０ａに挟みつける。 Next, the manufacturing process of the semiconductor device 1 will be described with reference to FIG.
First, the semiconductor chip 20 is bonded to the upper surface circuit pattern 11 of the patterned insulating substrate 10 with metal solder or conductive resin. Then, the heat radiating plate 30 is joined to the lower surface circuit pattern 12 of the patterned insulating substrate 10 with metal solder or conductive resin. At this time, the heat sink 30 is attached so that the protruding portion 10a is generated. Thus, the patterned insulating substrate 10, the semiconductor chip 20, and the heat sink 30 are integrated. Then, the first lead 41 to the third lead 43 of the lead frame 60 are sandwiched between the protruding portions 10a.

ここでリードフレーム６０は、図３に示すように、横方向に延びる横フレーム６１と、横フレーム６１同士を連結する縦フレーム６２と、横フレーム６１から放熱板３０に向かって延びる第１リード４１〜第３リード４３と、それぞれのリードを連結する横ダムバー６３と、横フレーム６１同士を連結する縦ダムバー６４とを備えている。
なおリードフレーム６０の厚みは、０．３ｍｍ〜０．６ｍｍ程度である。 Here, as shown in FIG. 3, the lead frame 60 includes a horizontal frame 61 extending in the horizontal direction, a vertical frame 62 connecting the horizontal frames 61, and a first lead 41 extending from the horizontal frame 61 toward the heat dissipation plate 30. -3rd lead 43, the horizontal dam bar 63 which connects each lead | read | reed, and the vertical dam bar 64 which connects horizontal frame 61 comrades are provided.
The lead frame 60 has a thickness of about 0.3 mm to 0.6 mm.

そして第１リード４１〜第３リード４３を突出部１０ａに対して挟みつけた状態で、上面回路パターン１１と第１上面リード４１ａとの接合及び半導体チップ２０の電極と第２、第３上面リード４２ａ、４３ａとの接合を超音波接合により行う。
その後、トランスファーモールドにより図示しないモールド金型のダイキャビティにモールド樹脂５０を流し込んで、パターン付絶縁基板１０と、半導体チップ２０と、放熱板３０と、リード４０とをモールドする。 Then, in a state where the first lead 41 to the third lead 43 are sandwiched with respect to the protruding portion 10a, the bonding between the upper surface circuit pattern 11 and the first upper surface lead 41a, the electrode of the semiconductor chip 20, and the second and third upper surface leads. Bonding with 42a and 43a is performed by ultrasonic bonding.
Thereafter, mold resin 50 is poured into a die cavity of a mold (not shown) by transfer molding to mold the patterned insulating substrate 10, the semiconductor chip 20, the heat sink 30, and the leads 40.

周知の構造として、図示しないモールド金型の上金型及び下金型は、図３に示すリードフレーム６０の横ダムバー６３及び縦ダムバー６４に当接して型締め力が加えられており、その間の領域がモールド金型のダイキャビティとなっている。そして、トランスファーモールド成形時、モールド樹脂５０は、図３に示すリードフレーム６０の横ダムバー６３及び縦ダムバー６４でせき止められる。
トランスファーモールド成形後、図３に一点鎖線で示す切断線Ｑで第１リード４１〜第３リード４３が切断される。これにより図１に示す半導体装置１が得られる。 As a well-known structure, the upper mold and the lower mold (not shown) are in contact with the horizontal dam bar 63 and the vertical dam bar 64 of the lead frame 60 shown in FIG. The region is the die cavity of the mold. At the time of transfer molding, the mold resin 50 is dammed by the horizontal dam bar 63 and the vertical dam bar 64 of the lead frame 60 shown in FIG.
After transfer molding, the first lead 41 to the third lead 43 are cut along a cutting line Q indicated by a one-dot chain line in FIG. Thereby, the semiconductor device 1 shown in FIG. 1 is obtained.

なお本実施例においては、突出部１０ａに対して第１リード４１〜第３リード４３の全ての上面リードと下面リードとを挟みつける構成としたが、必ずしもこのような構成に限る必要はない。
つまり図３に示すように、第１リード４１〜第３リード４３はリードフレーム６０において横ダムバー６３で連結されている。よって突出部１０ａに対して少なくとも１本の上面リードと下面リードとを挟みつけることで、第１リード４１〜第３リード４３の全てをパターン付絶縁基板１０に対して保持させて固定することができる。従って少なくとも１本の上面リードと下面リードとを挟みつけるような構成とするものであれば、適宜変更可能である。 In this embodiment, all the upper surface leads and the lower surface leads of the first lead 41 to the third lead 43 are sandwiched with respect to the protruding portion 10a. However, the present invention is not necessarily limited to such a configuration.
That is, as shown in FIG. 3, the first lead 41 to the third lead 43 are connected by the lateral dam bar 63 in the lead frame 60. Therefore, by sandwiching at least one upper surface lead and lower surface lead with respect to the protruding portion 10a, all of the first lead 41 to the third lead 43 can be held and fixed to the patterned insulating substrate 10. it can. Accordingly, any structure can be used as appropriate as long as at least one upper surface lead and lower surface lead are sandwiched.

また樹脂５０によるモールド前の製造工程は、必ずしも本実施例のものに限る必要はなく、パターン付絶縁基板１０と、半導体チップ２０と、放熱板３０と、第１リード４１〜第３リード４３とを最終的に一体化させることができるものであれば接合順序等は問わない。   Further, the manufacturing process before molding with the resin 50 is not necessarily limited to that of the present embodiment. The patterned insulating substrate 10, the semiconductor chip 20, the heat sink 30, the first lead 41 to the third lead 43, and the like. As long as they can be finally integrated, the joining order is not limited.

次に図４を参照して、第２の実施形態に係る半導体装置２を説明する。
半導体装置２は、上述した半導体装置１に比べてパターン付絶縁基板１０に複数個の半導体チップ２０を搭載するものである。またリード４０の形状及び半導体チップ２０とリード４０との接合位置を変形したものである。その他の構成については、半導体装置１と同様である。同一部材、同一機能を果たすものには同一番号を付し以下説明を省略する。
半導体チップ２０としては、同種又は異種のものからなる複数個とすることができる。
このようにパターン付絶縁基板１０に複数個の半導体チップ２０を搭載することで、複数個の半導体チップ２０を１つのモジュールとする、いわゆるマルチチップモジュールを構成することができる。よって半導体装置２の高性能化を図ることができる。 Next, a semiconductor device 2 according to the second embodiment will be described with reference to FIG.
The semiconductor device 2 has a plurality of semiconductor chips 20 mounted on the patterned insulating substrate 10 as compared with the semiconductor device 1 described above. Further, the shape of the lead 40 and the joining position between the semiconductor chip 20 and the lead 40 are modified. Other configurations are the same as those of the semiconductor device 1. The same member and the same function are designated by the same reference numerals and the description thereof will be omitted.
The semiconductor chip 20 may be a plurality of the same type or different types.
By mounting a plurality of semiconductor chips 20 on the patterned insulating substrate 10 in this manner, a so-called multichip module in which the plurality of semiconductor chips 20 are made into one module can be configured. Therefore, high performance of the semiconductor device 2 can be achieved.

本発明は樹脂封止型の半導体装置として、ハイブリッド車、電気自動車等の各種機器に用いられる電子部品に利用することができる。   INDUSTRIAL APPLICABILITY The present invention can be used as a resin-encapsulated semiconductor device for electronic components used in various devices such as hybrid vehicles and electric vehicles.

本発明の第１の実施形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 図１の断面図で、（ａ）はＡ−Ａ線における拡大断面図、（ｂ）はＢ−Ｂ線における拡大断面図である。2A is an enlarged cross-sectional view taken along line AA, and FIG. 2B is an enlarged cross-sectional view taken along line BB. 本発明の第１の実施形態に係る半導体装置の製造工程を説明する図であり、パターン付絶縁基板と半導体チップと放熱板とを一体化させた状態でリードをパターン付絶縁基板に挟みつけた状態を示す平面図である。It is a figure explaining the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention, and the lead was pinched | interposed into the insulating substrate with a pattern in the state which integrated the insulating substrate with a pattern, a semiconductor chip, and a heat sink. It is a top view which shows a state. 本発明の第２の実施形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention.

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体装置
１０ パターン付絶縁基板
１０ａ 突出部
１１ 上面回路パターン
１１ａ 端面
１２ 下面回路パターン
１２ａ 端面
２０ 半導体チップ
２０ａ 端面
２０ｂ 端面
３０ 放熱板
３０ａ 端面
３１ 開口部
４０ リード
４１ 第１リード
４１ａ 第１上面リード
４１ｂ 第１下面リード
４２ 第２リード
４２ａ 第２上面リード
４２ｂ 第２下面リード
４３ 第３リード
４３ａ 第３上面リード
４３ｂ 第３下面リード
５０ 樹脂
６０ リードフレーム
６１ 横フレーム
６２ 縦フレーム
６３ 横ダムバー
６４ 縦ダムバー
Ｌ 薄肉部
Ｍ 薄肉部
Ｎ 薄肉部
Ｐ 隙間
Ｑ 切断線 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 10 Patterned insulating substrate 10a Protruding part 11 Upper surface circuit pattern 11a End surface 12 Lower surface circuit pattern 12a End surface 20 Semiconductor chip 20a End surface 20b End surface 30 Heat sink 30a End surface 31 Opening 40 Lead 41 First lead 41a First lead 41a Upper surface lead 41b First lower surface lead 42 Second lead 42a Second upper surface lead 42b Second lower surface lead 43 Third lead 43a Third upper surface lead 43b Third lower surface lead 50 Resin 60 Lead frame 61 Horizontal frame 62 Vertical frame 63 Horizontal dam bar 64 Vertical dam bar L Thin part M Thin part N Thin part P Gap Q Cutting line

Claims (7)

回路パターンを備えたパターン付絶縁基板と、該パターン付絶縁基板に搭載される半導体チップと、前記パターン付絶縁基板の下面に取り付けられる放熱板と、前記パターン付絶縁基板及び前記半導体チップに接合されるリードとを備えた半導体装置であって、前記パターン付絶縁基板の一部を回路パターンを設けることなく且つ前記放熱板より突出させてなる突出部とすると共に、該突出部に対して前記リードの一部を挟みつけることで該リードを保持してあることを特徴とする半導体装置。   A patterned insulating substrate having a circuit pattern, a semiconductor chip mounted on the patterned insulating substrate, a heat sink attached to the lower surface of the patterned insulating substrate, and the patterned insulating substrate and the semiconductor chip. A part of the insulating substrate with a pattern is formed as a protruding part that protrudes from the heat radiating plate without providing a circuit pattern, and the lead with respect to the protruding part. A semiconductor device characterized in that the lead is held by sandwiching a part of the semiconductor device. リードは複数本からなり、該複数本のリードのうちの少なくとも１本について、そのリードの一部をパターン付絶縁基板の突出部に挟みつけてあることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor according to claim 1, wherein the lead comprises a plurality of leads, and at least one of the plurality of leads has a part of the lead sandwiched between the protruding portions of the patterned insulating substrate. apparatus. リードは３本からなり、第１のリードはパターン付絶縁基板の回路パターンに接合され、第２及び第３のリードは半導体チップの電極面に接合されており、且つパターン付絶縁基板の突出部に対してそれぞれのリードの一部を挟みつけてあることを特徴とする請求項１又は２に記載の半導体装置。   There are three leads, the first lead is bonded to the circuit pattern of the patterned insulating substrate, the second and third leads are bonded to the electrode surface of the semiconductor chip, and the protruding portion of the patterned insulating substrate The semiconductor device according to claim 1, wherein a part of each lead is sandwiched between. パターン付絶縁基板及び半導体チップに対するリードの接合部分は、通常の０．３ｍｍ〜０．６ｍｍリードフレーム厚に対して薄肉に形成してあることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。   4. The bonding portion of the lead to the patterned insulating substrate and the semiconductor chip is formed thinner than a normal lead frame thickness of 0.3 mm to 0.6 mm. A semiconductor device according to 1. パターン付絶縁基板及び半導体チップとリードとの接合は、超音波接合によりなされていることを特徴とする請求項１〜４の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating substrate with pattern and the semiconductor chip and the lead are joined by ultrasonic joining. 同種又は異種のものからなる複数個の半導体チップが１つのパターン付絶縁基板上に搭載されていることを特徴とする請求項１〜５の何れか１項に記載の半導体装置。   6. The semiconductor device according to claim 1, wherein a plurality of semiconductor chips made of the same kind or different kinds are mounted on one patterned insulating substrate. パターン付絶縁基板と、半導体チップと、放熱板と、リードとが樹脂によりモールドされていることを特徴とする請求項１〜６の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating substrate with pattern, the semiconductor chip, the heat sink, and the leads are molded with resin.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014132897A1 (en) * 2013-03-01 2014-09-04 住友電気工業株式会社 Semiconductor device
KR20190037722A (en) * 2017-09-29 2019-04-08 현대자동차주식회사 POWER MODULE FOR Vehicle
KR20200145091A (en) * 2019-06-20 2020-12-30 제엠제코(주) Semiconductor package
CN112992818A (en) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 Power device and manufacturing method thereof
US20210238408A1 (en) * 2018-10-29 2021-08-05 Henkel Ag & Co. Kgaa Thermal conductive potting composition

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5273372A (en) * 1975-12-17 1977-06-20 Hitachi Ltd Terminal for hyb ic substrate
JPS5895656U (en) * 1981-12-23 1983-06-29 日本電気株式会社 Hybrid integrated circuit device
JPS58111949U (en) * 1982-01-25 1983-07-30 日本電気株式会社 Hybrid integrated circuit device
JPS59124789A (en) * 1983-01-05 1984-07-18 日本電気株式会社 Hybrid integrated circuit unit
JPS62195159A (en) * 1986-02-21 1987-08-27 Hitachi Tobu Semiconductor Ltd Hybrid integrated circuit device and lead frame used for manufacture thereof
JPH06224359A (en) * 1993-01-22 1994-08-12 Toppan Printing Co Ltd Semiconductor device
JP2007251218A (en) * 2007-07-06 2007-09-27 Renesas Technology Corp Manufacturing method of power mosfet and power mosfet
JP2008098678A (en) * 2008-01-04 2008-04-24 Toshiba Corp Semiconductor device, and its manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5273372A (en) * 1975-12-17 1977-06-20 Hitachi Ltd Terminal for hyb ic substrate
JPS5895656U (en) * 1981-12-23 1983-06-29 日本電気株式会社 Hybrid integrated circuit device
JPS58111949U (en) * 1982-01-25 1983-07-30 日本電気株式会社 Hybrid integrated circuit device
JPS59124789A (en) * 1983-01-05 1984-07-18 日本電気株式会社 Hybrid integrated circuit unit
JPS62195159A (en) * 1986-02-21 1987-08-27 Hitachi Tobu Semiconductor Ltd Hybrid integrated circuit device and lead frame used for manufacture thereof
JPH06224359A (en) * 1993-01-22 1994-08-12 Toppan Printing Co Ltd Semiconductor device
JP2007251218A (en) * 2007-07-06 2007-09-27 Renesas Technology Corp Manufacturing method of power mosfet and power mosfet
JP2008098678A (en) * 2008-01-04 2008-04-24 Toshiba Corp Semiconductor device, and its manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014132897A1 (en) * 2013-03-01 2014-09-04 住友電気工業株式会社 Semiconductor device
JP2014170800A (en) * 2013-03-01 2014-09-18 Sumitomo Electric Ind Ltd Semiconductor device
KR20190037722A (en) * 2017-09-29 2019-04-08 현대자동차주식회사 POWER MODULE FOR Vehicle
KR102445515B1 (en) 2017-09-29 2022-09-21 현대자동차주식회사 POWER MODULE FOR Vehicle
US20210238408A1 (en) * 2018-10-29 2021-08-05 Henkel Ag & Co. Kgaa Thermal conductive potting composition
KR20200145091A (en) * 2019-06-20 2020-12-30 제엠제코(주) Semiconductor package
KR102199360B1 (en) * 2019-06-20 2021-01-06 제엠제코(주) Semiconductor package
CN112992818A (en) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 Power device and manufacturing method thereof

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