JPS6050355B2 - Lead frame and its manufacturing method - Google Patents
Lead frame and its manufacturing methodInfo
- Publication number
- JPS6050355B2 JPS6050355B2 JP55161176A JP16117680A JPS6050355B2 JP S6050355 B2 JPS6050355 B2 JP S6050355B2 JP 55161176 A JP55161176 A JP 55161176A JP 16117680 A JP16117680 A JP 16117680A JP S6050355 B2 JPS6050355 B2 JP S6050355B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- metal layer
- layer
- support part
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は、電力用樹脂封止型半導体装置等で使用され
るリードフレームならびにこれを製造する方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame used in a resin-sealed semiconductor device for electric power, and a method for manufacturing the lead frame.
樹脂封止型半導体装置は、通常リードフレームを用い
て半導体素子組立構体を形成し、これを樹”レ、 、
−↓１１、、Ｕル、ル １ｊ、−・・・ウーー身 、フ
、ｎ、握μｎ仁 封止型半導体装置における１つの問
題は、成型用樹脂の熱伝導度が低いため、動作時に発生
する熱の放散が十分でなく、電力損失が１０ワット程度
に達する電力用半導体装置の実現が困難なことである。Resin-sealed semiconductor devices usually use a lead frame to form a semiconductor element assembly structure, which is then assembled into a tree.
-↓11,,Uru,ru 1j,-...woou body, fu, n, grip μn jin One problem with encapsulated semiconductor devices is that the thermal conductivity of the molding resin is low, which occurs during operation. However, it is difficult to realize a power semiconductor device with power loss of about 10 watts due to insufficient heat dissipation.
この問題を解決するため、半導体基板の支持部となる部
分に放熱板を兼ねさせるようにしたリードフレームが提
案されるに至つている。 第１図は、かかるリードフレ
ームの構造をパワートランジスタ用リードフレームを例
に示す図であり、ａは平面図、をは第１図ａのＢ−Ｂ線
に沿つた断面図である。In order to solve this problem, lead frames have been proposed in which a portion that serves as a support for a semiconductor substrate also serves as a heat sink. FIG. 1 is a diagram showing the structure of such a lead frame using a lead frame for a power transistor as an example, in which a is a plan view and FIG. 1 is a cross-sectional view taken along the line B--B in FIG. 1a.
このリードフレームは熱伝導の良好な銅などの金属板に
打ち抜き加工を施すとによつて形成されるものであり、
移送ピッチを決定する孔１をもつ共通連結部２から、同
一方向へ向けて導出されるコレクタリード３、ベースリ
ード４ならびにエミッタリード５ならびにコレクタ リ
ード３の先端部に繋る基板支持部６とによつてトランジ
スタの組立部が形成される。このトランジスタの組立部
が共通連結部２によつて多数連結１され、また、個々の
基板支持部の変形を避けるために、基板支持部相互間が
連結細条７によつて連結された構造となつている。なお
、８は、完成した樹脂封止型半導体装置を外部放熱体へ
とりつける際にねじ特が挿通される孔である。 第１図
をで示すように、リード部の厚みにくらべて基板支持部
６の厚みが大きくなつているが、これは基板支持部６を
放熱板そのものとして積極極に利用とする意図に基くも
のである。This lead frame is formed by punching a metal plate such as copper, which has good thermal conductivity.
A collector lead 3, base lead 4, and emitter lead 5 are led out in the same direction from a common connection part 2 having a hole 1 that determines the transfer pitch, and a substrate support part 6 is connected to the tip of the collector lead 3. A transistor assembly is thus formed. A large number of transistor assembly parts 1 are connected by a common connection part 2, and in order to avoid deformation of each substrate support part, the substrate support parts are connected to each other by connection strips 7. It's summery. Note that 8 is a hole into which a screw is inserted when attaching the completed resin-sealed semiconductor device to an external heat sink. As shown in Figure 1, the thickness of the board support part 6 is larger than the thickness of the lead part, but this is based on the intention of actively utilizing the board support part 6 as a heat sink itself. It is.
このような構造とするためには、打ち抜き加工を施すリ
ードフレーム用原板の厚みを予め２部分で異らせておけ
ばよい。第２図は、上記のリードフレームを用いて形成
した樹脂封止型パワートランジスタの断面構造を示す図
であり、基板支持部６へトランジスタ素子９を接着する
とともに、トランジスタ素子９の電極とベースリードな
らびエミッタリードとの間を金属細線１０て接続したの
ち、樹脂１１によつて封止して樹脂封止型パワートラン
ジスタが形成されているが、図示するように、基板支持
部６の裏面ならひに先端部分を露呈させる関係を成立さ
せて樹脂封止がなされている。In order to obtain such a structure, the thickness of the lead frame original plate to be punched may be made different between the two parts in advance. FIG. 2 is a diagram showing the cross-sectional structure of a resin-sealed power transistor formed using the lead frame described above, in which the transistor element 9 is bonded to the substrate support 6, and the electrodes and base leads of the transistor element 9 are bonded together. A resin-sealed power transistor is formed by connecting the metal wire 10 and the emitter lead with a thin metal wire 10, and then sealing it with a resin 11. The resin sealing is performed by establishing a relationship in which the tip portion is exposed.
従来のリードフレームでは、上記のように基板支持部６
が放熱板を兼ねるところとなり、したがつて、この部分
で効果的に熱の放熱がなされる。In the conventional lead frame, as described above, the substrate support part 6
This portion also serves as a heat sink, and therefore heat is effectively radiated from this portion.
また、基板支持部６の露呈す裏面を外部放熱体へ熱的に
結合させるならば、放熱効果はよソー層大きくなる。か
しながら、従来のリードフレームでは基板支持部６がト
ランジスタのコレクタと電気的に接続されているため、
外部放熱体Ｓェへの取り付けに際して両者間電気的に絶
縁する必要があり、両者間に別体の絶縁シートＳ２など
を介在させることが不可避となる。Furthermore, if the exposed back surface of the substrate support portion 6 is thermally coupled to an external heat radiator, the heat radiation effect will be increased. However, in the conventional lead frame, the substrate support part 6 is electrically connected to the collector of the transistor.
When attaching to the external heat sink SE, it is necessary to electrically insulate the two, and it is inevitable that a separate insulating sheet S2 or the like be interposed between the two.
図示したリードフレームによれば、電力損失に関す問題
の解決ははかれるものの、上記のようにこのリードフレ
ームを用いて形成した半導体装置の実装時にわずられし
さが生じるばかりでなく、絶縁シートＳ２の位置決めが
不正確であると絶縁性か損われ、短絡事故を起すおそれ
もあつた。Although the illustrated lead frame solves the problem of power loss, it not only makes it difficult to mount a semiconductor device formed using this lead frame as described above, but also makes it difficult to mount the insulating sheet S2. Inaccurate positioning could lead to loss of insulation, which could lead to short circuits.
本発明は、以上説明した従来のリードフレームに存在し
た問題点の排除を意図してなされたものである。かかる
問題点を排除することのリードフレームとして、出願人
は、リードフレームの基板支持部を第１の金属層、絶縁
層ならびに第２の金属層からなる積層板となすとともに
、第１の金属層を基板支持部外まて延在させ、の金属層
により外部リード部をも形成するようにした構造を別途
提案している。第３図は、かかるリードフレームの構造
を示す図であり、ａは平面図、ｂは第３図ａ（７）Ｂ−
Ｂ線に沿つた断面図である。The present invention has been made with the intention of eliminating the problems that existed in the conventional lead frames described above. In order to create a lead frame that eliminates such problems, the applicant has created a substrate support portion of the lead frame as a laminate consisting of a first metal layer, an insulating layer, and a second metal layer, and the first metal layer We have separately proposed a structure in which the metal layer extends outside the substrate support part and also forms an external lead part. FIG. 3 is a diagram showing the structure of such a lead frame, in which a is a plan view and b is a plan view of FIG.
It is a sectional view along the B line.
このリードフレームの構造ならびに形状は、第１図で示
した従来のものと殆んど同じであるが、基板支持部６が
第１の金属層１２、絶縁層１３ならびに第２の金属層１
４の積層構造となつている点で従来のリードフレームと
異なつている。このリードフレームによれば、トランジ
スタ素子が接着される第１の金属層１２と樹脂封止のの
ちに絶縁層と接する側とは反対側の面が露呈される第２
の金属層１４とが電気的に絶縁されるところとなる。し
たがつて、完成したパワートランジスタを外部放熱体へ
熱的に結合する場合、第２の金属層の露呈面を直接外部
放熱体へ当接させてよく、従来のもののように、絶縁シ
ートＳ２を介在させることが不要と昭なる。ところで、
かかるリードフレームを形成する場合、上記のように積
層された原板に打ち抜き加工を施す工程で積層部に切断
処理が施され、さらに、樹脂封止が完了したのちトラン
ジスタを個々に分離する工程でも積層部の一部てある連
結細条７に切断処理が施される。これらの切断処理で用
いる切断刃（金型も含む）の切れがすこふる良好な場合
はさして問題はないが、切断刃の切れが鈍つた場合には
、金属層のかえりによつて絶縁性能が損われるおそれが
ある。第４図は、この状態を説明するための図てあり、
たとえば、切断刃１５により第１の金属層１２の側から
矢印×で示すように第２の金属層１４の方向へ向けて積
層体を切断すると、第１の金属層１２の切断部にかえり
１６が発生し、このかえり１６が金属層１３を越えて第
２の金属層１４にまで達したときには金属層１３を設け
両金属層間を絶縁することの効果が失われるところとな
る。The structure and shape of this lead frame are almost the same as the conventional one shown in FIG.
It differs from conventional lead frames in that it has a laminated structure of 4 layers. According to this lead frame, the first metal layer 12 to which the transistor element is bonded and the second metal layer 12 whose surface opposite to the side contacting the insulating layer is exposed after resin sealing.
The metal layer 14 is electrically insulated. Therefore, when thermally coupling the completed power transistor to an external heat sink, the exposed surface of the second metal layer may be brought into direct contact with the external heat sink, and the insulating sheet S2, as in the conventional case, may be brought into contact with the external heat sink. It turns out that there is no need to intervene. by the way,
When forming such a lead frame, the laminated parts are cut in the process of punching the laminated original plates as described above, and the laminated parts are also cut in the process of separating the transistors individually after resin encapsulation is completed. A cutting process is performed on the connecting strip 7 that is part of the section. If the cutting blade (including the mold) used in these cutting processes is sharp enough, there is no problem, but if the cutting blade becomes dull, the insulation performance may deteriorate due to the burrs of the metal layer. There is a risk of damage. Figure 4 is a diagram for explaining this state.
For example, when the laminate is cut with the cutting blade 15 from the first metal layer 12 side toward the second metal layer 14 as shown by the arrow When this burr 16 crosses the metal layer 13 and reaches the second metal layer 14, the effect of providing the metal layer 13 and insulating the two metal layers is lost.
本発明は第３図で示した積層形リードフレームに発生す
るおそれがあつた上記の絶縁不良の問題を完全に排除す
ることのできるリードフレームとその製造方法を提供す
るものであり、以下に図面を参照して詳しく説明する。
第５図は、本発明のリードフレームの一実施例を示す図
であり、ａは平面図、ｂは第５図ａ（７）Ｂ一Ｂ線に沿
つた断面図である。The present invention provides a lead frame and its manufacturing method that can completely eliminate the above-mentioned problem of poor insulation that could occur in the laminated lead frame shown in FIG. Please refer to the following for a detailed explanation.
FIG. 5 is a diagram showing an embodiment of the lead frame of the present invention, in which a is a plan view and b is a sectional view taken along line B--B in FIG. 5 a (7).
図示するように、本発明のリードフレームの構造は、第
３図で示した積層形リードフレームをその基本とするも
のではあるが、第１の金属層１２の基板支持部にスリツ
ト１７を形成することによつてこの部分を半導体基板接
着部６１と非接着部６２の２部分に分割した構造となつ
ている。スリット１７は切断処理で発生するかえりによ
つて第１金属層１２と第２金属層間に短絡事故が生じて
もこの影響が半導体基板接着部６１に及ばないように作
用するものである。As shown in the figure, the structure of the lead frame of the present invention is based on the laminated lead frame shown in FIG. Particularly, this part is divided into two parts, a semiconductor substrate bonded part 61 and a non-bonded part 62. The slit 17 acts to prevent the semiconductor substrate adhesive portion 61 from being affected even if a short circuit occurs between the first metal layer 12 and the second metal layer due to burrs generated during the cutting process.
すなわちスリット１７を形成したことにより半導体基板
接着部６１が非接着部６２と電気的に分離されているた
め、上記のような短絡事故が発生しても、この影響は非
接着部でとどまるところとなる。第６図は、以上説明し
た本発明のリードフレームを用いて形成したパワートラ
ンジスタの断面構造を示す図であり、トランジスタ素子
９は半導体基板接着部６１へ接着されている。In other words, by forming the slit 17, the semiconductor substrate bonded part 61 is electrically isolated from the non-bonded part 62, so even if the above-mentioned short circuit occurs, the effect will be limited to the non-bonded part. Become. FIG. 6 is a diagram showing a cross-sectional structure of a power transistor formed using the lead frame of the present invention described above, in which the transistor element 9 is bonded to the semiconductor substrate bonding portion 61.
この接着に際して大切なことは、トランジスタ素子９を
接着する鑞材が接着訊スリット１７の内部へ流入するこ
とを防ぐことである。このためには、例えば、半導体基
板接着部６１内の半導体基板接着領域を凹状となし、鑞
材の流れを阻止する配慮を払えばよい。なお、樹脂１１
による封止は従来のものと同様になされるが、この工程
でスリット１７は樹脂１１によつて埋められ、したがつ
て、半導体基板接着部６１の分離は完全なものとなる。
ところて、第１の金属層１２は第５図ｂから明らかなよ
うにリードフレームの外部リードならびに共通連結部の
形成材料としても利用されるものてあり、その厚みは外
部リードの厚みを考慮して決定されている。What is important in this bonding is to prevent the solder material for bonding the transistor element 9 from flowing into the adhesive slit 17. To this end, for example, the semiconductor substrate bonding region within the semiconductor substrate bonding portion 61 may be made concave to prevent the flow of the solder material. In addition, resin 11
Sealing is performed in the same manner as in the conventional method, but in this step the slit 17 is filled with the resin 11, so that the semiconductor substrate bonding portion 61 is completely separated.
By the way, as is clear from FIG. 5b, the first metal layer 12 is also used as a material for forming the external leads and the common connection part of the lead frame, and its thickness is determined by taking into account the thickness of the external leads. It has been decided that
また、絶縁層１３はトランジスタ素子を接着するための
熱処理工程て特性が劣化するものであつてはならない。
この要件をみたす絶縁層としては、例えばポリイミド樹
脂層が挙げられる。第７図は、以上説明したリードフレ
ームを形成する方法を説明するための図てあり、先す第
７図ａで示すように所定の部分にスリット１７が形成さ
れ、第１の金属層となる金属板１８と第２の金属層とな
る金属板１９を準備する。Further, the characteristics of the insulating layer 13 must not be deteriorated during the heat treatment process for bonding the transistor elements.
An example of an insulating layer that satisfies this requirement is a polyimide resin layer. FIG. 7 is a diagram for explaining the method of forming the lead frame described above. As shown in FIG. A metal plate 18 and a metal plate 19 that will become the second metal layer are prepared.
金属板１８の幅１１と厚みｔ１は得ようとするリードフ
レームの共通連結部、外部リードならびに基板支持部の
長さと外部リードの厚みを考慮して決定する。また、金
属板１９の幅１２と厚み！は、基板支持部の長さとリー
ドフレームとして完成したときの基板支持部の厚みを考
慮して決定する。次いて金属板１８と１９を絶縁層を形
成する樹脂、例えばポリイミド樹脂層によつて貼合せ、
第７図ｂで示すよに一部が３層構造を呈するリードフレ
ーム原板を形成する。The width 11 and thickness t1 of the metal plate 18 are determined in consideration of the lengths and thicknesses of the common connection portion, external leads, and substrate support portion of the lead frame to be obtained. Also, the width 12 and thickness of the metal plate 19! is determined by considering the length of the substrate support and the thickness of the substrate support when completed as a lead frame. Next, the metal plates 18 and 19 are bonded together with a resin forming an insulating layer, such as a polyimide resin layer,
As shown in FIG. 7b, a lead frame original plate having a three-layer structure in part is formed.
図中１３はポリイミド樹脂層である。こののち、打ち抜
き加工を施すことによつて第７図ｃで示すように本発明
のリードフレームが形成される。このようにして得られ
る本発明のリードフレームでは、トランジスタ素子が接
着される第１の金”属層１２が絶縁層１３によつて第２
の金属層１４と電気的に絶縁されるとともに、第１の金
属層の基板支持部６がスリット１７で２分されている。In the figure, 13 is a polyimide resin layer. Thereafter, the lead frame of the present invention is formed by punching as shown in FIG. 7c. In the lead frame of the present invention obtained in this manner, the first metal layer 12 to which the transistor element is bonded is connected to the second metal layer 12 by the insulating layer 13.
The substrate supporting portion 6 of the first metal layer is electrically insulated from the metal layer 14 of the first metal layer, and the substrate support portion 6 of the first metal layer is divided into two by a slit 17.
したがつて、このリードフレームを用いるとともに、第
６図で示したような関係を成立させて樹脂封止して得た
樹脂封止型パワー絶縁層の裏面に露呈する第２の金属層
１４は、トランジスタ素子とは電気的に絶縁されるとこ
ろとなり、この面を外部放熱体へ直接当接されるところ
となり、この面を外部放熱体へ直接当接させても何等支
障をきたさず、また積層部に対する切断時にかえりが生
じ、切断面で短絡事故が生じて何等問題にならない。な
お、絶縁層１３の厚みは、これが厚すぎると放熱特性面
て支障があり、一方、薄すぎると絶縁性の面で支障があ
る。Therefore, the second metal layer 14 exposed on the back surface of the resin-sealed power insulating layer obtained by using this lead frame and resin-sealing with the relationship shown in FIG. , it is electrically insulated from the transistor element, and this surface is in direct contact with the external heat sink, and there is no problem even if this surface is brought into direct contact with the external heat sink, and the laminated When cutting the part, burrs occur and short circuits occur at the cut surface, which does not cause any problems. Note that if the thickness of the insulating layer 13 is too thick, it will cause problems in terms of heat dissipation characteristics, and on the other hand, if it is too thin, it will cause problems in terms of insulation.
このため、厚みの選定はこれらを考慮する必要があり、
実験的には５０〜１１０μｍ程度の範囲で好結果が得ら
れた。また、絶縁層１３に気泡あるいはピンホールがあ
ると電気的絶縁性が損われるところとなるが、絶縁層１
３の一部を同種の絶縁シートとするならばかかる不都合
を排除する面ですぐれた効果の発揮されることが確認さ
れた。さらに、第１の金属層と第２の金属層の絶縁層に
接する側の表面を酸化あるいは窒化させるとにより、電
気絶縁性のよソー層の向上がはかられること、同面を予
め粗面化しておくことにより、積層体の接着力が高める
ことも確認された。Therefore, it is necessary to take these into consideration when selecting the thickness.
Experimentally, good results were obtained in the range of about 50 to 110 μm. Furthermore, if there are bubbles or pinholes in the insulating layer 13, the electrical insulation will be impaired;
It has been confirmed that if part of 3 is made of the same type of insulating sheet, an excellent effect will be exhibited in terms of eliminating such inconveniences. Furthermore, by oxidizing or nitriding the surfaces of the first metal layer and the second metal layer that are in contact with the insulating layer, the electrically insulating properties of the layer can be improved; It was also confirmed that the adhesion of the laminate could be increased by adding
以上説明したところから明らかなように、本発明によれ
ば、積層形リードフレームがもつ本質的な効果、すなわ
ち実装時のわずわらしさをことごとく排除した電力用樹
脂封止型半導体装置の実現に加えて、積層形としたこと
によつて打ち抜き加工時あるいは樹脂成型ののちに施さ
れる連結細条の切断時に発生するおそれがある短絡事故
の防止効果が奏されるとろとなる。As is clear from the above explanation, according to the present invention, it is possible to achieve the essential effect of a stacked lead frame, that is, to realize a resin-encapsulated power semiconductor device that completely eliminates the hassle of mounting. In addition, the laminated structure has the effect of preventing short-circuit accidents that may occur during punching or when cutting the connecting strips after resin molding.
なお、以上の実施例ではパワートランジスタ用リードフ
レームを例示したが、本発明はこの例に限られるもので
はない。In addition, although the lead frame for power transistors was illustrated in the above embodiment, the present invention is not limited to this example.
また、スリット１７の形状も図示したコ字形である必要
はなく、スリット１７の効果が奏される範囲で種々の形
状とすることが可能である。Furthermore, the shape of the slit 17 does not necessarily have to be the U-shape shown in the figure, but can be made into various shapes as long as the effect of the slit 17 is achieved.
第１図ａは従来のリードフレームの構造を示す平面図、
同ｂはＡＯＢ−Ｂ線断面図、第２図は同リードフレーム
を用いて形成された樹脂封止型パワートランジスタの実
装工程の断面図、第３図ａは本発明の基本となるリード
フレームの構造を示す平面図、同ｂは同ａ（７）Ｂ−Ｂ
線断面図、第４図は切断処理で生じるかえりで短絡事故
が生じる様子を示す図、第５図ａは本発明の一実施例に
かかるリードフレームの構造を示す平面図、同ｂは同ａ
（７）Ｂ−Ｂ線断面図、第６図は同リードフレームを用
いて形成した樹脂封止型パワートランジスタの断面図、
第７図Ａ，ｂ，ｃは本発明のリードフレームの製造方法
を説明するための製造工程図である。
１・・・・・・移送ピッチ決定用孔、２・・・・・・共
通連結部、３・・・・・・コレクタリード、４・・・・
・・ベースリード、５・・・・・・エミッタリード、６
・・・・・・基板支持部、６１・・・・・半導体基板接
着部、６２・・・・・非接着部、７・・・・・・連絡細
条、８・・・・・とりつけ用孔、９・・・・・・トラン
ジスタ素子、１０・・・・・・金属細線、１１・・・・
・・樹脂、１２・・・・・・第１の金属層、１３・・・
・・・絶縁層、１４・・・・・・第２の金属層、１５・
・・・・切断刃、１６・・かえり、１７・・・・スリッ
ト、１８，１９・・・・・リードフレーム原板形成用の
金属板。FIG. 1a is a plan view showing the structure of a conventional lead frame;
Figure 2b is a cross-sectional view taken along the line AOB-B, Figure 2 is a cross-sectional view of the mounting process of a resin-sealed power transistor formed using the same lead frame, and Figure 3a is a cross-sectional view of the lead frame which is the basis of the present invention. A plan view showing the structure, b is a (7) B-B
4 is a diagram illustrating how a short circuit occurs due to burrs that occur during the cutting process; FIG. 5a is a plan view showing the structure of a lead frame according to an embodiment of the present invention; and FIG.
(7) A cross-sectional view taken along the line B-B; FIG. 6 is a cross-sectional view of a resin-sealed power transistor formed using the same lead frame;
FIGS. 7A, b, and c are manufacturing process diagrams for explaining the lead frame manufacturing method of the present invention. 1...Transfer pitch determining hole, 2...Common connection part, 3...Collector lead, 4...
...Base lead, 5...Emitter lead, 6
...Substrate support part, 61...Semiconductor substrate bonding part, 62...Non-bonding part, 7...Connection strip, 8...For mounting Hole, 9...transistor element, 10...metal thin wire, 11...
...Resin, 12...First metal layer, 13...
...Insulating layer, 14...Second metal layer, 15.
... Cutting blade, 16 ... Burr, 17 ... Slit, 18, 19 ... Metal plate for forming lead frame original plate.
Claims (1)
に第２の金属層の３層構造積層板で形成されるとともに
、前記半導体基板支持部の第１の金属層がスリットによ
り半導体基板接着部と非接着部の２部に分割され、さら
に外部リード部ならびに共通連結部が前記第１の金属層
の延在部で形成されていることを特徴とするリードフレ
ーム。 ２ 基板支持部、外部リード部および共通連結部の３部
分を打ち抜くことが可能な面積をもちかつ前記基板支持
部打ち抜き領域にスリットが穿設された第１の金属板の
前記基板支持部打ち抜き領域部分に、耐熱性絶縁接着材
を用いて第２の金属板を貼着して基板支持部打ち抜き領
域部分のみ３層構造とした原板を形成し、次いで、同原
板に前記３層構造部分内のスリットに打ち抜き線が交る
ことのない打ち抜き加工を施すことを特徴とするリード
フレームの製造方法。[Scope of Claims] 1. The semiconductor substrate support part is formed of a three-layer laminated plate including a first metal layer, an insulating layer, and a second metal layer, and the first metal layer of the semiconductor substrate support part The lead frame is divided into two parts, a semiconductor substrate bonded part and a non-bonded part, by a slit, and an external lead part and a common connection part are formed by an extended part of the first metal layer. 2. The board support part punching area of the first metal plate, which has an area capable of punching out the three parts of the board support part, the external lead part, and the common connection part, and has a slit in the board support part punching area. A second metal plate is attached to the part using a heat-resistant insulating adhesive to form an original plate having a three-layer structure only in the punched area of the substrate support part, and then, on the original plate, the parts in the three-layer structure part are attached. A method for manufacturing a lead frame, characterized by performing a punching process such that punch lines do not intersect with slits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161176A JPS6050355B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161176A JPS6050355B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5784158A JPS5784158A (en) | 1982-05-26 |
| JPS6050355B2 true JPS6050355B2 (en) | 1985-11-08 |
Family
ID=15730022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55161176A Expired JPS6050355B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050355B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0622761U (en) * | 1992-04-21 | 1994-03-25 | 有限会社ウルトラモダンエクウィップメント | Disposable lighter case |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002274783A (en) * | 2001-03-19 | 2002-09-25 | Furukawa Co Ltd | Outrigger device for on-vehicle crane |
-
1980
- 1980-11-14 JP JP55161176A patent/JPS6050355B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0622761U (en) * | 1992-04-21 | 1994-03-25 | 有限会社ウルトラモダンエクウィップメント | Disposable lighter case |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5784158A (en) | 1982-05-26 |
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